Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
The MCP7940M is a I2C RTC chip. The new driver uses the dev/i2c API to
support the RTC. It is written with the intention, that the driver can
be adapted to other RTCs with a similar register layout by just
replacing the initialization function.
The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
This change causes NOR writes to be broken according to page boundaries.
Writes across page boundaries cause the writes beyond the boundary to
fail silently. This also introduces a new function that will explicitly
write pages.
Add <rtems/termiosdevice.h> which does not depend on <rtems/libio.h> to
provide rtems_termios_device_context and rtems_termios_device_handler.
For polled serial device drivers, this removes a header file dependency
to the full file system support.
This imports the full xil_exception.h instead of an empty stub. This is
required for some Xilinx drivers. The imported files adhere to the
current VERSION file.
This makes xil/sleep.h a stub to prevent multiple differing definitions
of sleep functions from toolchain and local headers. The non-standard
sleep definitions were not in use and can be added later if needed.
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.
Xilinx's upstream ILP32 xil_cache.h header is out of date and broken.
This provides a copy of the LP64 header in place of the ILP32 header
since the LP64 header includes all the correct types to work with either
data model.
This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
This support code is necessary for many Xilinx-provided bare metal device
drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for
all of these architectures is kept under bsps/include due to multiple
architecture variants being supported which requires complex logic in
the build system. The imported files are and should be able to remain
unmodified. Import information is kept in bsps/shared/xil/VERSION.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
