Add Thread_Control::is_in_the_air field if configured for SMP. This
helps to simplify the extract operation and avoids superfluous
inter-processor interrupts. Move the processor allocation step into the
enqueue operation.
Add and use _Scheduler_simple_smp_Get_highest_ready(). Add and use
_Scheduler_SMP_Get_lowest_scheduled().
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
This patch enables unlimited model in POSIX key manger and have a decent
runtime on POSIX key searching, adding and deleting operations. Memory
overhead is lower than current implementation when the size of key and key
value becomes big.
ISR locks are low-level locks to protect critical sections accessed by
threads and interrupt service routines.
On single processor configurations the ISR locks degrade to simple ISR
disable/enable sequences. No additional storage or objects are
required.
This synchronization primitive is supported on SMP configurations. Here
SMP locks are used.
Move implementation specific parts of object.h and object.inl into new
header file objectimpl.h. The object.h contains now only the
application visible API.
Move implementation specific parts of tqdata.h, threadq.h and
threadq.inl into new header file threadqimpl.h. The threadq.h contains
now only the application visible API.
Delete tqdata.h.
Move implementation specific parts of thread.h and thread.inl into new
header file threadimpl.h. The thread.h contains now only the
application visible API.
Remove superfluous header file includes from various files.
Move implementation specific parts of prioritybitmap.h and
prioritybitmap.inl into new header file prioritybitmapimpl.h. The
prioritybitmap.h contains now only the application visible API.
Move content of bitfield.h into prioritybitmapimpl.h.
Move implementation specific parts of stack.h and stack.inl into new
header file stackimpl.h. The stack.h contains now only the application
visible API.
