This adds generic JFFS2 interworking code that allows JFFS2 to be used
on top of any flashdev backend. It currently only supports NOR flashdev
backends.
This removes the headers imported from the embeddedsw repository in
favor of a much thinner shim. This also removes the complicated build
system configuration necessary to support use of these headers. The
primary reason for removal is that certain external Xilinx libraries
also require use of these headers and this causes version mismatches and
header conflicts that can be avoided.
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)
Update #5002.
Make the initialization and polled functions independent of the Termios
context. This helps to implement the kernel I/O support without a dependency
on the Termios framework.
Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to <bsp/irq-generic.h>. Canonicalize the
<bsp/irq.h> includes.
Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).
Provide stub implementations for i386 to fix build errors.
Add an opportunistic page cache to the xnandpsu driver since it does not
implement partial page reads and common filesystem access patterns
perform multiple reads from the same page. This has been seen to provide
a 10x speedup to read speeds and a 2x speedup on first initialization
when used with JFFS2.
Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
This imports the TTC hardware definitions for the triple timer counters
on various Xilinx platforms. This was imported as specified in the
VERSION file in this commit.
The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
This change causes NOR writes to be broken according to page boundaries.
Writes across page boundaries cause the writes beyond the boundary to
fail silently. This also introduces a new function that will explicitly
write pages.
Add <rtems/termiosdevice.h> which does not depend on <rtems/libio.h> to
provide rtems_termios_device_context and rtems_termios_device_handler.
For polled serial device drivers, this removes a header file dependency
to the full file system support.
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.
This adds Xilinx's driver for the Xilinx NAND controller embedded in the
ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. This has been added
to the hardware ZynqMP BSPs since QEMU does not support emulation of
this peripheral. This driver supports polled operation only. The
imported files are and should be able to remain unmodified. Import
information is kept in bsps/shared/dev/nand/VERSION.
Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1
enable registers. This fixes the build for the AArch32 target.
Add BSP options which define the initial values of CPU Interface registers.
