181 Commits

Author SHA1 Message Date
Joel Sherrill
a265d69094 bsps/riscv: Move SPDX line to top of file
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
2025-08-11 19:06:32 +00:00
Joel Sherrill
0a5890c623 bsps/riscv/niosv/flash/altera_epcq_driver.c: Variable unused after read
The driver was reading from memory and GCC warning that the value
read was ignored. Added annotation to indicate this was intentional.
2025-07-24 18:23:01 -05:00
Kinsey Moore
4f5723e125 bsps: Remove post-link config files
These files are not currently useful in the tree and will be replaced by
a different post-link tool.

Updates rtems/programs/gsoc#74
2025-07-09 21:05:37 -05:00
Matteo Concas
5e0a68d3ab bsps/noelv: Fix using console in polled mode
Before, the console driver needed
`BSP_CONSOLE_USE_INTERRUPTS` to be defined or it
would not build. The intent was to use polled
mode if the macro was equal to zero.

This change makes it so interrupt mode is used if
the macro is defined and polled mode is used if
the macro is not defined.
2025-06-26 02:40:05 +00:00
Lucian Silistru
7ec18af86c bsps/riscv: use lw to load _SMP_Processor_configured_maximum on rv64
_SMP_Processor_configured_maximum is 32 bit, LREG macro is ld on rv64,
lw on rv32. Changing the load to explicit 'lw' to always load 4 bytes

Closes #5251
2025-05-29 22:49:11 +00:00
Amar Takhar
70ad0926b0 readme: Convert to ASCII
Convert table to ASCII
2025-05-20 13:05:47 -04:00
Joel Sherrill
3a5069ced6 niosvc10lp/../altera_avalon_sysid_qsys_regs.h: Convert to UNIX format
Accidentally committed in DOS format.
2025-03-19 13:38:36 +00:00
Kinsey Moore
52c3ddfc3c riscv: Correct spelling of hart
RISC-V cores are called harts and have a hart ID (hartid).
2025-02-07 14:59:53 +00:00
Gedare Bloom
c72816751a griscv: add license based on git history 2025-02-07 00:48:23 +00:00
Gedare Bloom
c6ad57b102 riscv: fix FDT loads during work area init
Fixes #5139
2024-10-31 23:14:09 +00:00
Purva Yeshi
eaaeebedda riscv/beaglevfire: Rename 'bvf' to 'beaglevfire' 2024-10-25 21:23:23 +00:00
Francescodario Cuzzocrea
9d45cf1b44 riscv: add bsp for beagle v fire
Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
2024-10-25 21:23:23 +00:00
Francescodario Cuzzocrea
0e3792edbf riscv: Work area size based on /memory node in fdt
* It is not granted that we will always access to natually aligned
   access. So, before handling endianess do byte-a-byte load using
   the appropriate libfdt function to avoid unaligned access issues

Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
2024-10-25 21:23:23 +00:00
Kevin Kirspel
e9957cd8e3 riscv/niosv: Adding a new NIOS V BSP to RISC-V 2024-10-25 13:49:36 +00:00
Sebastian Huber
f43042cd06 bsps: Move <bsp/linker-symbols.h> to shared
Move architecture-independent items to a shared <bsp/linker-symbols.h>.
Allow architectures to customize it through <bsp/linker-symbols-arch.h>.
2024-10-11 01:27:48 +02:00
Sebastian Huber
e81a5db70e score: Remove unused _CPU_Fatal_halt()
Update #5067.
2024-08-23 14:54:37 +00:00
Sebastian Huber
5ea022ff12 bsps/riscv: Provide bsp_reset()
Update #5067.
2024-08-23 14:54:37 +00:00
Sebastian Huber
ab8817ca03 rtems: Add get/set interrupt priorities
Add directives to get and set the priority of an interrupt vector.

Implement the directives for the following BSP families:

* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq

Implement the directives for the following interrupt controllers:

* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)

Update #5002.
2024-05-10 13:26:22 +00:00
Sebastian Huber
5b0e355ed7 bsps: Move declarations to <bsp/irq-generic.h>
Move declarations of bsp_interrupt_get_affinity() and
bsp_interrupt_set_affinity() to <bsp/irq-generic.h>.  Canonicalize the
<bsp/irq.h> includes.

Implement bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
needed (usually RTEMS_SMP).

Provide stub implementations for i386 to fix build errors.
2024-03-27 20:20:38 +01:00
Sebastian Huber
1eed6f8bfc bsps: Avoid unused argument in clock interrupt
Pass the parameter of the clock interrupt handler to
Clock_driver_support_at_tick() and Clock_driver_timecounter_tick().  This makes
it possible to use the interrupt handler argument in clock drivers.

Use the interrupt handler provided by Clock_driver_support_install_isr() to
avoid local delarations of Clock_isr().

Update #4862.
2024-03-20 16:34:09 +01:00
Sebastian Huber
8fdecf6c55 bsps: Use new APBUART register block API 2023-07-14 12:21:33 +02:00
Sebastian Huber
2d71cba033 bsps/grlib: Add generated headers
Close #4828.
2023-07-14 09:11:19 +02:00
Sebastian Huber
4e3e9df1b4 bsps: Remove uses of BSP-specific interrupt API
Update #3269.
2023-06-16 07:30:50 +02:00
Sebastian Huber
bcef89f236 Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
2023-05-20 11:05:26 +02:00
Alan Cudmore
26853a0624 bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This patch adds support for the Kendryte K210 RISC-V BSP variant.
The SoC uses the existing Interrupt Controller, Timer, and console UART.
It only needs SoC specific initialization and an embedded device tree binary
similar to the polarfire SoC BSP.

Updates #4876
2023-03-28 14:04:04 -05:00
Alan Cudmore
ca1c4e70f5 bsps/riscv: add device tree source and device tree blob header for k210 bsp variant
This patch adds the k210 device tree source and the corresponding
device tree blob encoded in the header which is used for the
embedded device tree blob for the Kendryte K210 BSP variant.

Updates #4876
2023-03-28 14:04:04 -05:00
Sebastian Huber
11cc51ef27 bsps/riscv: Use per-CPU mtimecmp in clock driver
Use the mtimecmp from the PLIC/CLINT initialization in the clock driver.  This
register is defined by the device tree and does not assume a fixed mapping.
2023-03-17 07:25:34 +01:00
Sebastian Huber
cbddf5decd bsps/riscv: Fix riscv_get_hart_index_by_phandle()
Take a non-zero RISCV_BOOT_HARTID into account.
2023-03-17 07:25:34 +01:00
Sebastian Huber
e5233057be bsps/riscv: Make SMP start more robust
In SMP configurations, check that we run on a configured processor.  If not,
then there is not much that can be done since we do not have a stack available
for this processor.  Just loop forever in this case.  Do this in assemlby to
ensure that no stack memory is used.
2023-03-17 07:25:23 +01:00
Sebastian Huber
bb465c8548 doxygen: Add Doxygen files to a group
Update #3707.
2023-02-16 08:27:09 +01:00
Sebastian Huber
6136e28bf9 clockdrv: Add clock driver implementation group
Use standard wording in Clock Driver related files.

Update #3706.
2023-01-24 09:56:53 +01:00
Sebastian Huber
10ee41a8a3 tm27: Avoid function pointer casts
Add TM27_USE_VECTOR_HANDLER to select the interrupt handler type used by
the <tm27.h> implementation.

Close #4820.
2023-01-24 09:56:53 +01:00
Sebastian Huber
d46366a2e7 riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORT
Low-end configurations may want to have the HTIF support removed.
Enable the option by default.  Fix formatting.  Fix node validity
checks.

Updates #4779.
2023-01-12 08:15:58 +01:00
Hesham Almatary
88b80a5fd0 RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT
Updates #4779
2022-12-23 09:21:14 +00:00
Sebastian Huber
71d1acd41d bsps/irq: Rename handler in dispatch table
The name handler table was a bit misleading after the last rework.
Rename it to distach table.  Update the documentation accordingly.

Update #4769.
2022-12-02 10:25:39 +01:00
Sebastian Huber
d9c7db505c bsps/riscv: Simplify PLIC support
In uniprocessor configurations there is no need to take interrupt affinities
into account for the interrupt vector enable/disable.
2022-11-23 07:56:12 +01:00
Sebastian Huber
d448aa4d05 bsps/riscv: Fix PLIC enable register count 2022-11-23 07:56:12 +01:00
Sebastian Huber
733d9b750c bsps/riscv: Add riscv_plic_cpu_0_init()
Move boot processor initialization of PLIC to separate function.
2022-11-23 07:56:12 +01:00
Sebastian Huber
5756a6af10 bsps/riscv: Fix bsp_fdt_map_intr()
The interrupt numbers in the device tree are usually PLIC interrupts.  Map the
number to the vector number associated with an external interrupt.
2022-11-23 07:56:12 +01:00
Daniel Cederman
18a181c267 bsps/riscv: Change license to BSD-2 for files with Gaisler copyright
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.

Updates #3053.
2022-11-14 11:00:14 +01:00
Sebastian Huber
77c8d822c3 bsps/riscv: Fix software interrupt dispatching
In SMP configurations, there may be no software interrupt handler
installed when the software interrupt is processed.  Add the new
interrupt handler dispatch variant
bsp_interrupt_handler_dispatch_unlikely() for this special case.
2022-11-11 16:38:25 +01:00
Sebastian Huber
908ffc7a93 bsps/noel: Fix interrupt support 2022-11-11 16:38:25 +01:00
Sebastian Huber
bfdfc979fd bsps/riscv: Fix PLIC enable register count
Each PLIC enable register has 32 bits, so we have to divide by 32.
2022-11-10 15:17:07 +01:00
Sebastian Huber
e4210d5a08 bsps/riscv: Skip init on not configured processors 2022-11-10 08:55:38 +01:00
Sebastian Huber
3e5ccdd34e bsps/riscv: Simplify riscv_plic_init() 2022-11-10 08:55:38 +01:00
Sebastian Huber
d2bac3d730 bsps/riscv: Simplify riscv_clint_init() 2022-11-10 08:55:38 +01:00
Sebastian Huber
ccf09a6e16 bsps/riscv: Add tm27 support 2022-11-10 08:55:38 +01:00
Sebastian Huber
ba53a177ab bsps/riscv: Always dispatch software interrupts
This helps to run the interrupt API validation tests.
2022-11-10 08:55:38 +01:00
Sebastian Huber
47d156d706 bsps/riscv: bsp_interrupt_get/set_affinity()
Provide bsp_interrupt_get_affinity() and bsp_interrupt_set_affinity() only if
RTEMS_SMP is enabled.  Replace fatal error with a status code.
2022-11-10 08:55:38 +01:00
Sebastian Huber
1bf1c779e1 bsps/riscv: bsp_interrupt_raise_on()
Implement bsp_interrupt_raise_on() and bsp_interrupt_raise().
2022-11-10 08:55:38 +01:00