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Update from Eric Norum.

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This commit is contained in:
Joel Sherrill
1997-04-16 17:45:35 +00:00
parent 34217ccf59
commit f8f370b645
8 changed files with 423 additions and 183 deletions
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42
c/src/lib/libbsp/m68k/gen68360/README
View File

@@ -24,15 +24,16 @@
# MC68360 systems. The choice of hardware is made at the final link-edit # MC68360 systems. The choice of hardware is made at the final link-edit
# phase by setting the Makefile LDFLAGS definition appropriately. # phase by setting the Makefile LDFLAGS definition appropriately.
# #
# Decisions to be made a link-edit time include: # Decisions made at compile time include:
# - The version of hardware on which the application is to run. # - If the CPU is a member of the 68040 family, the BSP is
# This is selected by defining the MC68360HardwareType variable. # compiled for a generic 68040/68360 system as described
# Supported values are: # in Chapter 9 of the MC68360 User's Manual.
# MC68360HardwareTypeMotorolaGeneric (default) # - If the preprocessor symbol M68360_ATLAS_HSB is defined,
# MC68360HardwareTypeAtlasHSB # the BSP is compiled for an Atlas HSB card.
# To select the Atlas Computer Equipment HSB, # - Otherwise, the BSP is compiled for a generic 68360 system
# --defsym MC68360HardwareType=MC68360HardwareTypeAtlasHSB # as described in Chapter 9 of the MC68360 User's Manual.
# #
# Decisions to be made a link-edit time are:
# - The amount of dynamic RAM in the system. This value applies # - The amount of dynamic RAM in the system. This value applies
# only to hardware versions which support different sizes of RAM. # only to hardware versions which support different sizes of RAM.
# The default value is 4 Mbytes. To specify 16 Mbytes of memory, # The default value is 4 Mbytes. To specify 16 Mbytes of memory,
@@ -45,13 +46,15 @@
# To choose a heap size of 256 kbytes, # To choose a heap size of 256 kbytes,
# --defsym HeapSize=0x40000 # --defsym HeapSize=0x40000
# #
# - The Ethernet address for network boot proms.
BSP NAME: gen68360 BSP NAME: gen68360 or gen68360_040
BOARD: Generic 68360 as described in Motorola MC68360 User's Manual BOARD: Generic 68360 as described in Motorola MC68360 User's Manual
BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB) BOARD: Atlas Computer Equipment Inc. High Speed Bridge (HSB)
BOARD: Atlas Computer Equipment Inc. Advanced Communication Engine (ACE) BOARD: Atlas Computer Equipment Inc. Advanced Communication Engine (ACE)
BOARD: Arnewsh SBC360 68040/68360 card
BUS: none BUS: none
CPU FAMILY: Motorola CPU32+ CPU FAMILY: Motorola CPU32+, Motorola 68040
COPROCESSORS: none COPROCESSORS: none
MODE: not applicable MODE: not applicable
@@ -100,8 +103,8 @@ NEXTSTEP 3.3 (Intel and Motorola), Solaris 2.5
gcc-2.7.2 gcc-2.7.2
binutils-2.6 binutils-2.6
Verification Verification (Standalone 68360)
------------ -------------------------------
Single processor tests: Passed Single processor tests: Passed
Multi-processort tests: not applicable Multi-processort tests: not applicable
Timing tests: Timing tests:
@@ -290,8 +293,13 @@ Processor Users' Manual. The salient features of this hardware are:
Console serial port on SMC1 Console serial port on SMC1
Ethernet interface on SCC1 Ethernet interface on SCC1
The board support package has been tested with a home-built board and with an The board support package has been tested with:
ACE360A board produced by: A home-built 68360 board
Atlas Computer Equipment An ACE360A and an HSB board produced by:
703 Colina Lane Atlas Computer Equipment
Santa Barbara, CA 93103 703 Colina Lane
Santa Barbara, CA 93103
A 68040/68360 board (SBC360) produced by:
Arnewsh Inc.
P.O. Box 270352
Fort Collins, CO 80527-0352

9
c/src/lib/libbsp/m68k/gen68360/clock/ckinit.c
View File

@@ -57,6 +57,15 @@ rtems_device_minor_number rtems_clock_minor;
rtems_isr rtems_isr
Clock_isr (rtems_vector_number vector) Clock_isr (rtems_vector_number vector)
{ {
/*
* Perform a dummy read of DPRAM.
* This works around a bug in Rev. B of the 68360
*/
m360.dpram0[0];
/*
* Announce the clock tick
*/
Clock_driver_ticks++; Clock_driver_ticks++;
rtems_clock_tick(); rtems_clock_tick();
} }

3
c/src/lib/libbsp/m68k/gen68360/include/bsp.h
View File

@@ -132,9 +132,6 @@ m68k_isr_entry set_vector(
* Values assigned by link editor * Values assigned by link editor
*/ */
extern void *_RomBase, *_RamBase, *_RamSize; extern void *_RomBase, *_RamBase, *_RamSize;
extern void *_MC68360HardwareType;
extern void *_MC68360HardwareTypeMotorolaGeneric;
extern void *_MC68360HardwareTypeAtlasHSB;
/* /*
* Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB) * Definitions for Atlas Computer Equipment Inc. High Speed Bridge (HSB)

10
c/src/lib/libbsp/m68k/gen68360/start/start360.s
View File

@@ -1,4 +1,4 @@
/* entry.s /*
* *
* This file contains the entry point for the application. * This file contains the entry point for the application.
* The name of this entry point is compiler dependent. * The name of this entry point is compiler dependent.
@@ -311,15 +311,19 @@ spurious_interrupt:
.align 2 .align 2
.long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address .long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address
.global start
/* /*
* Initial PC * Initial PC
*/ */
.global start
start: start:
/* /*
* Step 2: Stay in Supervisor Mode * Step 2: Stay in Supervisor Mode
* (i.e. just do nothing for this step)
*/ */
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
oriw #0x3000,sr | Switch to Master Stack Pointer
lea SYM(m360)+1024-64,a7 | Load stack pointer with space
| for the Interrupt Stack
#endif
/* /*
* Step 3: Write the VBR * Step 3: Write the VBR

10
c/src/lib/libbsp/m68k/gen68360/start360/start360.s
View File

@@ -1,4 +1,4 @@
/* entry.s /*
* *
* This file contains the entry point for the application. * This file contains the entry point for the application.
* The name of this entry point is compiler dependent. * The name of this entry point is compiler dependent.
@@ -311,15 +311,19 @@ spurious_interrupt:
.align 2 .align 2
.long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address .long ETHERNET_ADDRESS | Low-order 3 octets of ethernet address
.global start
/* /*
* Initial PC * Initial PC
*/ */
.global start
start: start:
/* /*
* Step 2: Stay in Supervisor Mode * Step 2: Stay in Supervisor Mode
* (i.e. just do nothing for this step)
*/ */
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
oriw #0x3000,sr | Switch to Master Stack Pointer
lea SYM(m360)+1024-64,a7 | Load stack pointer with space
| for the Interrupt Stack
#endif
/* /*
* Step 3: Write the VBR * Step 3: Write the VBR

468
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
View File

@@ -32,14 +32,167 @@ void M360ExecuteRISC(rtems_unsigned16 command)
/* /*
* Initialize MC68360 * Initialize MC68360
*/ */
void _Init68360 (void) void _Init68360 (void)
{ {
int i; int i;
unsigned long l;
m68k_isr_entry *vbr; m68k_isr_entry *vbr;
extern void _CopyDataClearBSSAndStart (void); extern void _CopyDataClearBSSAndStart (void);
#if (defined (m68040) || defined (m68lc040) || defined (m68ec040))
/*
*******************************************
* Motorola 68040 and companion-mode 68360 *
*******************************************
*/
/*
* Step 6: Is this a power-up reset?
* For now we just ignore this and do *all* the steps
* Someday we might want to:
* if (Hard, Loss of Clock, Power-up)
* Do all steps
* else if (Double bus fault, watchdog or soft reset)
* Skip to step 12
* else (must be a reset command)
* Skip to step 14
*/
/*
* Step 7: Deal with clock synthesizer
* HARDWARE:
* Change if you're not using an external 25 MHz oscillator.
*/
m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */
m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
no LPSTOP slowdown, PLL X1 */
m360.cdvcr = 0x8000; /* No more writes, no clock division */
/*
* Step 8: Initialize system protection
* Disable watchdog FIXME: Should use watchdog!!!!
* Watchdog causes system reset
* Slowest watchdog timeout
* Disable double bus fault monitor
* Enable bus monitor external
* 1024 clocks for external timeout
*/
m360.sypcr = 0x74;
/*
* Step 9: Clear parameter RAM and reset communication processor module
*/
for (i = 0 ; i < 192 ; i += sizeof (long)) {
*((long *)((char *)&m360 + 0xC00 + i)) = 0;
*((long *)((char *)&m360 + 0xD00 + i)) = 0;
*((long *)((char *)&m360 + 0xE00 + i)) = 0;
*((long *)((char *)&m360 + 0xF00 + i)) = 0;
}
M360ExecuteRISC (M360_CR_RST);
/*
* Step 10: Write PEPAR
* SINTOUT standard M68000 family interrupt level encoding
* CF1MODE=10 (BCLRO* output)
* No RAS1* double drive
* A31 - A28
* AMUX output
* CAS2* - CAS3*
* CAS0* - CAS1*
* CS7*
* AVEC*
*/
m360.pepar = 0x3440;
/*
* Step 11: Remap Chip Select 0 (CS0*), set up GMR
*/
/*
* 512 addresses per DRAM page (256K DRAM chips)
* 70 nsec DRAM
* 180 nsec ROM (3 wait states)
*/
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_TSS40;
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
M360_MEMC_BR_V;
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
M360_MEMC_OR_32BIT;
/*
* Step 12: Initialize the system RAM
*/
/*
* Set up option/base registers
* 1M DRAM
* 70 nsec DRAM
* Enable burst mode
* No parity checking
* Wait for chips to power up
* Perform 8 read cycles
*/
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_1MB |
M360_MEMC_OR_DRAM;
m360.memc[1].br = (unsigned long)&_RamBase |
M360_MEMC_BR_BACK40 |
M360_MEMC_BR_V;
for (i = 0; i < 50000; i++)
continue;
for (i = 0; i < 8; ++i)
*((volatile unsigned long *)(unsigned long)&_RamBase);
/*
* Step 13: Copy the exception vector table to system RAM
*/
m68k_get_vbr (vbr);
for (i = 0; i < 256; ++i)
M68Kvec[i] = vbr[i];
m68k_set_vbr (M68Kvec);
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
* Disable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
* SCC1 requests at SCCa position
* SCC2 requests at SCCb position
* SCC3 requests at SCCc position
* SCC4 requests at SCCd position
* Interrupt request level 4
* Maintain original priority order
* Vector base 128
* SCCs priority grouped at top of table
*/
m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);
/*
* Step 15: Set module configuration register
* Bus request MC68040 Arbitration ID 3
* Bus asynchronous timing mode (work around bug in Rev. B)
* Arbitration asynchronous timing mode
* Disable timers during FREEZE
* Disable bus monitor during FREEZE
* BCLRO* arbitration level 3
* No show cycles
* User/supervisor access
* Bus clear in arbitration ID level 3
* SIM60 interrupt sources higher priority than CPM
*/
m360.mcr = 0x6000EC3F;
#elif (defined (M68360_ATLAS_HSB))
/*
******************************************
* Standalone Motorola 68360 -- ATLAS HSB *
******************************************
*/
/* /*
* Step 6: Is this a power-up reset? * Step 6: Is this a power-up reset?
* For now we just ignore this and do *all* the steps * For now we just ignore this and do *all* the steps
@@ -104,124 +257,43 @@ void _Init68360 (void)
/* /*
* Step 11: Remap Chip Select 0 (CS0*), set up GMR * Step 11: Remap Chip Select 0 (CS0*), set up GMR
*/ */
if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) { m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(1) | M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
M360_GMR_DPS_32BIT | M360_GMR_DWQ | M360_GMR_DPS_32BIT | M360_GMR_DWQ |
M360_GMR_GAMX; M360_GMR_GAMX;
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP | m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
M360_MEMC_BR_V; M360_MEMC_BR_V;
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB | m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
M360_MEMC_OR_8BIT; M360_MEMC_OR_8BIT;
}
else {
/*
* 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips)
* 60 nsec DRAM
* 180 nsec ROM (3 wait states)
*/
switch ((unsigned long)&_RamSize) {
default:
case 4*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(3) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
case 16*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(5) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
case 64*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(7) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
}
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
M360_MEMC_BR_V;
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
M360_MEMC_OR_8BIT;
}
/* /*
* Step 12: Initialize the system RAM * Step 12: Initialize the system RAM
*/ */
if (&_MC68360HardwareType == &_MC68360HardwareTypeAtlasHSB) { /* first bank 1MByte DRAM */
/* first bank 1MByte DRAM */ m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V; m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
/* second bank 1MByte DRAM */ /* second bank 1MByte DRAM */
m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB | m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM; M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) | m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
M360_MEMC_BR_V; M360_MEMC_BR_V;
/* flash rom socket U6 on CS5 */ /* flash rom socket U6 on CS5 */
m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP | m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
M360_MEMC_BR_V; M360_MEMC_BR_V;
m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB | m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
M360_MEMC_OR_8BIT; M360_MEMC_OR_8BIT;
/* CSRs on CS7 */ /* CSRs on CS7 */
m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB | m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
M360_MEMC_OR_8BIT; M360_MEMC_OR_8BIT;
m360.memc[7].br = ATLASHSB_ESR | 0x01; m360.memc[7].br = ATLASHSB_ESR | 0x01;
for (i = 0; i < 50000; i++) for (i = 0; i < 50000; i++)
continue; continue;
for (i = 0; i < 8; ++i) for (i = 0; i < 8; ++i)
*((volatile unsigned long *)(unsigned long)&_RamBase); *((volatile unsigned long *)(unsigned long)&_RamBase);
}
else {
/*
* Set up option/base registers
* 4M/16M/64M DRAM
* 60 nsec DRAM
* Wait for chips to power up
* Perform 8 read cycles
* Set all parity bits to correct state
* Enable parity checking
*/
switch ((unsigned long)&_RamSize) {
default:
case 4*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_4MB |
M360_MEMC_OR_DRAM;
break;
case 16*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_16MB |
M360_MEMC_OR_DRAM;
break;
case 64*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_64MB |
M360_MEMC_OR_DRAM;
break;
}
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
for (i = 0; i < 50000; i++)
continue;
for (i = 0; i < 8; ++i)
*((volatile unsigned long *)(unsigned long)&_RamBase);
for (l = 0 ; l < (unsigned long)&_RamSize ; l += sizeof (unsigned long)) {
volatile unsigned long *lp;
lp = (unsigned long *)((unsigned char *)&_RamBase + i);
*lp = *lp;
}
m360.memc[1].br = (unsigned long)&_RamBase |
M360_MEMC_BR_PAREN | M360_MEMC_BR_V;
}
/* /*
* Step 13: Copy the exception vector table to system RAM * Step 13: Copy the exception vector table to system RAM
@@ -263,6 +335,198 @@ void _Init68360 (void)
*/ */
m360.mcr = 0x4C7F; m360.mcr = 0x4C7F;
#else
/*
***************************************************
* Generic Standalone Motorola 68360 *
* As described in MC68360 User's Manual *
* Atlas ACE360 *
***************************************************
*/
/*
* Step 6: Is this a power-up reset?
* For now we just ignore this and do *all* the steps
* Someday we might want to:
* if (Hard, Loss of Clock, Power-up)
* Do all steps
* else if (Double bus fault, watchdog or soft reset)
* Skip to step 12
* else (must be a CPU32+ reset command)
* Skip to step 14
*/
/*
* Step 7: Deal with clock synthesizer
* HARDWARE:
* Change if you're not using an external 25 MHz oscillator.
*/
m360.clkocr = 0x8F; /* No more writes, no clock outputs */
m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
no LPSTOP slowdown, PLL X1 */
m360.cdvcr = 0x8000; /* No more writes, no clock division */
/*
* Step 8: Initialize system protection
* Disable watchdog FIXME: Should use watchdog!!!!
* Watchdog causes system reset
* Slowest watchdog timeout
* Enable double bus fault monitor
* Enable bus monitor external
* 128 clocks for external timeout
*/
m360.sypcr = 0x7F;
/*
* Step 9: Clear parameter RAM and reset communication processor module
*/
for (i = 0 ; i < 192 ; i += sizeof (long)) {
*((long *)((char *)&m360 + 0xC00 + i)) = 0;
*((long *)((char *)&m360 + 0xD00 + i)) = 0;
*((long *)((char *)&m360 + 0xE00 + i)) = 0;
*((long *)((char *)&m360 + 0xF00 + i)) = 0;
}
M360ExecuteRISC (M360_CR_RST);
/*
* Step 10: Write PEPAR
* SINTOUT not used (CPU32+ mode)
* CF1MODE=00 (CONFIG1 input)
* RAS1* double drive
* WE0* - WE3*
* OE* output
* CAS2* - CAS3*
* CAS0* - CAS1*
* CS7*
* AVEC*
* HARDWARE:
* Change if you are using a different memory configuration
* (static RAM, external address multiplexing, etc).
*/
m360.pepar = 0x0180;
/*
* Step 11: Remap Chip Select 0 (CS0*), set up GMR
*/
/*
* 1024/2048/4096 addresses per DRAM page (1M/4M/16M DRAM chips)
* 60 nsec DRAM
* 180 nsec ROM (3 wait states)
*/
switch ((unsigned long)&_RamSize) {
default:
case 4*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(3) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
case 16*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(5) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
case 64*1024*1024:
m360.gmr = M360_GMR_RCNT(24) | M360_GMR_RFEN |
M360_GMR_RCYC(0) | M360_GMR_PGS(7) |
M360_GMR_DPS_32BIT | M360_GMR_NCS |
M360_GMR_GAMX;
break;
}
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
M360_MEMC_BR_V;
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
M360_MEMC_OR_8BIT;
/*
* Step 12: Initialize the system RAM
*/
/*
* Set up option/base registers
* 4M/16M/64M DRAM
* 60 nsec DRAM
* Wait for chips to power up
* Perform 8 read cycles
* Set all parity bits to correct state
* Enable parity checking
*/
switch ((unsigned long)&_RamSize) {
default:
case 4*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_4MB |
M360_MEMC_OR_DRAM;
break;
case 16*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_16MB |
M360_MEMC_OR_DRAM;
break;
case 64*1024*1024:
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
M360_MEMC_OR_64MB |
M360_MEMC_OR_DRAM;
break;
}
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
for (i = 0; i < 50000; i++)
continue;
for (i = 0; i < 8; ++i)
*((volatile unsigned long *)(unsigned long)&_RamBase);
for (i = 0 ; i < (unsigned long)&_RamSize ; i += sizeof (unsigned long)) {
volatile unsigned long *lp;
lp = (unsigned long *)((unsigned char *)&_RamBase + i);
*lp = *lp;
}
m360.memc[1].br = (unsigned long)&_RamBase |
M360_MEMC_BR_PAREN | M360_MEMC_BR_V;
/*
* Step 13: Copy the exception vector table to system RAM
*/
m68k_get_vbr (vbr);
for (i = 0; i < 256; ++i)
M68Kvec[i] = vbr[i];
m68k_set_vbr (M68Kvec);
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)
* Disable SDMA during FREEZE
* Give SDMA priority over all interrupt handlers
* Set DMA arbiration level to 4
* CICR (CPM interrupt configuration register):
* SCC1 requests at SCCa position
* SCC2 requests at SCCb position
* SCC3 requests at SCCc position
* SCC4 requests at SCCd position
* Interrupt request level 4
* Maintain original priority order
* Vector base 128
* SCCs priority grouped at top of table
*/
m360.sdcr = M360_SDMA_FREEZE | M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
(4 << 13) | (0x1F << 8) | (128);
/*
* Step 15: Set module configuration register
* Disable timers during FREEZE
* Enable bus monitor during FREEZE
* BCLRO* arbitration level 3
* No show cycles
* User/supervisor access
* Bus clear interrupt service level 7
* SIM60 interrupt sources higher priority than CPM
*/
m360.mcr = 0x4C7F;
#endif
/* /*
* Copy data, clear BSS, switch stacks and call main() * Copy data, clear BSS, switch stacks and call main()
*/ */

30
c/src/lib/libbsp/m68k/gen68360/startup/linkcmds
View File

@@ -1,7 +1,7 @@
/* /*
* This file contains GNU linker directives for a generic MC68360 board. * This file contains GNU linker directives for a generic MC68360 board.
* Variations in hardware type and dynamic memory size can be made * Variations in memory size and allocation can be made by
* by overriding some values with linker command-line arguments. * overriding some values with linker command-line arguments.
* *
* Saskatchewan Accelerator Laboratory * Saskatchewan Accelerator Laboratory
* University of Saskatchewan * University of Saskatchewan
@@ -21,13 +21,6 @@ RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000; HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000;
StackSize = DEFINED(StackSize) ? StackSize : 0x1000; StackSize = DEFINED(StackSize) ? StackSize : 0x1000;
/*
* Declare hardware type
*/
MC68360HardwareTypeMotorolaGeneric = 0;
MC68360HardwareTypeAtlasHSB = 1;
MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
/* /*
* Declare on-board memory. * Declare on-board memory.
* It would be nice if the ram length could be given as * It would be nice if the ram length could be given as
@@ -36,8 +29,8 @@ MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
*/ */
MEMORY { MEMORY {
ram : ORIGIN = 0x00000000, LENGTH = 64M ram : ORIGIN = 0x00000000, LENGTH = 64M
rom : ORIGIN = 0xFF000000, LENGTH = 1M rom : ORIGIN = 0x0F000000, LENGTH = 1M
dpram : ORIGIN = 0xFE000000, LENGTH = 8k dpram : ORIGIN = 0x0E000000, LENGTH = 8k
} }
/* /*
@@ -45,15 +38,6 @@ MEMORY {
*/ */
ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12; ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12;
/*
* Declare hardware type.
* Acceptable values are:
* 0 - Generic system as described in the MC68360 User's Manual
* (MC68360UM/AD Rev. 1).
* 1 - ATLAS Computer Equipment Incorporated ACE360/HSB.
*/
MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
/* /*
* Load objects * Load objects
*/ */
@@ -63,12 +47,6 @@ SECTIONS {
*/ */
_RamSize = RamSize; _RamSize = RamSize;
__RamSize = RamSize; __RamSize = RamSize;
_MC68360HardwareType = MC68360HardwareType;
__MC68360HardwareType = MC68360HardwareType;
_MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;
__MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;
_MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;
__MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;
/* /*
* Boot PROM * Boot PROM

34
c/src/lib/libbsp/m68k/gen68360/startup/linkcmds.bootp
View File

@@ -4,16 +4,14 @@
* by overriding some values with linker command-line arguments. * by overriding some values with linker command-line arguments.
* *
* These linker directives are for producing a PROM version. * These linker directives are for producing a PROM version.
* To create the PROM image from the linker output you must use objcopy * The data segment is placed at the end of the text segment in the PROM.
* (--adjust-section-vma) to place the data segment at the end of the text * The start-up code takes care of copying this region to RAM.
* segment in the PROM. The start-up code takes care of copying this region
* to RAM.
* *
* Saskatchewan Accelerator Laboratory * Saskatchewan Accelerator Laboratory
* University of Saskatchewan * University of Saskatchewan
* Saskatoon, Saskatchewan, CANADA * Saskatoon, Saskatchewan, CANADA
* eric@skatter.usask.ca * eric@skatter.usask.ca
* *
* $Id$ * $Id$
*/ */
@@ -27,13 +25,6 @@ RamSize = DEFINED(RamSize) ? RamSize : 4M;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000; HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000;
StackSize = DEFINED(StackSize) ? StackSize : 0x1000; StackSize = DEFINED(StackSize) ? StackSize : 0x1000;
/*
* Declare hardware type
*/
MC68360HardwareTypeMotorolaGeneric = 0;
MC68360HardwareTypeAtlasHSB = 1;
MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
/* /*
* Declare on-board memory. * Declare on-board memory.
* It would be nice if the ram length could be given as * It would be nice if the ram length could be given as
@@ -43,8 +34,8 @@ MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
MEMORY { MEMORY {
ram : ORIGIN = 0x00000000, LENGTH = 64M ram : ORIGIN = 0x00000000, LENGTH = 64M
myram : ORIGIN = 4M-512k, LENGTH = 512k myram : ORIGIN = 4M-512k, LENGTH = 512k
rom : ORIGIN = 0xFF000000, LENGTH = 1M rom : ORIGIN = 0x0F000000, LENGTH = 1M
dpram : ORIGIN = 0xFE000000, LENGTH = 8k dpram : ORIGIN = 0x0E000000, LENGTH = 8k
} }
/* /*
@@ -52,15 +43,6 @@ MEMORY {
*/ */
ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12; ETHERNET_ADDRESS = DEFINED(ETHERNET_ADDRESS) ? ETHERNET_ADDRESS : 0xDEAD12;
/*
* Declare hardware type.
* Acceptable values are:
* 0 - Generic system as described in the MC68360 User's Manual
* (MC68360UM/AD Rev. 1).
* 1 - ATLAS Computer Equipment Incorporated ACE360/HSB.
*/
MC68360HardwareType = DEFINED(MC68360HardwareType) ? MC68360HardwareType : 0;
/* /*
* Load objects * Load objects
*/ */
@@ -70,12 +52,6 @@ SECTIONS {
*/ */
_RamSize = RamSize; _RamSize = RamSize;
__RamSize = RamSize; __RamSize = RamSize;
_MC68360HardwareType = MC68360HardwareType;
__MC68360HardwareType = MC68360HardwareType;
_MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;
__MC68360HardwareTypeMotorolaGeneric = MC68360HardwareTypeMotorolaGeneric;
_MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;
__MC68360HardwareTypeAtlasHSB = MC68360HardwareTypeAtlasHSB;
/* /*
* Boot PROM * Boot PROM