forked from Imagelibrary/rtems
bsp/atsam: Fix MPU sections.
The nocache section has been hard coded which could lead to problems when a bigger region should be used. Fix that. The internal SRAM has not been set up correctly. A duplicate external SDRAM has been set up instead. Remove a lot of other hard coded sections too.
This commit is contained in:
Christian Mauderer
committed by
Sebastian Huber
Sebastian Huber
parent
bdbf1ffa6e
commit
f7f420e11a
@@ -92,18 +92,28 @@ void _SetupMemoryRegion(void)
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START_Addr:- 0x00000000UL
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END_Addr:- 0x003FFFFFUL
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****************************************************/
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dwRegionBaseAddr =
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ITCM_START_ADDRESS |
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MPU_REGION_VALID |
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MPU_DEFAULT_ITCM_REGION; // 1
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#ifdef __rtems__
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if (ITCM_END_ADDRESS + 1 != ITCM_START_ADDRESS) {
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#endif /* __rtems__ */
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dwRegionAttr =
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MPU_AP_PRIVILEGED_READ_WRITE |
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MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
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MPU_REGION_ENABLE;
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#ifdef __rtems__
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} else {
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dwRegionAttr = MPU_REGION_DISABLE;
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}
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#endif /* __rtems__ */
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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/****************************************************
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Internal flash memory region --- Normal read-only
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(update to Strongly ordered in write accesses)
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@@ -136,14 +146,23 @@ void _SetupMemoryRegion(void)
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MPU_REGION_VALID |
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MPU_DEFAULT_DTCM_REGION; //3
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#ifdef __rtems__
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if (DTCM_END_ADDRESS + 1 != DTCM_START_ADDRESS) {
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#endif /* __rtems__ */
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dwRegionAttr =
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MPU_AP_PRIVILEGED_READ_WRITE |
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INNER_NORMAL_NOCACHE_TYPE(NON_SHAREABLE) |
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MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
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MPU_REGION_ENABLE;
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#ifdef __rtems__
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} else {
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dwRegionAttr = MPU_REGION_DISABLE;
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}
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#endif /* __rtems__ */
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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/****************************************************
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SRAM Cacheable memory region --- Normal
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START_Addr:- 0x20400000UL
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@@ -183,6 +202,12 @@ void _SetupMemoryRegion(void)
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MPU_REGION_ENABLE;
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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#else /* __rtems__ */
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/* NOTE: The first SRAM region is increased so it covers the whole SRAM. If
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* the SRAM is something odd (like 384k on the SAME70Q21), the next higher
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* power of two will be used (in the example: 512k). That removes the need of
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* the second SRAM region. There is currently no memory after the SRAM so that
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* shouldn't be a problem. */
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#endif /* __rtems__ */
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#ifdef MPU_HAS_NOCACHE_REGION
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@@ -218,6 +243,20 @@ void _SetupMemoryRegion(void)
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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#ifdef __rtems__
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dwRegionBaseAddr =
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SYSTEM_START_ADDRESS |
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MPU_REGION_VALID |
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MPU_SYSTEM_REGION;
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dwRegionAttr = MPU_AP_FULL_ACCESS |
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MPU_REGION_EXECUTE_NEVER |
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SHAREABLE_DEVICE_TYPE |
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MPU_CalMPURegionSize(SYSTEM_END_ADDRESS - SYSTEM_START_ADDRESS)
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| MPU_REGION_ENABLE;
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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#endif /* __rtems__ */
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/****************************************************
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External EBI memory memory region --- Strongly Ordered
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@@ -267,11 +306,19 @@ void _SetupMemoryRegion(void)
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MPU_REGION_VALID |
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MPU_QSPIMEM_REGION; //8
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#ifdef __rtems__
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if (QSPI_END_ADDRESS + 1 != QSPI_START_ADDRESS) {
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#endif /* __rtems__ */
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dwRegionAttr =
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MPU_AP_FULL_ACCESS |
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INNER_NORMAL_WB_NWA_TYPE(SHAREABLE) |
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MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
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MPU_REGION_ENABLE;
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#ifdef __rtems__
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} else {
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dwRegionAttr = MPU_REGION_DISABLE;
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}
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#endif /* __rtems__ */
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MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
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@@ -301,7 +348,11 @@ void _SetupMemoryRegion(void)
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| SCB_SHCSR_USGFAULTENA_Msk);
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/* Enable the MPU region */
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#ifndef __rtems__
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MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
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#else /* __rtems__ */
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MPU_Enable(MPU_ENABLE);
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#endif /* __rtems__ */
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memory_sync();
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}
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@@ -54,6 +54,7 @@
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#if defined MPU_HAS_NOCACHE_REGION
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#define MPU_NOCACHE_SRAM_REGION (11)
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#endif
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#define MPU_SYSTEM_REGION (12)
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#define MPU_REGION_VALID (0x10)
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#define MPU_REGION_ENABLE (0x01)
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@@ -101,10 +102,17 @@
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*/
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/********* IFLASH memory macros *********************/
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#ifdef __rtems__
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#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin)
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#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1)
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#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin)
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#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1)
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#else /* !__rtems__ */
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#define ITCM_START_ADDRESS 0x00000000UL
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#define ITCM_END_ADDRESS 0x003FFFFFUL
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#define IFLASH_START_ADDRESS 0x00400000UL
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#define IFLASH_END_ADDRESS 0x005FFFFFUL
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#endif /* __rtems__ */
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#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
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@@ -114,24 +122,36 @@
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#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
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/**************** DTCM *******************************/
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#ifdef __rtems__
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#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin)
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#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1)
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#else /* !__rtems__ */
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#define DTCM_START_ADDRESS 0x20000000UL
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#define DTCM_END_ADDRESS 0x203FFFFFUL
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#endif /* __rtems__ */
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/******* SRAM memory macros ***************************/
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#ifdef __rtems__
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#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
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#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
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#else /* !__rtems__ */
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#define SRAM_START_ADDRESS 0x20400000UL
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#define SRAM_END_ADDRESS 0x2045FFFFUL
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#endif /* __rtems__ */
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#ifndef __rtems__
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#if defined MPU_HAS_NOCACHE_REGION
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#define NOCACHE_SRAM_REGION_SIZE 0x1000
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#endif
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#endif /* __rtems__ */
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/* Regions should be a 2^(N+1) where 4 < N < 31 */
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#ifdef __rtems__
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#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
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#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
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#else /* __rtems__ */
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#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
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#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
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#else /* !__rtems__ */
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#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
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#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
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#endif /* __rtems__ */
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@@ -140,7 +160,8 @@
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#ifdef __rtems__
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#define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
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#define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
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#else /* __rtems__ */
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#define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
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#else /* !__rtems__ */
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#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
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#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
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#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
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@@ -155,18 +176,32 @@
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/************** Peripherals memory region macros ********/
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#define PERIPHERALS_START_ADDRESS 0x40000000UL
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#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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#ifdef __rtems__
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#define SYSTEM_START_ADDRESS 0xE0000000UL
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#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL
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#endif /* __rtems__ */
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/******* Ext EBI memory macros ***************************/
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#define EXT_EBI_START_ADDRESS 0x60000000UL
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#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
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/******* Ext-SRAM memory macros ***************************/
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#ifdef __rtems__
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#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
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#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
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#else /* !__rtems__ */
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#define SDRAM_START_ADDRESS 0x70000000UL
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#define SDRAM_END_ADDRESS 0x7FFFFFFFUL
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#endif /* __rtems__ */
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/******* QSPI macros ***************************/
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#ifdef __rtems__
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#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin)
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#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1)
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#else /* !__rtems__ */
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#define QSPI_START_ADDRESS 0x80000000UL
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#define QSPI_END_ADDRESS 0x9FFFFFFFUL
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#endif /* __rtems__ */
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/************** USBHS_RAM region macros ******************/
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#define USBHSRAM_START_ADDRESS 0xA0100000UL
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@@ -8,6 +8,8 @@ MEMORY {
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QSPIFLASH : ORIGIN = 0x80000000, LENGTH = @ATSAM_MEMORY_QSPIFLASH_SIZE@
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}
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/* Must be used only for MPU definitions */
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atsam_memory_itcm_begin = ORIGIN (ITCM);
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atsam_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM);
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atsam_memory_itcm_size = LENGTH (ITCM);
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