forked from Imagelibrary/rtems
bsp/altera-cyclone-v: New BSP
Implemented so far: - nocache heap for uncached RAM - basic timer - level 1 cache handling for arm cache controller in arm-cache-l1.h - level 2 L2C-310 cache controller - MMU - DWMAC 1000 ethernet controller - basic errata handling - smp startup for second core
This commit is contained in:
Ralf Kirchner
committed by
Sebastian Huber
Sebastian Huber
parent
4953b72490
commit
f73cfe99d0
@@ -2,6 +2,8 @@
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AC_DEFUN([RTEMS_CHECK_BSPDIR],
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[
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case "$1" in
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altera-cyclone-v )
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AC_CONFIG_SUBDIRS([altera-cyclone-v]);;
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csb336 )
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AC_CONFIG_SUBDIRS([csb336]);;
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csb337 )
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197
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
Normal file
197
c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am
Normal file
@@ -0,0 +1,197 @@
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##
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#
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# @file
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#
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# @brief Makefile of LibBSP for the Altera Cyclone-V platform.
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#
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ACLOCAL_AMFLAGS = -I ../../../../aclocal
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include $(top_srcdir)/../../../../automake/compile.am
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include_bspdir = $(includedir)/bsp
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include_libcpudir = $(includedir)/libcpu
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dist_project_lib_DATA = bsp_specs
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###############################################################################
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# Header #
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###############################################################################
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include_HEADERS = include/bsp.h
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include_HEADERS += include/tm27.h
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nodist_include_HEADERS = ../../shared/include/coverhd.h \
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include/bspopts.h
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nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
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include_bsp_HEADERS =
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include_bsp_HEADERS += ../../shared/include/utility.h
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include_bsp_HEADERS += ../../shared/include/irq-generic.h
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include_bsp_HEADERS += ../../shared/include/irq-info.h
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include_bsp_HEADERS += ../../shared/include/stackalloc.h
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include_bsp_HEADERS += ../../shared/tod.h
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include_bsp_HEADERS += ../shared/include/start.h
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include_bsp_HEADERS += ../shared/include/arm-a9mpcore-clock.h
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include_bsp_HEADERS += ../shared/include/arm-a9mpcore-irq.h
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include_bsp_HEADERS += ../shared/include/arm-a9mpcore-regs.h
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include_bsp_HEADERS += ../shared/include/arm-a9mpcore-start.h
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include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
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include_bsp_HEADERS += ../shared/include/arm-errata.h
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include_bsp_HEADERS += ../shared/include/arm-gic.h
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include_bsp_HEADERS += ../shared/include/arm-gic-irq.h
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include_bsp_HEADERS += ../shared/include/arm-gic-regs.h
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include_bsp_HEADERS += ../shared/include/arm-gic-tm27.h
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include_bsp_HEADERS += ../shared/include/arm-release-id.h
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include_bsp_HEADERS += include/irq.h
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include_bsp_HEADERS += include/nocache-heap.h
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# Altera hwlib
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include_bsp_HEADERS += hwlib/include/alt_address_space.h
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include_bsp_HEADERS += hwlib/include/alt_clock_group.h
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include_bsp_HEADERS += hwlib/include/alt_clock_manager.h
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include_bsp_HEADERS += hwlib/include/alt_generalpurpose_io.h
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include_bsp_HEADERS += hwlib/include/alt_hwlibs_ver.h
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include_bsp_HEADERS += hwlib/include/alt_interrupt_common.h
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include_bsp_HEADERS += hwlib/include/alt_mpu_registers.h
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include_bsp_HEADERS += hwlib/include/alt_reset_manager.h
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include_bsp_HEADERS += hwlib/include/hwlib.h
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#The following Altera hwlib header files have been left out because so far
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#they are not required:
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#include_bsp_HEADERS += hwlib/include/alt_16550_uart.h
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#include_bsp_HEADERS += hwlib/include/alt_bridge_manager.h
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#include_bsp_HEADERS += hwlib/include/alt_dma_common.h
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#include_bsp_HEADERS += hwlib/include/alt_dma_program.h
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#include_bsp_HEADERS += hwlib/include/alt_dma.h
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#include_bsp_HEADERS += hwlib/include/alt_fpga_manager.h
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#include_bsp_HEADERS += hwlib/include/alt_globaltmr.h
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#include_bsp_HEADERS += hwlib/include/alt_system_manager.h
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#include_bsp_HEADERS += hwlib/include/alt_timers.h
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#include_bsp_HEADERS += hwlib/include/alt_watchdog.h
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#The following Altera hwlib headers would be problematic with RTEMS:
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#include_bsp_HEADERS += hwlib/include/alt_interrupt.h
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#All header files from hwlib/include/socal are regarded as BSP
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#internal and thus not installed
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include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
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###############################################################################
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# Data #
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###############################################################################
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noinst_LIBRARIES = libbspstart.a
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libbspstart_a_SOURCES = ../shared/start/start.S
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project_lib_DATA = start.$(OBJEXT)
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project_lib_DATA += startup/linkcmds
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project_lib_DATA += startup/linkcmds.altcycv
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project_lib_DATA += startup/linkcmds.altcycv_devkit
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project_lib_DATA += startup/linkcmds.altcycv_devkit_smp
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###############################################################################
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# LibBSP #
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###############################################################################
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noinst_LIBRARIES += libbsp.a
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libbsp_a_SOURCES =
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libbsp_a_CPPFLAGS =
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libbsp_a_LIBADD =
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# for the Altera hwlib
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libbsp_a_CPPFLAGS += -I ${srcdir}/hwlib/include
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libbsp_a_CPPFLAGS += -std=gnu99
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# hwlib from Altera
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libbsp_a_SOURCES += hwlib/src/hwmgr/alt_address_space.c
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libbsp_a_SOURCES += hwlib/src/hwmgr/alt_clock_manager.c
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libbsp_a_SOURCES += hwlib/src/hwmgr/alt_generalpurpose_io.c
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libbsp_a_SOURCES += hwlib/src/hwmgr/alt_reset_manager.c
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#The following Altera hwlib source files have been left out because so far
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#they are not required:
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_16550_uart.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_bridge_manager.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma_program.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_dma.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_fpga_manager.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_globaltmr.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_system_manager.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_timers.c
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_watchdog.c
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# The following Altera hwlib source files would be problematic with RTEMS:
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#libbsp_a_SOURCES += hwlib/src/hwmgr/alt_interrupt.c
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# Shared
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libbsp_a_SOURCES += ../../shared/bootcard.c
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libbsp_a_SOURCES += ../../shared/bspclean.c
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libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
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libbsp_a_SOURCES += ../../shared/bsplibc.c
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libbsp_a_SOURCES += ../../shared/bsppost.c
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libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
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libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
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libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
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libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
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libbsp_a_SOURCES += ../../shared/sbrk.c
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libbsp_a_SOURCES += ../../shared/timerstub.c
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libbsp_a_SOURCES += ../../shared/src/stackalloc.c
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libbsp_a_SOURCES += ../shared/abort/simple_abort.c
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libbsp_a_SOURCES += ../shared/startup/bsp-start-memcpy.S
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libbsp_a_SOURCES += ../shared/arm-cp15-set-exception-handler.c
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libbsp_a_SOURCES += ../shared/arm-cp15-set-ttb-entries.c
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# Startup
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libbsp_a_SOURCES += startup/bspreset.c
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libbsp_a_SOURCES += startup/bspstart.c
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libbsp_a_SOURCES += startup/nocache-heap.c
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# IRQ
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libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
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libbsp_a_SOURCES += ../../shared/src/irq-generic.c
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libbsp_a_SOURCES += ../../shared/src/irq-info.c
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libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
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libbsp_a_SOURCES += ../../shared/src/irq-server.c
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libbsp_a_SOURCES += ../../shared/src/irq-shell.c
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libbsp_a_SOURCES += ../shared/arm-gic-irq.c
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# Network
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libbsp_a_SOURCES += network/network.c
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# Console
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libbsp_a_SOURCES += ../../shared/console.c
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libbsp_a_SOURCES += ../../shared/console_control.c
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libbsp_a_SOURCES += ../../shared/console_read.c
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libbsp_a_SOURCES += ../../shared/console_select_simple.c
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libbsp_a_SOURCES += ../../shared/console_write.c
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libbsp_a_SOURCES += console/console-config.c
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# Clock
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libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
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libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
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# Cache
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libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
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libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
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libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
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libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
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# Start hooks
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libbsp_a_SOURCES += startup/bspstarthooks.c
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if HAS_SMP
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libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
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endif
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###############################################################################
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# Special Rules #
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###############################################################################
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DISTCLEANFILES = include/bspopts.h
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include $(srcdir)/preinstall.am
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include $(top_srcdir)/../../../../automake/local.am
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3
c/src/lib/libbsp/arm/altera-cyclone-v/README
Normal file
3
c/src/lib/libbsp/arm/altera-cyclone-v/README
Normal file
@@ -0,0 +1,3 @@
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Evaluation board for this BSP:
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- Cyclone V SoC FPGA Development Kit
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- DK-DEV-5CSXC6N/ES-0L
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13
c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs
Normal file
13
c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs
Normal file
@@ -0,0 +1,13 @@
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%rename endfile old_endfile
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%rename startfile old_startfile
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%rename link old_link
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*startfile:
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%{!qrtems: %(old_startfile)} \
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%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}}
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*link:
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%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}
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*endfile:
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%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s }
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56
c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac
Normal file
56
c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac
Normal file
@@ -0,0 +1,56 @@
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##
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#
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# @file
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#
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# @brief Configure script of LibBSP for the Altera Cyclone-V platform.
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#
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AC_PREREQ([2.69])
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AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
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AC_CONFIG_SRCDIR([bsp_specs])
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RTEMS_TOP(../../../../../..)
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RTEMS_CANONICAL_TARGET_CPU
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AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
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RTEMS_BSP_CONFIGURE
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RTEMS_PROG_CC_FOR_TARGET
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RTEMS_CANONICALIZE_TOOLS
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RTEMS_PROG_CCAS
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RTEMS_CHECK_NETWORKING
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AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
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RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[])
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RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start])
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RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U])
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RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U])
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RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz])
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RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[1])
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RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE],
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[This sets a mode where the time runs as fast as possible when a clock ISR
|
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occurs while the IDLE thread is executing. This can significantly reduce
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simulation times.])
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RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[0])
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RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device])
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RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_CONSOLE],[*],[0])
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RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_CONSOLE],[configuration for console (UART 0)])
|
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|
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RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_UART_1],[*],[0])
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RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1])
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RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U])
|
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RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs])
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RTEMS_CHECK_SMP
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AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
|
||||
|
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RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
|
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RTEMS_BSP_LINKCMDS
|
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|
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AC_CONFIG_FILES([Makefile])
|
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AC_OUTPUT
|
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195
c/src/lib/libbsp/arm/altera-cyclone-v/console/console-config.c
Normal file
195
c/src/lib/libbsp/arm/altera-cyclone-v/console/console-config.c
Normal file
@@ -0,0 +1,195 @@
|
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/*
|
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
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*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
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#include <libchip/serial.h>
|
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#include <libchip/ns16550.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/alt_clock_manager.h>
|
||||
#include "socal/alt_rstmgr.h"
|
||||
#include "socal/socal.h"
|
||||
#include "socal/alt_uart.h"
|
||||
#include "socal/hps.h"
|
||||
|
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bool altera_cyclone_v_uart_probe( int minor );
|
||||
|
||||
static uint8_t altera_cyclone_v_uart_get_register(uintptr_t addr, uint8_t i)
|
||||
{
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volatile uint32_t *reg = (volatile uint32_t *) addr;
|
||||
|
||||
return (uint8_t) reg [i];
|
||||
}
|
||||
|
||||
static void altera_cyclone_v_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
|
||||
{
|
||||
volatile uint32_t *reg = (volatile uint32_t *) addr;
|
||||
|
||||
reg [i] = val;
|
||||
}
|
||||
|
||||
console_tbl Console_Configuration_Ports[] = {
|
||||
#ifdef CYCLONE_V_CONFIG_CONSOLE
|
||||
{
|
||||
.sDeviceName = "/dev/ttyS0",
|
||||
.deviceType = SERIAL_NS16550,
|
||||
.pDeviceFns = &ns16550_fns,
|
||||
.deviceProbe = altera_cyclone_v_uart_probe,
|
||||
.pDeviceFlow = NULL,
|
||||
.ulMargin = 16,
|
||||
.ulHysteresis = 8,
|
||||
.pDeviceParams = (void *)CYCLONE_V_UART_BAUD,
|
||||
.ulCtrlPort1 = (uint32_t)ALT_UART0_ADDR,
|
||||
.ulCtrlPort2 = 0,
|
||||
.ulDataPort = (uint32_t)ALT_UART0_ADDR,
|
||||
.getRegister = altera_cyclone_v_uart_get_register,
|
||||
.setRegister = altera_cyclone_v_uart_set_register,
|
||||
.getData = NULL,
|
||||
.setData = NULL,
|
||||
.ulClock = 0,
|
||||
.ulIntVector = ALT_INT_INTERRUPT_UART0
|
||||
},
|
||||
#endif
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||||
#ifdef CYCLONE_V_CONFIG_UART_1
|
||||
{
|
||||
.sDeviceName = "/dev/ttyS1",
|
||||
.deviceType = SERIAL_NS16550,
|
||||
.pDeviceFns = &ns16550_fns,
|
||||
.deviceProbe = altera_cyclone_v_uart_probe,
|
||||
.pDeviceFlow = NULL,
|
||||
.ulMargin = 16,
|
||||
.ulHysteresis = 8,
|
||||
.pDeviceParams = (void *)CYCLONE_V_UART_BAUD,
|
||||
.ulCtrlPort1 = (uint32_t)ALT_UART1_ADDR,
|
||||
.ulCtrlPort2 = 0,
|
||||
.ulDataPort = (uint32_t)ALT_UART1_ADDR,
|
||||
.getRegister = altera_cyclone_v_uart_get_register,
|
||||
.setRegister = altera_cyclone_v_uart_set_register,
|
||||
.getData = NULL,
|
||||
.setData = NULL,
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||||
.ulClock = 0,
|
||||
.ulIntVector = ALT_INT_INTERRUPT_UART1
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
unsigned long Console_Configuration_Count =
|
||||
RTEMS_ARRAY_SIZE(Console_Configuration_Ports);
|
||||
|
||||
bool altera_cyclone_v_uart_probe(int minor)
|
||||
{
|
||||
bool ret = true;
|
||||
uint32_t uart_set_mask;
|
||||
uint32_t ucr;
|
||||
ALT_STATUS_CODE sc;
|
||||
void* location;
|
||||
|
||||
/* The ALT_CLK_L4_SP is required for all SoCFPGA UARTs.
|
||||
* Check that it's enabled. */
|
||||
assert( alt_clk_is_enabled(ALT_CLK_L4_SP) == ALT_E_TRUE );
|
||||
if ( alt_clk_is_enabled(ALT_CLK_L4_SP) != ALT_E_TRUE ) {
|
||||
ret = false;
|
||||
}
|
||||
|
||||
if ( ret ) {
|
||||
switch(minor)
|
||||
{
|
||||
case(0):
|
||||
/* UART 0 */
|
||||
uart_set_mask = ALT_RSTMGR_PERMODRST_UART0_SET_MSK;
|
||||
location = ALT_UART0_ADDR;
|
||||
break;
|
||||
case(1):
|
||||
/* UART 1 */
|
||||
uart_set_mask = ALT_RSTMGR_PERMODRST_UART1_SET_MSK;
|
||||
location = ALT_UART1_ADDR;
|
||||
break;
|
||||
default:
|
||||
/* Unknown case */
|
||||
assert( minor == 0 || minor == 1 );
|
||||
ret = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ( ret ) {
|
||||
sc = alt_clk_freq_get(ALT_CLK_L4_SP, &Console_Configuration_Ports[minor].ulClock);
|
||||
assert( sc == ALT_E_SUCCESS );
|
||||
if ( sc != ALT_E_SUCCESS ) {
|
||||
ret = false;
|
||||
}
|
||||
}
|
||||
|
||||
if ( ret ) {
|
||||
// Bring UART out of reset.
|
||||
alt_clrbits_word(ALT_RSTMGR_PERMODRST_ADDR, uart_set_mask);
|
||||
|
||||
// Verify the UCR (UART Component Version)
|
||||
ucr = alt_read_word( ALT_UART_UCV_ADDR( location ) );
|
||||
|
||||
assert( ucr == ALT_UART_UCV_UART_COMPONENT_VER_RESET );
|
||||
if ( ucr != ALT_UART_UCV_UART_COMPONENT_VER_RESET ) {
|
||||
ret = false;
|
||||
}
|
||||
}
|
||||
|
||||
if ( ret ) {
|
||||
// Write SRR::UR (Shadow Reset Register :: UART Reset)
|
||||
alt_write_word( ALT_UART_SRR_ADDR( location ), ALT_UART_SRR_UR_SET_MSK );
|
||||
|
||||
// Read the MSR to work around case:119085.
|
||||
(void)alt_read_word( ALT_UART_MSR_ADDR( location ) );
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void output_char(char c)
|
||||
{
|
||||
int minor = (int) Console_Port_Minor;
|
||||
const console_tbl *ct = Console_Port_Tbl != NULL ?
|
||||
Console_Port_Tbl[minor] : &Console_Configuration_Ports[minor];
|
||||
const console_fns *cf = ct->pDeviceFns;
|
||||
|
||||
if (c == '\n') {
|
||||
(*cf->deviceWritePolled)(minor, '\r');
|
||||
}
|
||||
|
||||
(*cf->deviceWritePolled)(minor, c);
|
||||
}
|
||||
|
||||
static void output_char_init(char c)
|
||||
{
|
||||
if (Console_Port_Tbl == NULL) {
|
||||
int minor;
|
||||
const console_fns *cf;
|
||||
|
||||
bsp_console_select();
|
||||
|
||||
minor = (int) Console_Port_Minor;
|
||||
cf = Console_Configuration_Ports[minor].pDeviceFns;
|
||||
|
||||
(*cf->deviceInitialize)(minor);
|
||||
}
|
||||
|
||||
BSP_output_char = output_char;
|
||||
output_char(c);
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = output_char_init;
|
||||
|
||||
BSP_polling_getchar_function_type BSP_poll_char = NULL;
|
||||
65
c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h
Normal file
65
c/src/lib/libbsp/arm/altera-cyclone-v/include/bsp.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_ALTERY_CYCLONE_V_BSP_H
|
||||
#define LIBBSP_ARM_ALTERY_CYCLONE_V_BSP_H
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#define BSP_FEATURE_IRQ_EXTENSION
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/clockdrv.h>
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
|
||||
|
||||
#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
|
||||
|
||||
#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
|
||||
|
||||
#define BSP_ARM_L2CC_BASE 0xFFFEF000U
|
||||
|
||||
/* Forward declaration */
|
||||
struct rtems_bsdnet_ifconfig;
|
||||
|
||||
/** @brief Network interface attach detach
|
||||
*
|
||||
* Attaches a network interface tp the network stack.
|
||||
* NOTE: Detaching is not supported!
|
||||
*/
|
||||
int altera_cyclone_v_network_if_attach_detach(
|
||||
struct rtems_bsdnet_ifconfig *config,
|
||||
int attaching );
|
||||
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH altera_cyclone_v_network_if_attach_detach
|
||||
#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_ARM_ALTERY_CYCLONE_V_BSP_H */
|
||||
41
c/src/lib/libbsp/arm/altera-cyclone-v/include/irq.h
Normal file
41
c/src/lib/libbsp/arm/altera-cyclone-v/include/irq.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
|
||||
#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#include <bsp/arm-a9mpcore-irq.h>
|
||||
#include <bsp/arm-gic-irq.h>
|
||||
#include <bsp/alt_interrupt_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* Use interrupt IDs as defined in alt_interrupt_common.h */
|
||||
#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0
|
||||
#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */
|
||||
55
c/src/lib/libbsp/arm/altera-cyclone-v/include/nocache-heap.h
Normal file
55
c/src/lib/libbsp/arm/altera-cyclone-v/include/nocache-heap.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief Heap handling for uncached RAM
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef NOCACHE_HEAP_H_
|
||||
#define NOCACHE_HEAP_H_
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief Initialize nocache heap.
|
||||
*
|
||||
* Initializes a heap for uncached RAM
|
||||
*/
|
||||
void altera_cyclone_v_nocache_init_heap( void );
|
||||
|
||||
/** @brief Nocache alloc.
|
||||
*
|
||||
* Allocate memory from uncached heap.
|
||||
* @param size Number of bytes to be allocated.
|
||||
* @returns Pointer to the allocated memory.
|
||||
*/
|
||||
void *altera_cyclone_v_nocache_malloc( const size_t size );
|
||||
|
||||
/** @brief Nocache free.
|
||||
*
|
||||
* Release memory from uncached heap.
|
||||
* @param ptr Address of the memory to be released.
|
||||
*/
|
||||
void altera_cyclone_v_nocache_free( void *ptr );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* NOCACHE_HEAP_H_ */
|
||||
24
c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h
Normal file
24
c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h
Normal file
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <bsp/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -0,0 +1,8 @@
|
||||
include $(RTEMS_ROOT)/make/custom/default.cfg
|
||||
|
||||
RTEMS_CPU = arm
|
||||
|
||||
CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
|
||||
|
||||
#CFLAGS_OPTIMIZE_V ?= -O0 -g
|
||||
CFLAGS_OPTIMIZE_V ?= -O2 -g
|
||||
@@ -0,0 +1 @@
|
||||
include $(RTEMS_ROOT)/make/custom/altcycv.inc
|
||||
@@ -0,0 +1 @@
|
||||
include $(RTEMS_ROOT)/make/custom/altcycv.inc
|
||||
1237
c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c
Normal file
1237
c/src/lib/libbsp/arm/altera-cyclone-v/network/network.c
Normal file
File diff suppressed because it is too large
Load Diff
200
c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am
Normal file
200
c/src/lib/libbsp/arm/altera-cyclone-v/preinstall.am
Normal file
@@ -0,0 +1,200 @@
|
||||
## Automatically generated by ampolish3 - Do not edit
|
||||
|
||||
if AMPOLISH3
|
||||
$(srcdir)/preinstall.am: Makefile.am
|
||||
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
|
||||
endif
|
||||
|
||||
PREINSTALL_DIRS =
|
||||
DISTCLEANFILES += $(PREINSTALL_DIRS)
|
||||
|
||||
all-local: $(TMPINSTALL_FILES)
|
||||
|
||||
TMPINSTALL_FILES =
|
||||
CLEANFILES = $(TMPINSTALL_FILES)
|
||||
|
||||
all-am: $(PREINSTALL_FILES)
|
||||
|
||||
PREINSTALL_FILES =
|
||||
CLEANFILES += $(PREINSTALL_FILES)
|
||||
|
||||
$(PROJECT_LIB)/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_LIB)
|
||||
@: > $(PROJECT_LIB)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)
|
||||
@: > $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
|
||||
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
|
||||
$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
|
||||
@$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
|
||||
@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
|
||||
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
|
||||
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
|
||||
|
||||
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-clock.h: ../shared/include/arm-a9mpcore-clock.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-clock.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-clock.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h: ../shared/include/arm-a9mpcore-irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-irq.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h: ../shared/include/arm-a9mpcore-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h: ../shared/include/arm-a9mpcore-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-cp15-start.h: ../shared/include/arm-cp15-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-errata.h: ../shared/include/arm-errata.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-errata.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-errata.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-gic.h: ../shared/include/arm-gic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-gic-irq.h: ../shared/include/arm-gic-irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-irq.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-irq.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-gic-regs.h: ../shared/include/arm-gic-regs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-regs.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-regs.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h: ../shared/include/arm-gic-tm27.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-gic-tm27.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/arm-release-id.h: ../shared/include/arm-release-id.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-release-id.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-release-id.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/nocache-heap.h: include/nocache-heap.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/nocache-heap.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/nocache-heap.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_address_space.h: hwlib/include/alt_address_space.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_address_space.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_address_space.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_clock_group.h: hwlib/include/alt_clock_group.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_group.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_group.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_clock_manager.h: hwlib/include/alt_clock_manager.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_clock_manager.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h: hwlib/include/alt_generalpurpose_io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_generalpurpose_io.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h: hwlib/include/alt_hwlibs_ver.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_hwlibs_ver.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h: hwlib/include/alt_interrupt_common.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_interrupt_common.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h: hwlib/include/alt_mpu_registers.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_mpu_registers.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/alt_reset_manager.h: hwlib/include/alt_reset_manager.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/alt_reset_manager.h
|
||||
|
||||
$(PROJECT_INCLUDE)/bsp/hwlib.h: hwlib/include/hwlib.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwlib.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwlib.h
|
||||
|
||||
$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
|
||||
|
||||
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
|
||||
|
||||
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.altcycv: startup/linkcmds.altcycv $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.altcycv
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.altcycv
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.altcycv_devkit: startup/linkcmds.altcycv_devkit $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.altcycv_devkit
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.altcycv_devkit
|
||||
|
||||
$(PROJECT_LIB)/linkcmds.altcycv_devkit_smp: startup/linkcmds.altcycv_devkit_smp $(PROJECT_LIB)/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp
|
||||
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds.altcycv_devkit_smp
|
||||
|
||||
37
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspreset.c
Normal file
37
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspreset.c
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/alt_reset_manager.h>
|
||||
#include "socal/alt_rstmgr.h"
|
||||
#include "socal/hps.h"
|
||||
|
||||
void bsp_reset(void)
|
||||
{
|
||||
uint32_t self_cpu = rtems_smp_get_current_processor();
|
||||
volatile uint32_t *mpumodrst = ALT_RSTMGR_MPUMODRST_ADDR;
|
||||
|
||||
if( self_cpu == 0 ) {
|
||||
/* Reset CPU1 */
|
||||
(*mpumodrst) |= ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK;
|
||||
|
||||
/* Simply call the reset method from alteras HWLIB */
|
||||
(void) alt_reset_cold_reset();
|
||||
} else {
|
||||
/* Keep CPU1 waiting until it gets reset by CPU0 */
|
||||
while ( true ) {
|
||||
__asm__ volatile ("wfi");
|
||||
}
|
||||
}
|
||||
}
|
||||
69
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstart.c
Normal file
69
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstart.c
Normal file
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdint.h>
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/nocache-heap.h>
|
||||
#include <rtems/config.h>
|
||||
#include "socal/alt_rstmgr.h"
|
||||
#include "socal/alt_sysmgr.h"
|
||||
#include "socal/hps.h"
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) )
|
||||
#endif
|
||||
|
||||
#define BSPSTART_MAX_CORES_PER_CONTROLLER 2
|
||||
|
||||
static void bsp_start_secondary_cores( void )
|
||||
{
|
||||
#ifdef RTEMS_SMP
|
||||
volatile uint32_t *mpumodrst = ALT_RSTMGR_MPUMODRST_ADDR;
|
||||
uint32_t *cpu1_start_addr = (
|
||||
ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST );
|
||||
const uint32_t CORES = MIN(
|
||||
(uintptr_t) bsp_processor_count,
|
||||
rtems_configuration_get_maximum_processors() );
|
||||
unsigned int index;
|
||||
|
||||
|
||||
/* Memory would get overwritten if a too small processor count
|
||||
* would be specified */
|
||||
assert(
|
||||
(uintptr_t) bsp_processor_count >= BSPSTART_MAX_CORES_PER_CONTROLLER );
|
||||
|
||||
if ( (uintptr_t) bsp_processor_count >= BSPSTART_MAX_CORES_PER_CONTROLLER ) {
|
||||
for ( index = 1; index < CORES; ++index ) {
|
||||
/* set the start address from where the core will execute */
|
||||
(*cpu1_start_addr) = ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(
|
||||
(uintptr_t) _start );
|
||||
|
||||
/* Make the core finish it's reset */
|
||||
(*mpumodrst) &= ~ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK;
|
||||
}
|
||||
}
|
||||
#endif /* #ifdef RTEMS_SMP */
|
||||
}
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
altera_cyclone_v_nocache_init_heap();
|
||||
bsp_start_secondary_cores();
|
||||
}
|
||||
204
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
Normal file
204
c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c
Normal file
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <info@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/arm-cp15-start.h>
|
||||
#include <bsp/arm-a9mpcore-start.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <alt_address_space.h>
|
||||
#include "socal/socal.h"
|
||||
#include "socal/alt_sdr.h"
|
||||
#include "socal/hps.h"
|
||||
#include "../include/arm-cache-l1.h"
|
||||
|
||||
/*#define DEBUG_ECC_ERROR*/ /* TODO: Delete DEBUG_ECC_ERROR after the implementation phase */
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
#define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE
|
||||
#else
|
||||
#define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED
|
||||
#endif
|
||||
|
||||
/* 1 MB reset default value for address filtering start */
|
||||
#define BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
|
||||
|
||||
#ifndef BSPSTARTHOOKS_MIN
|
||||
#define BSPSTARTHOOKS_MIN( a, b ) ( ( a ) < ( b ) ? ( a ) : ( b ) )
|
||||
#endif
|
||||
|
||||
LINKER_SYMBOL( bsp_section_nocache_size );
|
||||
LINKER_SYMBOL( bsp_section_nocache_end );
|
||||
LINKER_SYMBOL( bsp_section_nocache_begin );
|
||||
|
||||
BSP_START_DATA_SECTION static const arm_cp15_start_section_config
|
||||
altcycv_mmu_config_table[] = {
|
||||
ARMV7_CP15_START_DEFAULT_SECTIONS,
|
||||
{
|
||||
.begin = (uint32_t) bsp_section_nocache_begin,
|
||||
.end = (uint32_t) bsp_section_nocache_end,
|
||||
|
||||
.flags = ARMV7_MMU_DATA_READ_WRITE | ARM_MMU_SECT_TEX_0
|
||||
}, { /* Periphery area */
|
||||
.begin = 0xFC000000U,
|
||||
.end = 0x00000000U,
|
||||
.flags = ARMV7_MMU_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
BSP_START_TEXT_SECTION static void setup_mmu_and_cache( const uint32_t CPU_ID )
|
||||
{
|
||||
uint32_t ctrl = arm_cp15_get_control();
|
||||
const uint32_t CORES = BSPSTARTHOOKS_MIN(
|
||||
(uintptr_t) bsp_processor_count,
|
||||
rtems_configuration_get_maximum_processors() );
|
||||
|
||||
/* We expect the L1 caches and program flow prediction to be off */
|
||||
assert( ( ctrl & ARM_CP15_CTRL_I ) == 0 );
|
||||
assert( ( ctrl & ARM_CP15_CTRL_C ) == 0 );
|
||||
assert( ( ctrl & ARM_CP15_CTRL_Z ) == 0 );
|
||||
|
||||
ctrl = arm_cp15_start_setup_mmu_and_cache(
|
||||
ARM_CP15_CTRL_A | ARM_CP15_CTRL_M,
|
||||
ARM_CP15_CTRL_AFE
|
||||
);
|
||||
|
||||
if( CPU_ID == 0 ) {
|
||||
arm_cp15_start_setup_translation_table(
|
||||
(uint32_t *) bsp_translation_table_base,
|
||||
ARM_MMU_DEFAULT_CLIENT_DOMAIN,
|
||||
&altcycv_mmu_config_table[0],
|
||||
RTEMS_ARRAY_SIZE( altcycv_mmu_config_table )
|
||||
);
|
||||
} else {
|
||||
/* FIXME: Sharing the translation table between processors is brittle */
|
||||
arm_cp15_set_translation_table_base((uint32_t *) bsp_translation_table_base);
|
||||
}
|
||||
|
||||
/* Enable MMU */
|
||||
ctrl |= ARM_CP15_CTRL_M;
|
||||
|
||||
arm_cp15_set_control( ctrl );
|
||||
|
||||
if( CPU_ID == (CORES - 1) ) {
|
||||
/* Enable all cache levels for the last core */
|
||||
rtems_cache_enable_instruction();
|
||||
rtems_cache_enable_data();
|
||||
} else {
|
||||
/* Enable only L1 cache */
|
||||
arm_cache_l1_enable_data();
|
||||
arm_cache_l1_enable_instruction();
|
||||
}
|
||||
|
||||
/* Enable flow control prediction aka. branch prediction */
|
||||
|
||||
/* TODO: With the current network stack 06-Feb2014 in_checksum()
|
||||
* becomes a severe performance bottle neck with branch prediction enabled
|
||||
ctrl |= ARM_CP15_CTRL_Z;
|
||||
arm_cp15_set_control(ctrl);*/
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_0( void )
|
||||
{
|
||||
uint32_t ctrl;
|
||||
volatile a9mpcore_scu *scu = (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
|
||||
uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
|
||||
const uint32_t CORES = BSPSTARTHOOKS_MIN(
|
||||
(uintptr_t) bsp_processor_count,
|
||||
rtems_configuration_get_maximum_processors() );
|
||||
|
||||
assert( cpu_id < CORES );
|
||||
|
||||
if( cpu_id < CORES ) {
|
||||
if( cpu_id == 0 ) {
|
||||
ctrl = arm_cp15_mmu_disable( 32 );
|
||||
|
||||
ctrl &= ~( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_Z );
|
||||
arm_cp15_set_control( ctrl );
|
||||
|
||||
/* Enable Snoop Control Unit (SCU) */
|
||||
arm_a9mpcore_start_scu_enable( scu );
|
||||
}
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
/* Enable cache coherency support for this processor */
|
||||
uint32_t actlr = arm_cp15_get_auxiliary_control();
|
||||
actlr |= ARM_CORTEX_A9_ACTL_SMP;
|
||||
arm_cp15_set_auxiliary_control(actlr);
|
||||
#endif
|
||||
|
||||
if (cpu_id == 0) {
|
||||
arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF);
|
||||
}
|
||||
|
||||
setup_mmu_and_cache( cpu_id );
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
if (cpu_id != 0) {
|
||||
arm_a9mpcore_start_set_vector_base();
|
||||
|
||||
arm_gic_irq_initialize_secondary_cpu();
|
||||
|
||||
arm_cp15_set_domain_access_control(
|
||||
ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
|
||||
);
|
||||
_SMP_Start_multitasking_on_secondary_processor();
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
/* FIXME: Shutdown processor */
|
||||
while (1) {
|
||||
__asm__ volatile ("wfi");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
|
||||
{
|
||||
uint32_t addr_filt_start;
|
||||
uint32_t addr_filt_end;
|
||||
|
||||
/* Disable ECC. Preloader respectively UBoot enable ECC.
|
||||
But they do run without interrupts. Our BSP will enable interrupts
|
||||
and get spurious ECC error interrupts. Thus we disasable ECC
|
||||
until we either know about a better handling or Altera has modified
|
||||
it's SDRAM settings to not create possibly false ECC errors */
|
||||
uint32_t ctlcfg = alt_read_word( ALT_SDR_CTL_CTLCFG_ADDR );
|
||||
ctlcfg &= ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK;
|
||||
alt_write_word( ALT_SDR_CTL_CTLCFG_ADDR, ctlcfg );
|
||||
|
||||
/* Perform L3 remap register programming first by setting the desired new MPU
|
||||
address space 0 mapping. Assume BOOTROM in order to be able to boot the
|
||||
second core. */
|
||||
alt_addr_space_remap(
|
||||
ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
|
||||
ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM,
|
||||
ALT_ADDR_SPACE_H2F_ACCESSIBLE,
|
||||
ALT_ADDR_SPACE_LWH2F_ACCESSIBLE );
|
||||
|
||||
/* Next, adjust the L2 cache address filtering range. Set the start address
|
||||
* to the default reset value and retain the existing end address
|
||||
* configuration. */
|
||||
alt_l2_addr_filter_cfg_get( &addr_filt_start, &addr_filt_end );
|
||||
|
||||
if ( addr_filt_start != BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET ) {
|
||||
alt_l2_addr_filter_cfg_set( BSPSTART_L2_CACHE_ADDR_FILTERING_START_RESET,
|
||||
addr_filt_end );
|
||||
}
|
||||
|
||||
arm_a9mpcore_start_hook_1();
|
||||
bsp_start_copy_sections();
|
||||
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
REGION_ALIAS ("REGION_START", RAM);
|
||||
REGION_ALIAS ("REGION_VECTOR", RAM);
|
||||
REGION_ALIAS ("REGION_TEXT", RAM);
|
||||
REGION_ALIAS ("REGION_TEXT_LOAD", RAM);
|
||||
REGION_ALIAS ("REGION_RODATA", RAM);
|
||||
REGION_ALIAS ("REGION_RODATA_LOAD", RAM);
|
||||
REGION_ALIAS ("REGION_DATA", RAM);
|
||||
REGION_ALIAS ("REGION_DATA_LOAD", RAM);
|
||||
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
|
||||
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM);
|
||||
REGION_ALIAS ("REGION_FAST_DATA", RAM);
|
||||
REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM);
|
||||
REGION_ALIAS ("REGION_BSS", RAM);
|
||||
REGION_ALIAS ("REGION_WORK", RAM);
|
||||
REGION_ALIAS ("REGION_STACK", RAM);
|
||||
|
||||
bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
|
||||
bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
|
||||
|
||||
bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M;
|
||||
|
||||
bsp_vector_table_in_start_section = 1;
|
||||
|
||||
bsp_translation_table_base = ORIGIN (RAM_MMU);
|
||||
|
||||
INCLUDE linkcmds.armv4
|
||||
@@ -0,0 +1,18 @@
|
||||
MEMORY {
|
||||
RAM_MMU : ORIGIN = 0x00100000, LENGTH = 16k
|
||||
NOCACHE : ORIGIN = 0x00200000, LENGTH = 1M
|
||||
RAM : ORIGIN = 0x00300000, LENGTH = 1024M - 1M - 1M - 1M
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
.nocache : {
|
||||
bsp_section_nocache_begin = .;
|
||||
*(SORT(.bsp_nocache*))
|
||||
bsp_section_nocache_end = .;
|
||||
} > NOCACHE AT > NOCACHE
|
||||
bsp_section_nocache_size = bsp_section_nocache_end - bsp_section_nocache_begin;
|
||||
bsp_section_nocache_load_begin = LOADADDR (.nocache);
|
||||
bsp_section_nocache_load_end = bsp_section_nocache_load_begin + bsp_section_nocache_size;
|
||||
}
|
||||
|
||||
INCLUDE linkcmds.altcycv
|
||||
@@ -0,0 +1,3 @@
|
||||
bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 2;
|
||||
|
||||
INCLUDE linkcmds.altcycv_devkit
|
||||
89
c/src/lib/libbsp/arm/altera-cyclone-v/startup/nocache-heap.c
Normal file
89
c/src/lib/libbsp/arm/altera-cyclone-v/startup/nocache-heap.c
Normal file
@@ -0,0 +1,89 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief Heap handling for uncached RAM
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/nocache-heap.h>
|
||||
#include <rtems/score/heapimpl.h>
|
||||
#include <rtems/score/apimutex.h>
|
||||
|
||||
/** @brief Uncached RAM pool
|
||||
*
|
||||
* Allocate the whole bsp_nocache for the nocache heap */
|
||||
static char nocache_pool[1024
|
||||
* 1024] __attribute__( ( section( ".bsp_nocache" ) ) );
|
||||
|
||||
/** @brief Nocache heap
|
||||
*
|
||||
* Heap control for the uncached RAM heap */
|
||||
static Heap_Control nocache_heap;
|
||||
|
||||
/** @brief Init nocache heap
|
||||
*
|
||||
* Constructor for the uncached RAM heap
|
||||
* @returns 0 on succuss, error code from errno.h on failure
|
||||
*/
|
||||
void altera_cyclone_v_nocache_init_heap( void )
|
||||
{
|
||||
uintptr_t heap_status = 0;
|
||||
|
||||
heap_status = _Heap_Initialize(
|
||||
&nocache_heap,
|
||||
&nocache_pool[0],
|
||||
sizeof( nocache_pool ),
|
||||
0
|
||||
);
|
||||
assert( heap_status != 0 );
|
||||
}
|
||||
|
||||
/** @brief Allocate uncached RAM
|
||||
*
|
||||
* Allocates RAM from the uncached heap
|
||||
* @param size Number of bytes to be allocated
|
||||
* @returns Pointer to the allocated RAM
|
||||
*/
|
||||
void *altera_cyclone_v_nocache_malloc( const size_t size )
|
||||
{
|
||||
void* ret = NULL;
|
||||
|
||||
_RTEMS_Lock_allocator();
|
||||
ret = _Heap_Allocate( &nocache_heap, size );
|
||||
_RTEMS_Unlock_allocator();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/** @brief Free uncached RAM
|
||||
*
|
||||
* Releases RAM from the uncached heap
|
||||
* @param ptr Address of the RAM to be released
|
||||
*/
|
||||
void altera_cyclone_v_nocache_free( void *ptr )
|
||||
{
|
||||
if ( ptr != NULL ) {
|
||||
bool ok;
|
||||
|
||||
_RTEMS_Lock_allocator();
|
||||
ok = _Heap_Free( &nocache_heap, ptr );
|
||||
_RTEMS_Unlock_allocator();
|
||||
|
||||
assert( ok );
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user