forked from Imagelibrary/rtems
libchip: Add dwmac 10/100/1000 network driver
This commit is contained in:
Ralf Kirchner
committed by
Sebastian Huber
Sebastian Huber
parent
bbc5527010
commit
4953b72490
@@ -44,11 +44,20 @@ libnetchip_a_SOURCES = network/cs8900.c network/dec21140.c network/i82586.c \
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libnetchip_a_SOURCES += network/greth.c
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include_libchip_HEADERS += network/smc91111.h network/smc91111exp.h
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libnetchip_a_SOURCES += network/smc91111.c network/smc91111config.h
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include_libchip_HEADERS += network/dwmac.h
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libnetchip_a_SOURCES += \
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network/dwmac-1000-core.c \
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network/dwmac-1000-dma.c \
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network/dwmac-1000-ethernet-mac-ops.c \
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network/dwmac-core.c \
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network/dwmac-desc-com.c \
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network/dwmac-desc-enh.c \
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network/dwmac.c
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endif
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EXTRA_DIST += network/README network/README.cs8900 network/README.dec21140 \
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network/README.i82586 network/README.open_eth network/README.sonic \
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network/cs8900.c.bsp network/README.tulipclone
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network/cs8900.c.bsp network/README.tulipclone network/README.dwmac
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# rtc
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include_libchip_HEADERS += rtc/rtc.h rtc/icm7170.h rtc/m48t08.h \
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25
c/src/libchip/network/README.dwmac
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25
c/src/libchip/network/README.dwmac
Normal file
@@ -0,0 +1,25 @@
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About
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=====
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The dwmac* files implement libchip driver for the DWMAC 10/100/1000
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ethernet MAC. The DWMAC 10/100/1000 ethernet MAC is a Synopsys IP core.
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Target Support
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==============
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The target is required to provide the low level support routines as
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listed in the Configuration section of this file.
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The file cs8900.[ch].bsp are an example BSP files for DIMMPC target.
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Conditionals
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============
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None
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Todo
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====
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+ Add support for DWMAC 10/100. currently only support for DWMAC 1000
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is implemented
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Configuration
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=============
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See the dwmac.h header file for the documentation.
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238
c/src/libchip/network/dwmac-1000-core.c
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238
c/src/libchip/network/dwmac-1000-core.c
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@@ -0,0 +1,238 @@
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/**
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* @file
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*
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* @brief DWMAC 1000 on-chip Ethernet controllers Core Handling
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*
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* Functions and data which are specific to the DWMAC 1000 Core Handling.
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*/
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/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <assert.h>
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#include "dwmac-core.h"
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#include "dwmac-common.h"
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#define DWMAC_1000_CORE_DEBUG
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//#undef DWMAC_1000_CORE_DEBUG
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#ifdef DWMAC_1000_CORE_DEBUG
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#define DWMAC_1000_CORE_PRINT_DBG( fmt, args ... ) printk( fmt, ## args )
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#else
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#define DWMAC_1000_CORE_PRINT_DBG( fmt, args ... ) do { } while ( 0 )
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#endif
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#define DWMAC_1000_CORE_INIT \
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( \
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( MACGRP_MAC_CONFIGURATION_JD \
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| MACGRP_MAC_CONFIGURATION_BE ) \
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& ~MACGRP_MAC_CONFIGURATION_PS \
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)
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#define DWMAC_1000_CORE_HASH_TABLE_SIZE 256
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static volatile uint32_t *dwmac_1000_core_get_mac_addr_low(
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dwmac_common_context *self,
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const unsigned int mac_addr_index )
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{
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volatile uint32_t *addr = NULL;
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assert( self != NULL );
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assert( mac_addr_index <= 127 );
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if ( mac_addr_index > 15 ) {
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addr = &self->macgrp->mac_addr16_127[mac_addr_index].low;
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} else {
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addr = &self->macgrp->mac_addr0_15[mac_addr_index].low;
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}
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return addr;
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}
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static volatile uint32_t *dwmac_1000_core_get_mac_addr_high(
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dwmac_common_context *self,
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const unsigned int mac_addr_index )
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{
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volatile uint32_t *addr = NULL;
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assert( self != NULL );
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assert( mac_addr_index <= 127 );
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if ( mac_addr_index > 15 ) {
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addr = &self->macgrp->mac_addr16_127[mac_addr_index].high;
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} else {
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addr = &self->macgrp->mac_addr0_15[mac_addr_index].high;
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}
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return addr;
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}
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static void dwmac_1000_core_init( dwmac_common_context *self )
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{
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uint32_t value = self->macgrp->mac_configuration;
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value |= DWMAC_1000_CORE_INIT;
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if ( ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP1COE ) != 0
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|| ( self->dmagrp->hw_feature & DMAGRP_HW_FEATURE_RXTYP2COE ) != 0 ) {
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/* Enable RX checksum calculation offload to hardware */
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value |= MACGRP_MAC_CONFIGURATION_IPC;
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}
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/* No Jumbo- or Giant frames. The network stack does not support them */
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value &= ~MACGRP_MAC_CONFIGURATION_JE;
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value &= ~MACGRP_MAC_CONFIGURATION_TWOKPE;
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self->macgrp->mac_configuration = value;
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/* Mask GMAC interrupts */
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self->macgrp->interrupt_mask =
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MACGRP_INTERRUPT_MASK_RGSMIIIM
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| MACGRP_INTERRUPT_MASK_PCSLCHGIM
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| MACGRP_INTERRUPT_MASK_PCSANCIM
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| MACGRP_INTERRUPT_MASK_TSIM;
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/* mask out interrupts because we don't handle them yet */
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self->macgrp->mmc_receive_interrupt_mask = ( uint32_t ) ~0L;
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self->macgrp->mmc_transmit_interrupt_mask = ( uint32_t ) ~0L;
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self->macgrp->mmc_ipc_receive_interrupt_mask = ( uint32_t ) ~0L;
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}
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static void dwmac_1000_core_set_umac_addr(
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dwmac_common_context *self,
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const uint8_t *addr,
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unsigned int reg_n )
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{
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dwmac_core_set_mac_addr(
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addr,
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dwmac_1000_core_get_mac_addr_high( self, reg_n ),
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dwmac_1000_core_get_mac_addr_low( self, reg_n )
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);
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}
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static void dwmac_1000_core_set_hash_filter(
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dwmac_common_context *self,
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const bool add,
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struct ifreq *ifr )
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{
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int eno = 0;
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struct arpcom *ac = &self->arpcom;
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if ( add ) {
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eno = ether_addmulti( ifr, ac );
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} else {
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eno = ether_delmulti( ifr, ac );
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}
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if ( eno == ENETRESET ) {
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struct ether_multistep step;
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struct ether_multi *enm;
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unsigned int num_multi = 0;
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unsigned int index;
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ETHER_FIRST_MULTI( step, ac, enm );
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while ( enm != NULL ) {
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/* Find out how many multicast addresses we have to handle */
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uint64_t addrlo = 0;
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uint64_t addrhi = 0;
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memcpy( &addrlo, enm->enm_addrlo, ETHER_ADDR_LEN );
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memcpy( &addrhi, enm->enm_addrhi, ETHER_ADDR_LEN );
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num_multi += 1U + (uint32_t) ( addrhi - addrlo );
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}
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if ( num_multi > DWMAC_1000_CORE_HASH_TABLE_SIZE ) {
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/* Too many addresses to be hashed, Use the
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* pass all multi option instead */
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for ( index = 0; index < 8; ++index ) {
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self->macgrp->hash_table_reg[index] = 0xffffffff;
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}
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self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_PM;
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} else if ( num_multi > 0 ) {
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uint32_t hash_shadow[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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ETHER_FIRST_MULTI( step, ac, enm );
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while ( enm != NULL ) {
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uint64_t addrlo = 0;
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uint64_t addrhi = 0;
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memcpy( &addrlo, enm->enm_addrlo, ETHER_ADDR_LEN );
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memcpy( &addrhi, enm->enm_addrhi, ETHER_ADDR_LEN );
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while ( addrlo <= addrhi ) {
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/* XXX: ether_crc32_le() does not work, why? */
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uint32_t crc = ether_crc32_be( (uint8_t *) &addrlo, ETHER_ADDR_LEN );
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/* The upper 8 bits of the bit reversed 32 bit CRC are used for hash filtering.
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* The most significant bits determine the register to be used and the
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* least significant five bits determine which bit to be set within the register */
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uint32_t index_reg = ( crc >> 29 ) & 0x7;
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uint32_t index_bit = ( crc >> 24 ) & 0x1f;
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hash_shadow[index_reg] |= 1U << index_bit;
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++addrlo;
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}
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ETHER_NEXT_MULTI( step, enm );
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}
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for ( index = 0; index < 8; ++index ) {
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self->macgrp->hash_table_reg[index] = hash_shadow[index];
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}
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/* Hash filter for multicast */
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self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_HMC;
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} else {
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/* Set all hash registers to accect to accept no multicast packets */
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for ( index = 0; index < 8; ++index ) {
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self->macgrp->hash_table_reg[index] = 0x00000000;
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}
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/* Hash filter for multicast */
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self->macgrp->mac_frame_filter |= MACGRP_MAC_FRAME_FILTER_HMC;
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}
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DWMAC_1000_CORE_PRINT_DBG(
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"Frame Filter reg: 0x%08x\n",
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self->macgrp->mac_frame_filter
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);
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DWMAC_1000_CORE_PRINT_DBG(
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"Hash regs:\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n"
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"0x%08x\n",
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self->macgrp->hash_table_reg[0],
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self->macgrp->hash_table_reg[1],
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self->macgrp->hash_table_reg[2],
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self->macgrp->hash_table_reg[3],
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self->macgrp->hash_table_reg[4],
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self->macgrp->hash_table_reg[5],
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self->macgrp->hash_table_reg[6],
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self->macgrp->hash_table_reg[7]
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);
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}
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}
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const dwmac_common_core_ops dwmac_core_ops_1000 = {
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.core_init = dwmac_1000_core_init,
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.set_hash_filter = dwmac_1000_core_set_hash_filter,
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.set_umac_addr = dwmac_1000_core_set_umac_addr,
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};
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244
c/src/libchip/network/dwmac-1000-dma.c
Normal file
244
c/src/libchip/network/dwmac-1000-dma.c
Normal file
@@ -0,0 +1,244 @@
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/**
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* @file
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*
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* @brief DWMAC 1000 on-chip Ethernet controllers DMA handling
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*
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* Functions and data which are specific to the DWMAC 1000 DMA Handling.
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*/
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/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <errno.h>
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#include "dwmac-core.h"
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#include "dwmac-common.h"
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typedef enum {
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DWMAC100_OPERATION_MODE_TTC_CONTROL_64 = 0x00000000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_128 = 0x00004000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_192 = 0x00008000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_256 = 0x0000c000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_40 = 0x00010000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_32 = 0x00014000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_24 = 0x00018000,
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DWMAC100_OPERATION_MODE_TTC_CONTROL_16 = 0x0001c000,
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} dwmac1000_operation_mode_ttc_control;
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typedef enum {
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DWMAC100_OPERATION_MODE_RTC_CONTROL_64 = 0x00000000,
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DWMAC100_OPERATION_MODE_RTC_CONTROL_32 = 0x00000008,
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DWMAC100_OPERATION_MODE_RTC_CONTROL_96 = 0x00000010,
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DWMAC100_OPERATION_MODE_RTC_CONTROL_128 = 0x00000018,
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} dwmac1000_operation_mode_rtc_control;
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static int dwmac1000_dma_init(
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dwmac_common_context *self,
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const uint32_t pbl,
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const uint32_t fb,
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const uint32_t mb,
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const bool use_enhanced_desc,
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const uint32_t burst_len_4_support,
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const uint32_t burst_len_8_support,
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const uint32_t burst_len_16_support,
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const uint32_t burst_boundary,
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volatile dwmac_desc *dma_tx,
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volatile dwmac_desc *dma_rx )
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{
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int eno = 0;
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uint32_t value = self->dmagrp->bus_mode;
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int limit = 10;
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/* DMA SW reset */
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value |= DMAGRP_BUS_MODE_SWR;
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self->dmagrp->bus_mode = value;
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while ( limit-- ) {
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if ( !( self->dmagrp->bus_mode & DMAGRP_BUS_MODE_SWR ) )
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break;
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rtems_task_wake_after( rtems_clock_get_ticks_per_second() / 100 );
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}
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if ( limit < 0 ) {
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eno = EBUSY;
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} else {
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/*
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* Set the DMA PBL (Programmable Burst Length) mode
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*/
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if ( pbl >= DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_8 ) {
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value =
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DMAGRP_BUS_MODE_PBL( ( pbl + 1 ) / 8 ) | DMAGRP_BUS_MODE_RPBL(
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( pbl + 1 ) / 8 ) | DMAGRP_BUS_MODE_EIGHTXPBL;
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} else {
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value = DMAGRP_BUS_MODE_PBL( pbl + 1 ) | DMAGRP_BUS_MODE_RPBL( pbl + 1 );
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}
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/* Set the Fixed burst mode */
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if ( fb ) {
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value |= DMAGRP_BUS_MODE_FB;
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}
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/* Mixed Burst has no effect when fb is set */
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if ( mb ) {
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value |= DMAGRP_BUS_MODE_MB;
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}
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if ( use_enhanced_desc ) {
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value |= DMAGRP_BUS_MODE_ATDS;
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}
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self->dmagrp->bus_mode = value;
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/* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE
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* for supported bursts.
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*
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* Note: This is applicable only for revision GMACv3.61a. For
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* older version this register is reserved and shall have no
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* effect.
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*
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* Note:
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* For Fixed Burst Mode: if we directly write 0xFF to this
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* register using the configurations pass from platform code,
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* this would ensure that all bursts supported by core are set
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* and those which are not supported would remain ineffective.
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*
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* For Non Fixed Burst Mode: provide the maximum value of the
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* burst length. Any burst equal or below the provided burst
|
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* length would be allowed to perform. */
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value = self->dmagrp->axi_bus_mode;
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if ( burst_len_4_support ) {
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value |= DMAGRP_AXI_BUS_MODE_BLEND4;
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} else {
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value &= ~DMAGRP_AXI_BUS_MODE_BLEND4;
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}
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if ( burst_len_8_support ) {
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value |= DMAGRP_AXI_BUS_MODE_BLEND8;
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} else {
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value &= ~DMAGRP_AXI_BUS_MODE_BLEND8;
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}
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if ( burst_len_16_support ) {
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value |= DMAGRP_AXI_BUS_MODE_BLEND16;
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} else {
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value &= ~DMAGRP_AXI_BUS_MODE_BLEND16;
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}
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if ( burst_boundary ) {
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value |= DMAGRP_AXI_BUS_MODE_ONEKBBE;
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} else {
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value &= ~DMAGRP_AXI_BUS_MODE_ONEKBBE;
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}
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self->dmagrp->axi_bus_mode = value;
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/* Mask interrupts by writing to CSR7 */
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dwmac_core_enable_dma_irq_rx( self );
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dwmac_core_enable_dma_irq_tx( self );
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/* The base address of the RX/TX descriptor lists must be written into
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* DMA CSR3 and CSR4, respectively. */
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self->dmagrp->transmit_descr_list_addr = (uintptr_t) &dma_tx[0];
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self->dmagrp->receive_descr_list_addr = (uintptr_t) &dma_rx[0];
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}
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return eno;
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}
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static void dwmac1000_dma_operation_mode(
|
||||
dwmac_common_context *self,
|
||||
const unsigned int txmode,
|
||||
const unsigned int rxmode )
|
||||
{
|
||||
uint32_t value = self->dmagrp->operation_mode;
|
||||
|
||||
|
||||
if ( txmode == DWMAC_COMMON_DMA_MODE_STORE_AND_FORWARD ) {
|
||||
/* Transmit COE type 2 cannot be done in cut-through mode. */
|
||||
value |= DMAGRP_OPERATION_MODE_TSF;
|
||||
|
||||
/* Operating on second frame increase the performance
|
||||
* especially when transmit store-and-forward is used.*/
|
||||
value |= DMAGRP_OPERATION_MODE_OSF;
|
||||
} else {
|
||||
value &= ~DMAGRP_OPERATION_MODE_TSF;
|
||||
value &= ~DMAGRP_OPERATION_MODE_TTC_GET( value );
|
||||
|
||||
/* Set the transmit threshold */
|
||||
if ( txmode <= 32 ) {
|
||||
value |= DMAGRP_OPERATION_MODE_TTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_TTC_CONTROL_32
|
||||
);
|
||||
} else if ( txmode <= 64 ) {
|
||||
value = DMAGRP_OPERATION_MODE_TTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_TTC_CONTROL_64
|
||||
);
|
||||
} else if ( txmode <= 128 ) {
|
||||
value = DMAGRP_OPERATION_MODE_TTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_TTC_CONTROL_128
|
||||
);
|
||||
} else if ( txmode <= 192 ) {
|
||||
value = DMAGRP_OPERATION_MODE_TTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_TTC_CONTROL_192
|
||||
);
|
||||
} else {
|
||||
value = DMAGRP_OPERATION_MODE_TTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_TTC_CONTROL_256
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
if ( rxmode == DWMAC_COMMON_DMA_MODE_STORE_AND_FORWARD ) {
|
||||
value |= DMAGRP_OPERATION_MODE_RSF;
|
||||
} else {
|
||||
value &= ~DMAGRP_OPERATION_MODE_RSF;
|
||||
value &= DMAGRP_OPERATION_MODE_RTC_GET( value );
|
||||
|
||||
if ( rxmode <= 32 ) {
|
||||
value = DMAGRP_OPERATION_MODE_RTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_RTC_CONTROL_32
|
||||
);
|
||||
} else if ( rxmode <= 64 ) {
|
||||
value = DMAGRP_OPERATION_MODE_RTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_RTC_CONTROL_64
|
||||
);
|
||||
} else if ( rxmode <= 96 ) {
|
||||
value = DMAGRP_OPERATION_MODE_RTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_RTC_CONTROL_96
|
||||
);
|
||||
} else {
|
||||
value = DMAGRP_OPERATION_MODE_RTC_SET(
|
||||
value,
|
||||
DWMAC100_OPERATION_MODE_RTC_CONTROL_128
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
self->dmagrp->operation_mode = value;
|
||||
}
|
||||
|
||||
const dwmac_common_dma_ops dwmac_dma_ops_1000 = {
|
||||
.init = dwmac1000_dma_init,
|
||||
.dma_mode = dwmac1000_dma_operation_mode,
|
||||
};
|
||||
33
c/src/libchip/network/dwmac-1000-ethernet-mac-ops.c
Normal file
33
c/src/libchip/network/dwmac-1000-ethernet-mac-ops.c
Normal file
@@ -0,0 +1,33 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief Operations for the dwmac 1000 ethernet mac
|
||||
*
|
||||
* DWMAC_1000_ETHERNET_MAC_OPS will be accessible in the API header and can be
|
||||
* passed to the configuration data if handling a DWMAC 1000 driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include "dwmac-common.h"
|
||||
|
||||
extern const dwmac_common_dma_ops dwmac_dma_ops_1000;
|
||||
extern const dwmac_common_core_ops dwmac_core_ops_1000;
|
||||
|
||||
const dwmac_ethernet_mac_ops DWMAC_1000_ETHERNET_MAC_OPS =
|
||||
DWMAC_ETHERNET_MAC_OPS_INITIALIZER(
|
||||
&dwmac_core_ops_1000,
|
||||
&dwmac_dma_ops_1000
|
||||
);
|
||||
374
c/src/libchip/network/dwmac-common.h
Normal file
374
c/src/libchip/network/dwmac-common.h
Normal file
@@ -0,0 +1,374 @@
|
||||
/**
|
||||
* @file
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems./license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef DWMAC_COMMON_H_
|
||||
#define DWMAC_COMMON_H_
|
||||
|
||||
#define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1
|
||||
#define __BSD_VISIBLE 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <rtems.h>
|
||||
#include <rtems/rtems_bsdnet.h>
|
||||
#include <rtems/rtems_mii_ioctl.h>
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/sockio.h>
|
||||
#include <sys/mbuf.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_arp.h>
|
||||
#include <netinet/in.h>
|
||||
#include <netinet/if_ether.h>
|
||||
#include <netinet/in_systm.h>
|
||||
#include <netinet/ip.h>
|
||||
|
||||
#include <libchip/dwmac.h>
|
||||
#include "dwmac-desc.h"
|
||||
#include "dwmac-regs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define DWMAC_COMMON_DMA_MODE_STORE_AND_FORWARD 1 /* DMA STORE-AND-FORWARD Operation Mode */
|
||||
|
||||
/* Events */
|
||||
/* Common task events */
|
||||
#define DWMAC_COMMON_EVENT_TASK_INIT RTEMS_EVENT_1
|
||||
#define DWMAC_COMMON_EVENT_TASK_STOP RTEMS_EVENT_2
|
||||
|
||||
/* Events for the transmit task */
|
||||
#define DWMAC_COMMON_EVENT_TX_TRANSMIT_FRAME RTEMS_EVENT_3
|
||||
#define DWMAC_COMMON_EVENT_TX_FRAME_TRANSMITTED RTEMS_EVENT_4
|
||||
#define DWMAC_COMMON_EVENT_TX_BUMP_UP_DMA_THRESHOLD RTEMS_EVENT_5
|
||||
#define DWMAC_COMMON_EVENT_TX_PHY_STATUS_CHANGE RTEMS_EVENT_6
|
||||
|
||||
/* Events for the receive task */
|
||||
#define DWMAC_COMMON_EVENT_RX_FRAME_RECEIVED RTEMS_EVENT_3
|
||||
|
||||
#ifdef __ARM_ARCH_7A__
|
||||
#define DWMAC_COMMON_DSB() _ARM_Data_synchronization_barrier()
|
||||
#else /* __ARM_ARCH_7A__ */
|
||||
#define DWMAC_COMMON_DSB()
|
||||
#endif /* __ARM_ARCH_7A__ */
|
||||
|
||||
/* Foreward declarations */
|
||||
typedef struct dwmac_common_core_ops dwmac_common_core_ops;
|
||||
typedef struct dwmac_common_dma_ops dwmac_common_dma_ops;
|
||||
typedef struct dwmac_common_desc_ops dwmac_common_desc_ops;
|
||||
|
||||
typedef enum { /* IPC status */
|
||||
DWMAC_COMMON_RX_FRAME_STATUS_GOOD,
|
||||
DWMAC_COMMON_RX_FRAME_STATUS_DISCARD,
|
||||
DWMAC_COMMON_RX_FRAME_STATUS_CSUM_NONE,
|
||||
DWMAC_COMMON_RX_FRAME_STATUS_LLC_SNAP
|
||||
} dwmac_common_rx_frame_status;
|
||||
|
||||
typedef enum {
|
||||
DWMAC_COMMON_STATE_DOWN,
|
||||
DWMAC_COMMON_STATE_UP,
|
||||
|
||||
DWMAC_COMMON_STATE_COUNT
|
||||
} dwmac_common_state;
|
||||
|
||||
typedef struct {
|
||||
uint32_t link_down;
|
||||
uint32_t link_up;
|
||||
} dwmac_common_phy_status_counts;
|
||||
|
||||
typedef struct {
|
||||
uint32_t receive;
|
||||
uint32_t transmit;
|
||||
uint32_t tx_underflow;
|
||||
uint32_t tx_jabber;
|
||||
uint32_t rx_overflow;
|
||||
uint32_t rx_early;
|
||||
uint32_t rx_buf_unav;
|
||||
uint32_t rx_process_stopped;
|
||||
uint32_t rx_watchdog;
|
||||
uint32_t tx_early;
|
||||
uint32_t tx_buf_unav;
|
||||
uint32_t tx_process_stopped;
|
||||
uint32_t fatal_bus_error;
|
||||
uint32_t unhandled;
|
||||
} dwmac_common_dma_irq_counts;
|
||||
|
||||
typedef struct {
|
||||
uint32_t dest_addr_fail; /* When set, this bit indicates a frame that failed in the DA Filter in the MAC. */
|
||||
uint32_t crc_error; /* When set, this bit indicates that a CRC error occurred on the received frame. This field is valid only when the Last
|
||||
Descriptor (RDES0[8]) is set. */
|
||||
uint32_t receive_error; /* When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted during frame
|
||||
reception. Error can be of less or no extension, or error (rxd !=0xf) during extension. */
|
||||
uint32_t watchdog_timeout; /* When set, this bit indicates that the receive Watchdog Timer has expired while receiving the current frame and the
|
||||
current frame is truncated after the Watchdog Timeout. */
|
||||
uint32_t late_collision; /* When set, this bit indicates that a late collision has occurred while receiving the frame in the half-duplex mode. */
|
||||
uint32_t giant_frame; /* When advanced timestamp feature is present, when set, this bit indicates that a snapshot of the Timestamp is
|
||||
written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is
|
||||
set.
|
||||
When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates that the 16-bit IPv4 Header checksum
|
||||
calculated by the EMAC did not match the received checksum bytes.
|
||||
Otherwise, this bit, when set, indicates the Giant frame Status. Giant frames are larger than 1,518-byte (or
|
||||
1,522-byte for VLAN or 2,000-byte when Bit 27 (2KPE) of MAC Configuration register is set) normal frames and
|
||||
larger than 9,018-byte (9,022-byte for VLAN) frame when Jumbo frame processing is enabled. */
|
||||
uint32_t overflow_error; /* When set, this bit indicates that the received frame was damaged because of buffer overflow in MTL.
|
||||
Note: This bit is set only when the DMA transfers a partial frame to the application. This happens only when the RX
|
||||
FIFO buffer is operating in the threshold mode. In the store-and-forward mode, all partial frames are dropped
|
||||
completely in RX FIFO buffer. */
|
||||
uint32_t descriptor_error; /* When set, this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor
|
||||
buffers, and that the DMA does not own the Next descriptor. The frame is truncated. This field is valid only when the
|
||||
Last Descriptor (RDES0[8]) is set. */
|
||||
uint32_t source_addr_fail; /* When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC. */
|
||||
uint32_t length_error; /* When set, this bit indicates that the actual length of the frame received and that the Length/ Type field does not
|
||||
match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset. */
|
||||
uint32_t vlan_tag; /* When set, this bit indicates that the frame to which this descriptor is pointing is a VLAN frame tagged by the MAC.
|
||||
The VLAN tagging depends on checking the VLAN fields of received frame based on the Register 7 (VLAN Tag
|
||||
Register) setting. */
|
||||
uint32_t ethernet_frames; /* When set, this bit indicates that the receive frame is an Ethernet-type frame (the LT field is greater than or equal to
|
||||
0x0600). When this bit is reset, it indicates that the received frame is an IEEE802.3 frame. This bit is not valid for
|
||||
Runt frames less than 14 bytes. */
|
||||
uint32_t dribble_bit_error; /* When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). This bit is valid
|
||||
only in the MII Mode. */
|
||||
} dwmac_common_desc_status_counts_rx;
|
||||
|
||||
typedef struct {
|
||||
uint32_t jabber; /* When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only set when Bit 22
|
||||
(Jabber Disable) of Register 0 (MAC Configuration Register) is not set. */
|
||||
uint32_t frame_flushed; /* When set, this bit indicates that the DMA or MTL flushed the frame because of a software Flush command given by
|
||||
the CPU. */
|
||||
uint32_t losscarrier; /* When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the gmii_crs_i
|
||||
signal was inactive for one or more transmit clock periods during frame transmission). This is valid only for the
|
||||
frames transmitted without collision when the MAC operates in the half-duplex mode. */
|
||||
uint32_t no_carrier; /* When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during transmission. */
|
||||
uint32_t excessive_collisions; /* When set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to
|
||||
transmit the current frame. If Bit 9 (Disable Retry) bit in the Register 0 (MAC Configuration Register) is set, this bit
|
||||
is set after the first collision, and the transmission of the frame is aborted. */
|
||||
uint32_t excessive_deferral; /* When set, this bit indicates that the transmission has ended because of excessive deferral of over 24,288 bit times
|
||||
(155,680 bits times in 1,000-Mbps mode or if Jumbo frame is enabled) if Bit 4 (Deferral Check) bit in Register 0
|
||||
(MAC Configuration Register) is set high. */
|
||||
uint32_t underflow; /* When set, this bit indicates that the MAC aborted the frame because the data arrived late from the Host memory.
|
||||
Underflow Error indicates that the DMA encountered an empty transmit buffer while transmitting the frame. The
|
||||
transmission process enters the Suspended state and sets both Transmit Underflow (Register 5[5]) and Transmit
|
||||
Interrupt (Register 5[0]). */
|
||||
uint32_t ip_header_error; /* When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header. The transmitter
|
||||
checks the header length in the IPv4 packet against the number of header bytes received from the application and
|
||||
indicates an error status if there is a mismatch. For IPv6 frames, a header error is reported if the main header length
|
||||
is not 40 bytes. Furthermore, the Ethernet Length/Type field value for an IPv4 or IPv6 frame must match the IP
|
||||
header version received with the packet. For IPv4 frames, an error status is also indicated if the Header Length field
|
||||
has a value less than 0x5. */
|
||||
uint32_t payload_error; /* When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP datagram payload.
|
||||
The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP,
|
||||
UDP, or ICMP packet bytes received from the application and issues an error status in case of a mismatch. */
|
||||
uint32_t deferred; /* When set, this bit indicates that the MAC defers before transmission because of the presence of carrier. This bit is
|
||||
valid only in the half-duplex mode. */
|
||||
uint32_t vlan; /* When set, this bit indicates that the transmitted frame is a VLAN-type frame. */
|
||||
} dwmac_common_desc_status_counts_tx;
|
||||
|
||||
typedef struct {
|
||||
uint32_t errors; /* Frames with errors */
|
||||
uint32_t dropped; /* Frames dropped */
|
||||
uint32_t frames_good; /* Frames passed to the network stack */
|
||||
uint32_t bytes_good; /* Sum of bytes passed to the network stack */
|
||||
uint32_t frames; /* Frames handled (good or bad) */
|
||||
uint32_t dma_suspended; /* The receive DMA was supended due to lack of descriptors */
|
||||
} dwmac_common_rx_frame_counts;
|
||||
|
||||
typedef struct {
|
||||
uint32_t frames_from_stack; /* Frames received from the network stack fro tranmission */
|
||||
uint32_t frames_to_dma; /* Number of frames transmitted to DMA */
|
||||
uint32_t packets_to_dma; /* Number of packets transmitted to DMA*/
|
||||
uint32_t bytes_to_dma; /* Number of bytes transmitted */
|
||||
uint32_t packet_errors; /* Packets with errors */
|
||||
uint32_t packets_tranmitted_by_DMA; /* Packets tranmitted by the DMA */
|
||||
} dwmac_common_tx_frame_counts;
|
||||
|
||||
typedef struct {
|
||||
dwmac_common_phy_status_counts phy_status_counts;
|
||||
dwmac_common_dma_irq_counts dma_irq_counts;
|
||||
dwmac_common_desc_status_counts_rx desc_status_counts_rx;
|
||||
dwmac_common_desc_status_counts_tx desc_status_counts_tx;
|
||||
dwmac_common_rx_frame_counts frame_counts_rx;
|
||||
dwmac_common_tx_frame_counts frame_counts_tx;
|
||||
} dwmac_common_stats;
|
||||
|
||||
typedef struct {
|
||||
struct arpcom arpcom;
|
||||
struct rtems_bsdnet_ifconfig *bsd_config;
|
||||
struct rtems_mdio_info mdio;
|
||||
rtems_id task_id_rx;
|
||||
rtems_id task_id_tx;
|
||||
rtems_id task_id_control;
|
||||
void *arg;
|
||||
volatile macgrp *macgrp;
|
||||
volatile dmagrp *dmagrp;
|
||||
unsigned int csr_clock;
|
||||
dwmac_common_state state;
|
||||
dwmac_common_stats stats;
|
||||
unsigned int dma_threshold_control;
|
||||
volatile dwmac_desc *dma_tx;
|
||||
volatile dwmac_desc *dma_rx;
|
||||
unsigned int idx_rx;
|
||||
struct mbuf **mbuf_addr_rx;
|
||||
struct mbuf **mbuf_addr_tx;
|
||||
const dwmac_cfg *CFG;
|
||||
} dwmac_common_context;
|
||||
|
||||
struct dwmac_common_core_ops {
|
||||
/* MAC core initialization */
|
||||
void (*core_init) ( dwmac_common_context *self );
|
||||
|
||||
/* Multicast filter setting */
|
||||
void (*set_hash_filter) (
|
||||
dwmac_common_context *self,
|
||||
const bool add,
|
||||
struct ifreq *ifr );
|
||||
|
||||
/* Set/Get Unicast MAC addresses */
|
||||
void (*set_umac_addr) (
|
||||
dwmac_common_context *ioaddr,
|
||||
const unsigned char *addr,
|
||||
const unsigned int reg_n );
|
||||
};
|
||||
|
||||
struct dwmac_common_dma_ops {
|
||||
/* DMA core initialization */
|
||||
int (*init) (
|
||||
dwmac_common_context *self,
|
||||
const uint32_t pbl,
|
||||
const uint32_t fb,
|
||||
const uint32_t mb,
|
||||
const bool use_enhanced_desc,
|
||||
const uint32_t burst_len_4_support,
|
||||
const uint32_t burst_len_8_support,
|
||||
const uint32_t burst_len_16_support,
|
||||
const uint32_t burst_boundary,
|
||||
volatile dwmac_desc *dma_tx,
|
||||
volatile dwmac_desc *dma_rx );
|
||||
|
||||
/* Set tx/rx threshold in the csr6 register
|
||||
* An invalid value enables the store-and-forward mode */
|
||||
void (*dma_mode) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int txmode,
|
||||
const unsigned int rxmode );
|
||||
};
|
||||
|
||||
struct dwmac_common_desc_ops {
|
||||
/* Verify that it is OK to use the selected descriptor operations */
|
||||
int (*validate) ( dwmac_common_context *self );
|
||||
bool (*use_enhanced_descs) ( dwmac_common_context *self );
|
||||
|
||||
/* DMA RX descriptor ring allocation */
|
||||
int (*create_rx_desc) ( dwmac_common_context *self );
|
||||
|
||||
/* DMA TX descriptor ring allocation */
|
||||
int (*create_tx_desc) ( dwmac_common_context *self );
|
||||
|
||||
/* Free DMA RX descriptor ring */
|
||||
int (*destroy_rx_desc) ( dwmac_common_context *self );
|
||||
|
||||
/* Free DMA TX descriptor ring */
|
||||
int (*destroy_tx_desc) ( dwmac_common_context *self );
|
||||
|
||||
/* DMA RX descriptor initialization */
|
||||
void (*init_rx_desc) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int index );
|
||||
|
||||
/* DMA TX descriptor ring initialization */
|
||||
void (*init_tx_desc) ( dwmac_common_context *self );
|
||||
|
||||
/* Free rx data buffers */
|
||||
void (*release_rx_bufs) ( dwmac_common_context *self );
|
||||
|
||||
/* Allocate a data buffer */
|
||||
struct mbuf *(*alloc_data_buf)( dwmac_common_context *self );
|
||||
|
||||
/* Free tx data buffers */
|
||||
void (*release_tx_bufs) ( dwmac_common_context *self );
|
||||
|
||||
/* Invoked by the xmit function to prepare the tx descriptor */
|
||||
void (*prepare_tx_desc) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx,
|
||||
const bool is_first,
|
||||
const size_t len,
|
||||
const void *pdata );
|
||||
|
||||
/* Set/get the owner of the descriptor */
|
||||
void (*release_tx_ownership) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
bool (*am_i_tx_owner) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
|
||||
/* Invoked by the xmit function to close the tx descriptor */
|
||||
void (*close_tx_desc) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
|
||||
/* Clean the tx descriptor as soon as the tx irq is received */
|
||||
void (*release_tx_desc) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
|
||||
/* Last tx segment reports the transmit status */
|
||||
int (*get_tx_ls) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
|
||||
/* Return the transmit status looking at the TDES1 */
|
||||
int (*tx_status) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int idx_tx );
|
||||
|
||||
/* Handle extra events on specific interrupts hw dependent */
|
||||
bool (*am_i_rx_owner) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int desc_idx );
|
||||
|
||||
/* Get the receive frame size */
|
||||
size_t (*get_rx_frame_len) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int desc_idx );
|
||||
|
||||
/* Return the reception status looking at the RDES1 */
|
||||
dwmac_common_rx_frame_status (*rx_status) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int desc_idx );
|
||||
bool (*is_first_rx_segment) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int descriptor_index );
|
||||
bool (*is_last_rx_segment) (
|
||||
dwmac_common_context *self,
|
||||
const unsigned int descriptor_index );
|
||||
void (*print_tx_desc) (
|
||||
volatile dwmac_desc *p,
|
||||
const unsigned int count );
|
||||
void (*print_rx_desc) (
|
||||
volatile dwmac_desc *p,
|
||||
const unsigned int count );
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* DWMAC_COMMON_H_ */
|
||||
406
c/src/libchip/network/dwmac-core.c
Normal file
406
c/src/libchip/network/dwmac-core.c
Normal file
@@ -0,0 +1,406 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief DWMAC 10/100/1000 Network Interface Controllers Core Handling
|
||||
*
|
||||
* DWMAC 10/100/1000 on-chip Synopsys IP Ethernet controllers.
|
||||
* Driver core handling.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include "dwmac-core.h"
|
||||
#include "dwmac-common.h"
|
||||
#include "dwmac-regs.h"
|
||||
|
||||
#undef DWMAC_CORE_DEBUG
|
||||
#ifdef DWMAC_CORE_DEBUG
|
||||
#define DWMAC_CORE_PRINT_DBG( fmt, args ... ) printk( fmt, ## args )
|
||||
#else
|
||||
#define DWMAC_CORE_PRINT_DBG( fmt, args ... ) do { } while ( 0 )
|
||||
#endif
|
||||
|
||||
/* DMA default interrupt masks */
|
||||
#define DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_RX \
|
||||
( \
|
||||
DMAGRP_INTERRUPT_ENABLE_NIE \
|
||||
| DMAGRP_INTERRUPT_ENABLE_RIE \
|
||||
)
|
||||
#define DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_TX \
|
||||
( \
|
||||
DMAGRP_INTERRUPT_ENABLE_NIE \
|
||||
| DMAGRP_INTERRUPT_ENABLE_TIE \
|
||||
| DMAGRP_INTERRUPT_ENABLE_FBE \
|
||||
| DMAGRP_INTERRUPT_ENABLE_UNE \
|
||||
| DMAGRP_INTERRUPT_ENABLE_AIE \
|
||||
)
|
||||
|
||||
#define DWMAC_CORE_INTR_STATUS_DEFAULT_MASK_RX \
|
||||
( \
|
||||
DMAGRP_STATUS_NIS \
|
||||
| DMAGRP_STATUS_RI \
|
||||
)
|
||||
#define DWMAC_CORE_INTR_STATUS_DEFAULT_MASK_TX \
|
||||
( \
|
||||
DMAGRP_STATUS_NIS \
|
||||
| DMAGRP_STATUS_TI \
|
||||
| DMAGRP_STATUS_FBI \
|
||||
| DMAGRP_STATUS_UNF \
|
||||
| DMAGRP_STATUS_AIS \
|
||||
)
|
||||
|
||||
/* CSR1 enables the transmit DMA to check for new descriptor */
|
||||
void dwmac_core_dma_restart_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->transmit_poll_demand = 1;
|
||||
}
|
||||
|
||||
void dwmac_core_enable_dma_irq_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->interrupt_enable |= DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_TX;
|
||||
}
|
||||
|
||||
void dwmac_core_enable_dma_irq_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->interrupt_enable |= DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_RX;
|
||||
}
|
||||
|
||||
void dwmac_core_disable_dma_irq_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->interrupt_enable &= ~DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_TX;
|
||||
}
|
||||
|
||||
void dwmac_core_reset_dma_irq_status_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->status = DWMAC_CORE_INTR_STATUS_DEFAULT_MASK_TX;
|
||||
}
|
||||
|
||||
void dwmac_core_reset_dma_irq_status_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->status = DWMAC_CORE_INTR_STATUS_DEFAULT_MASK_RX;
|
||||
}
|
||||
|
||||
void dwmac_core_disable_dma_irq_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->interrupt_enable &= ~DWMAC_CORE_INTR_ENABLE_DEFAULT_MASK_RX;
|
||||
}
|
||||
|
||||
void dwmac_core_dma_start_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->operation_mode |= DMAGRP_OPERATION_MODE_ST;
|
||||
}
|
||||
|
||||
void dwmac_core_dma_stop_tx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->operation_mode &= ~DMAGRP_OPERATION_MODE_ST;
|
||||
}
|
||||
|
||||
void dwmac_core_dma_start_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->operation_mode |= DMAGRP_OPERATION_MODE_SR;
|
||||
}
|
||||
|
||||
void dwmac_core_dma_stop_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->operation_mode &= ~DMAGRP_OPERATION_MODE_SR;
|
||||
}
|
||||
|
||||
void dwmac_core_dma_restart_rx( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->receive_poll_demand = 1;
|
||||
}
|
||||
|
||||
#ifdef DWMAC_CORE_DEBUG
|
||||
static void show_tx_process_state( const uint32_t status )
|
||||
{
|
||||
const uint32_t STATE = DMAGRP_STATUS_TS_GET( status );
|
||||
|
||||
|
||||
switch ( STATE ) {
|
||||
case 0:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Stopped): Reset or Stop command\n" );
|
||||
break;
|
||||
case 1:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Running):Fetching the Tx desc\n" );
|
||||
break;
|
||||
case 2:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Running): Waiting for end of tx\n" );
|
||||
break;
|
||||
case 3:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Running): Reading the data "
|
||||
"and queuing the data into the Tx buf\n" );
|
||||
break;
|
||||
case 6:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Suspended): Tx Buff Underflow "
|
||||
"or an unavailable Transmit descriptor\n" );
|
||||
break;
|
||||
case 7:
|
||||
DWMAC_CORE_PRINT_DBG( "- TX (Running): Closing Tx descriptor\n" );
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void show_rx_process_state( const uint32_t status )
|
||||
{
|
||||
const uint32_t STATE = DMAGRP_STATUS_RS_GET( status );
|
||||
|
||||
|
||||
switch ( STATE ) {
|
||||
case 0:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Stopped): Reset or Stop command\n" );
|
||||
break;
|
||||
case 1:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Running): Fetching the Rx desc\n" );
|
||||
break;
|
||||
case 2:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Running):Checking for end of pkt\n" );
|
||||
break;
|
||||
case 3:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Running): Waiting for Rx pkt\n" );
|
||||
break;
|
||||
case 4:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Suspended): Unavailable Rx buf\n" );
|
||||
break;
|
||||
case 5:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Running): Closing Rx descriptor\n" );
|
||||
break;
|
||||
case 6:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX(Running): Flushing the current frame"
|
||||
" from the Rx buf\n" );
|
||||
break;
|
||||
case 7:
|
||||
DWMAC_CORE_PRINT_DBG( "- RX (Running): Queuing the Rx frame"
|
||||
" from the Rx buf into memory\n" );
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* DWMAC_CORE_DEBUG */
|
||||
#define show_tx_process_state( status )
|
||||
#define show_rx_process_state( status )
|
||||
#endif /* DWMAC_CORE_DEBUG */
|
||||
|
||||
void dwmac_core_dma_interrupt( void *arg )
|
||||
{
|
||||
dwmac_common_context *self = (dwmac_common_context *) arg;
|
||||
dwmac_common_dma_irq_counts *count = &self->stats.dma_irq_counts;
|
||||
rtems_event_set events_receive = 0;
|
||||
rtems_event_set events_transmit = 0;
|
||||
|
||||
/* Get interrupt status */
|
||||
uint32_t irq_status = self->dmagrp->status & self->dmagrp->interrupt_enable;
|
||||
uint32_t irq_handled = 0;
|
||||
uint32_t irq_disable = 0;
|
||||
|
||||
|
||||
DWMAC_CORE_PRINT_DBG( "%s: [CSR5: 0x%08x]\n", __func__, irq_status );
|
||||
|
||||
/* It displays the DMA process states (CSR5 register) if DWMAC_CORE_DEBUG is #defined */
|
||||
show_tx_process_state( self->dmagrp->status );
|
||||
show_rx_process_state( self->dmagrp->status );
|
||||
|
||||
/* Is there any abnormal interrupt? */
|
||||
if ( irq_status & DMAGRP_STATUS_AIS ) {
|
||||
DWMAC_CORE_PRINT_DBG( "CSR5[15] DMA ABNORMAL IRQ: " );
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_UNF ) {
|
||||
DWMAC_CORE_PRINT_DBG( "transmit underflow\n" );
|
||||
events_transmit |= DWMAC_COMMON_EVENT_TX_BUMP_UP_DMA_THRESHOLD;
|
||||
irq_handled |= DMAGRP_STATUS_UNF;
|
||||
irq_disable |= DMAGRP_INTERRUPT_ENABLE_UNE;
|
||||
++count->tx_underflow;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_TJT ) {
|
||||
DWMAC_CORE_PRINT_DBG( "transmit jabber\n" );
|
||||
irq_handled |= DMAGRP_STATUS_TJT;
|
||||
++count->tx_jabber;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_OVF ) {
|
||||
DWMAC_CORE_PRINT_DBG( "recv overflow\n" );
|
||||
irq_handled |= DMAGRP_STATUS_OVF;
|
||||
++count->rx_overflow;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_TU ) {
|
||||
DWMAC_CORE_PRINT_DBG( "transmit buffer unavailable\n" );
|
||||
irq_handled |= DMAGRP_STATUS_TU;
|
||||
++count->tx_buf_unav;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_RU ) {
|
||||
DWMAC_CORE_PRINT_DBG( "receive buffer unavailable\n" );
|
||||
irq_handled |= DMAGRP_STATUS_RU;
|
||||
++count->rx_buf_unav;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_RPS ) {
|
||||
DWMAC_CORE_PRINT_DBG( "receive process stopped\n" );
|
||||
irq_handled |= DMAGRP_STATUS_RPS;
|
||||
++count->rx_process_stopped;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_RWT ) {
|
||||
DWMAC_CORE_PRINT_DBG( "receive watchdog\n" );
|
||||
irq_handled |= DMAGRP_STATUS_RWT;
|
||||
++count->rx_watchdog;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_ETI ) {
|
||||
DWMAC_CORE_PRINT_DBG( "transmit early interrupt\n" );
|
||||
irq_handled |= DMAGRP_STATUS_ETI;
|
||||
++count->tx_early;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_ERI ) {
|
||||
DWMAC_CORE_PRINT_DBG( "receive early interrupt\n" );
|
||||
irq_handled |= DMAGRP_STATUS_ERI;
|
||||
++count->rx_early;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_TPS ) {
|
||||
DWMAC_CORE_PRINT_DBG( "transmit process stopped\n" );
|
||||
events_transmit |= DWMAC_COMMON_EVENT_TASK_INIT;
|
||||
irq_handled |= DMAGRP_STATUS_TPS;
|
||||
irq_disable |= DMAGRP_INTERRUPT_ENABLE_TSE;
|
||||
++count->tx_process_stopped;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_FBI ) {
|
||||
DWMAC_CORE_PRINT_DBG( "fatal bus error\n" );
|
||||
events_transmit |= DWMAC_COMMON_EVENT_TASK_INIT;
|
||||
irq_handled |= DMAGRP_STATUS_FBI;
|
||||
irq_disable |= DMAGRP_INTERRUPT_ENABLE_FBE;
|
||||
++count->fatal_bus_error;
|
||||
}
|
||||
|
||||
irq_handled |= DMAGRP_STATUS_AIS;
|
||||
}
|
||||
|
||||
/* Is there any normal interrupt? */
|
||||
if ( irq_status & DMAGRP_STATUS_NIS ) {
|
||||
/* Transmit interrupt */
|
||||
if ( irq_status & DMAGRP_STATUS_TI ) {
|
||||
events_transmit |= DWMAC_COMMON_EVENT_TX_FRAME_TRANSMITTED;
|
||||
irq_handled |= DMAGRP_STATUS_TI;
|
||||
irq_disable |= DMAGRP_INTERRUPT_ENABLE_TIE;
|
||||
++count->transmit;
|
||||
}
|
||||
|
||||
/* Receive interrupt */
|
||||
if ( irq_status & DMAGRP_STATUS_RI ) {
|
||||
events_receive |= DWMAC_COMMON_EVENT_RX_FRAME_RECEIVED;
|
||||
irq_handled |= DMAGRP_STATUS_RI;
|
||||
irq_disable |= DMAGRP_INTERRUPT_ENABLE_RIE;
|
||||
++count->receive;
|
||||
}
|
||||
|
||||
irq_handled |= DMAGRP_STATUS_NIS;
|
||||
}
|
||||
|
||||
/* Optional hardware blocks, interrupts should be disabled */
|
||||
if ( irq_status
|
||||
& ( DMAGRP_STATUS_GMI | DMAGRP_STATUS_GLI ) ) {
|
||||
DWMAC_CORE_PRINT_DBG( "%s: unexpected status %08x\n", __func__,
|
||||
irq_status );
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_GMI ) {
|
||||
irq_handled |= DMAGRP_STATUS_GMI;
|
||||
++count->unhandled;
|
||||
}
|
||||
|
||||
if ( irq_status & DMAGRP_STATUS_GLI ) {
|
||||
irq_handled |= DMAGRP_STATUS_GLI;
|
||||
++count->unhandled;
|
||||
}
|
||||
}
|
||||
|
||||
/* Count remaining unhandled interrupts (there should not be any) */
|
||||
if ( ( irq_status & 0x1FFCF ) != irq_handled ) {
|
||||
++count->unhandled;
|
||||
}
|
||||
|
||||
/* Disable interrupts which need further handling by tasks.
|
||||
* The tasks will re-enable them. */
|
||||
self->dmagrp->interrupt_enable &= ~irq_disable;
|
||||
|
||||
/* Clear interrupts */
|
||||
self->dmagrp->status = irq_handled;
|
||||
|
||||
/* Send events to receive task */
|
||||
if ( events_receive != 0 ) {
|
||||
(void) rtems_bsdnet_event_send( self->task_id_rx, events_receive );
|
||||
}
|
||||
|
||||
/* Send events to transmit task */
|
||||
if ( events_transmit != 0 ) {
|
||||
(void) rtems_bsdnet_event_send( self->task_id_tx, events_transmit );
|
||||
}
|
||||
|
||||
DWMAC_CORE_PRINT_DBG( "\n\n" );
|
||||
}
|
||||
|
||||
void dwmac_core_dma_flush_tx_fifo( dwmac_common_context *self )
|
||||
{
|
||||
self->dmagrp->operation_mode |= DMAGRP_OPERATION_MODE_FTF;
|
||||
|
||||
do {
|
||||
} while ( ( self->dmagrp->operation_mode & DMAGRP_OPERATION_MODE_FTF ) != 0 );
|
||||
}
|
||||
|
||||
void dwmac_core_set_mac_addr(
|
||||
const uint8_t addr[6],
|
||||
volatile uint32_t *reg_high,
|
||||
volatile uint32_t *reg_low )
|
||||
{
|
||||
uint32_t data = MAC_HIGH_ADDRHI( ( addr[5] << 8 ) | addr[4] );
|
||||
|
||||
|
||||
/* For MAC Addr registers se have to set the Address Enable (AE)
|
||||
* bit that has no effect on the High Reg 0 where the bit 31 (MO)
|
||||
* is RO.
|
||||
*/
|
||||
data |= MAC_HIGH_AE;
|
||||
*reg_high = data;
|
||||
|
||||
data =
|
||||
( (uint32_t) addr[3] << 24 )
|
||||
| ( (uint32_t) addr[2] << 16 )
|
||||
| ( (uint32_t) addr[1] << 8 )
|
||||
| addr[0];
|
||||
*reg_low = data;
|
||||
}
|
||||
|
||||
/* Enable disable MAC RX/TX */
|
||||
void dwmac_core_set_mac(
|
||||
dwmac_common_context *self,
|
||||
const bool enable )
|
||||
{
|
||||
uint32_t value = self->macgrp->mac_configuration;
|
||||
|
||||
|
||||
if ( enable ) {
|
||||
value |= MACGRP_MAC_CONFIGURATION_RE | MACGRP_MAC_CONFIGURATION_TE;
|
||||
} else {
|
||||
value &= ~( MACGRP_MAC_CONFIGURATION_RE | MACGRP_MAC_CONFIGURATION_TE );
|
||||
}
|
||||
|
||||
self->macgrp->mac_configuration = value;
|
||||
}
|
||||
76
c/src/libchip/network/dwmac-core.h
Normal file
76
c/src/libchip/network/dwmac-core.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief DWMAC 10/100/1000 Network Interface Controllers Core Handling
|
||||
*
|
||||
* DWMAC 10/100/1000 on-chip Synopsys IP Ethernet controllers.
|
||||
* Driver core handling.
|
||||
* This header file is NOT part of the driver API.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef DWMAC_CORE_H_
|
||||
#define DWMAC_CORE_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "dwmac-common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
void dwmac_core_set_mac_addr(
|
||||
const uint8_t addr[6],
|
||||
volatile uint32_t *reg_high,
|
||||
volatile uint32_t *reg_low );
|
||||
|
||||
void dwmac_core_set_mac(
|
||||
dwmac_common_context *self,
|
||||
const bool enable );
|
||||
|
||||
void dwmac_core_dma_start_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_stop_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_start_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_stop_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_restart_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_restart_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_enable_dma_irq_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_enable_dma_irq_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_disable_dma_irq_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_disable_dma_irq_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_reset_dma_irq_status_tx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_reset_dma_irq_status_rx( dwmac_common_context *self );
|
||||
|
||||
void dwmac_core_dma_interrupt( void *arg );
|
||||
|
||||
void dwmac_core_dma_flush_tx_fifo( dwmac_common_context *self );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* DWMAC_CORE_H_ */
|
||||
60
c/src/libchip/network/dwmac-desc-com.c
Normal file
60
c/src/libchip/network/dwmac-desc-com.c
Normal file
@@ -0,0 +1,60 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief DWMAC 10/100/1000 Common Descriptor Handling
|
||||
*
|
||||
* DWMAC 10/100/1000 on-chip Ethernet controllers.
|
||||
* Functions which are common to normal and enhanced DMA descriptors.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#include "dwmac-desc-com.h"
|
||||
|
||||
#undef DWMAC_DESC_COM_DEBUG
|
||||
#ifdef DWMAC_DESC_COM_DEBUG
|
||||
#define DWMAC_DESC_COM_PRINT_DBG( fmt, args ... ) printk( fmt, ## args )
|
||||
#else
|
||||
#define DWMAC_DESC_COM_PRINT_DBG( fmt, args ... ) do { } while ( 0 )
|
||||
#endif
|
||||
|
||||
struct mbuf *dwmac_desc_com_new_mbuf( dwmac_common_context *self ) {
|
||||
struct ifnet *ifp = &self->arpcom.ac_if;
|
||||
struct mbuf *m = NULL;
|
||||
|
||||
|
||||
MGETHDR( m, M_DONTWAIT, MT_DATA );
|
||||
|
||||
if ( m != NULL ) {
|
||||
MCLGET( m, M_DONTWAIT );
|
||||
|
||||
if ( m->m_ext.ext_buf != NULL ) {
|
||||
if ( ( m->m_flags & M_EXT ) != 0 ) {
|
||||
/* Set receive interface */
|
||||
m->m_pkthdr.rcvif = ifp;
|
||||
|
||||
/* Make sure packet data will be aligned */
|
||||
m->m_data = mtod( m, char * ) + ETHER_ALIGN;
|
||||
return m;
|
||||
} else {
|
||||
m_free( m );
|
||||
}
|
||||
} else {
|
||||
m_free( m );
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
44
c/src/libchip/network/dwmac-desc-com.h
Normal file
44
c/src/libchip/network/dwmac-desc-com.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief DWMAC 10/100/1000 Common Descriptor Handling.
|
||||
*
|
||||
* DWMAC 10/100/1000 on-chip Ethernet controllers.
|
||||
* Functions and data which are common to normal and enhanced DMA descriptors.
|
||||
* This header file is NOT part of the driver API.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef DWMAC_DESC_COM_H_
|
||||
#define DWMAC_DESC_COM_H_
|
||||
|
||||
#include "dwmac-common.h"
|
||||
#include <sys/queue.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define DWMAC_DESC_COM_HW_CRC_BYTES 4
|
||||
#define DWMAC_DESC_COM_BUF_SIZE ( ETHER_MAX_LEN + DWMAC_DESC_COM_HW_CRC_BYTES )
|
||||
|
||||
struct mbuf *dwmac_desc_com_new_mbuf( dwmac_common_context *self );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* DWMAC_DESC_COM_H_ */
|
||||
1051
c/src/libchip/network/dwmac-desc-enh.c
Normal file
1051
c/src/libchip/network/dwmac-desc-enh.c
Normal file
File diff suppressed because it is too large
Load Diff
257
c/src/libchip/network/dwmac-desc.h
Normal file
257
c/src/libchip/network/dwmac-desc.h
Normal file
@@ -0,0 +1,257 @@
|
||||
#ifndef DWMAC_DESC_RX_REGS_H
|
||||
#define DWMAC_DESC_RX_REGS_H
|
||||
|
||||
#include <bsp/utility.h>
|
||||
|
||||
typedef struct {
|
||||
uint32_t des0;
|
||||
#define DWMAC_DESC_RX_DES0_OWN_BIT BSP_BIT32(31)
|
||||
#define DWMAC_DESC_RX_DES0_DEST_ADDR_FILTER_FAIL BSP_BIT32(30)
|
||||
#define DWMAC_DESC_RX_DES0_FRAME_LENGTH(val) BSP_FLD32(val, 16, 29)
|
||||
#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_GET(reg) BSP_FLD32GET(reg, 16, 29)
|
||||
#define DWMAC_DESC_RX_DES0_FRAME_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 29)
|
||||
#define DWMAC_DESC_RX_DES0_ERROR_SUMMARY BSP_BIT32(15)
|
||||
#define DWMAC_DESC_RX_DES0_DESCRIPTOR_ERROR BSP_BIT32(14)
|
||||
#define DWMAC_DESC_RX_DES0_SRC_ADDR_FILTER_FAIL BSP_BIT32(13)
|
||||
#define DWMAC_DESC_RX_DES0_LENGTH_ERROR BSP_BIT32(12)
|
||||
#define DWMAC_DESC_RX_DES0_OVERFLOW_ERROR BSP_BIT32(11)
|
||||
#define DWMAC_DESC_RX_DES0_VLAN_TAG BSP_BIT32(10)
|
||||
#define DWMAC_DESC_RX_DES0_FIRST_DESCRIPTOR BSP_BIT32(9)
|
||||
#define DWMAC_DESC_RX_DES0_LAST_DESCRIPTOR BSP_BIT32(8)
|
||||
#define DWMAC_DESC_RX_DES0_CHECKSUM_ERROR BSP_BIT32(7)
|
||||
#define DWMAC_DESC_RX_DES0_LATE_COLLISION BSP_BIT32(6)
|
||||
#define DWMAC_DESC_RX_DES0_FRAME_TYPE BSP_BIT32(5)
|
||||
#define DWMAC_DESC_RX_DES0_RECEIVE_WATCHDOG_TIMEOUT BSP_BIT32(4)
|
||||
#define DWMAC_DESC_RX_DES0_RECEIVE_ERROR BSP_BIT32(3)
|
||||
#define DWMAC_DESC_RX_DES0_DRIBBLE_BIT_ERROR BSP_BIT32(2)
|
||||
#define DWMAC_DESC_RX_DES0_CRC_ERROR BSP_BIT32(1)
|
||||
#define DWMAC_DESC_RX_DES0_RX_MAC_ADDR_OR_PAYLOAD_CHECKSUM_ERROR BSP_BIT32(0)
|
||||
uint32_t des1;
|
||||
#define DWMAC_DESC_RX_DES1_DISABLE_IRQ_ON_COMPLETION BSP_BIT32(31)
|
||||
#define DWMAC_DESC_RX_DES1_RECEIVE_END_OF_RING BSP_BIT32(25)
|
||||
#define DWMAC_DESC_RX_DES1_SECOND_ADDR_CHAINED BSP_BIT32(24)
|
||||
#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE(val) BSP_FLD32(val, 11, 21)
|
||||
#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 11, 21)
|
||||
#define DWMAC_DESC_RX_DES1_RECEIVE_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 11, 21)
|
||||
#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 10)
|
||||
#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 10)
|
||||
#define DWMAC_DESC_RX_DES1_RECIVE_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
|
||||
uint32_t des2;
|
||||
#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES2_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des3;
|
||||
#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_RX_DES3_IEEE_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_rx;
|
||||
|
||||
typedef struct {
|
||||
uint32_t des0;
|
||||
#define DWMAC_DESC_TX_DES0_OWN_BIT BSP_BIT32(31)
|
||||
#define DWMAC_DESC_TX_DES0_TX_TIMESTAMP_STATUS BSP_BIT32(17)
|
||||
#define DWMAC_DESC_TX_DES0_IP_HEADER_ERROR BSP_BIT32(16)
|
||||
#define DWMAC_DESC_TX_DES0_ERROR_SUMMARY BSP_BIT32(15)
|
||||
#define DWMAC_DESC_TX_DES0_JABBER_TIMEOUT BSP_BIT32(14)
|
||||
#define DWMAC_DESC_TX_DES0_FRAME_FLUSHED BSP_BIT32(13)
|
||||
#define DWMAC_DESC_TX_DES0_PAYLOAD_CHECKSUM_ERROR BSP_BIT32(12)
|
||||
#define DWMAC_DESC_TX_DES0_LOSS_OF_CARRIER BSP_BIT32(11)
|
||||
#define DWMAC_DESC_TX_DES0_NO_CARRIER BSP_BIT32(10)
|
||||
#define DWMAC_DESC_TX_DES0_EXCESSIVE_COLLISION BSP_BIT32(8)
|
||||
#define DWMAC_DESC_TX_DES0_VLAN_FRAME BSP_BIT32(7)
|
||||
#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT(val) BSP_FLD32(val, 3, 6)
|
||||
#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_GET(reg) BSP_FLD32GET(reg, 3, 6)
|
||||
#define DWMAC_DESC_TX_DES0_COLLISION_TIMEOUT_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6)
|
||||
#define DWMAC_DESC_TX_DES0_EXCESSIVE_DEFERAL BSP_BIT32(2)
|
||||
#define DWMAC_DESC_TX_DES0_UNDERFLOW_ERROR BSP_BIT32(1)
|
||||
#define DWMAC_DESC_TX_DES0_DEFERED_BIT BSP_BIT32(0)
|
||||
uint32_t des1;
|
||||
#define DWMAC_DESC_TX_DES1_IRQ_ON_COMPLETION BSP_BIT32(31)
|
||||
#define DWMAC_DESC_TX_DES1_LAST_SEGMENT BSP_BIT32(30)
|
||||
#define DWMAC_DESC_TX_DES1_FIRST_SEGMENT BSP_BIT32(29)
|
||||
#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL(val) BSP_FLD32(val, 27, 28)
|
||||
#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_GET(reg) BSP_FLD32GET(reg, 27, 28)
|
||||
#define DWMAC_DESC_TX_DES1_CHECKSUM_INSERTION_CONTROL_SET(reg, val) BSP_FLD32SET(reg, val, 27, 28)
|
||||
#define DWMAC_DESC_TX_DES1_DISABLE_CRC BSP_BIT32(26)
|
||||
#define DWMAC_DESC_TX_DES1_TRANSMIT_END_OF_RING BSP_BIT32(25)
|
||||
#define DWMAC_DESC_TX_DES1_SECOND_ADDRESS_CHAINED BSP_BIT32(24)
|
||||
#define DWMAC_DESC_TX_DES1_DISABLE_PADDING BSP_BIT32(23)
|
||||
#define DWMAC_DESC_TX_DES1_TRANSMIT_TIMESTAMP_ENABLE BSP_BIT32(22)
|
||||
#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE(val) BSP_FLD32(val, 11, 21)
|
||||
#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 11, 21)
|
||||
#define DWMAC_DESC_TX_DES1_TRANMIT_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 11, 21)
|
||||
#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 10)
|
||||
#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 10)
|
||||
#define DWMAC_DESC_TX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
|
||||
uint32_t des2;
|
||||
#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES2_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des3;
|
||||
#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_TX_DES3_IEEE_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_tx;
|
||||
|
||||
typedef struct {
|
||||
uint32_t des0;
|
||||
#define DWMAC_DESC_ERX_DES0_OWN_BIT BSP_BIT32(31)
|
||||
#define DWMAC_DESC_ERX_DES0_DEST_ADDR_FILTER_FAIL BSP_BIT32(30)
|
||||
#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH(val) BSP_FLD32(val, 16, 29)
|
||||
#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_GET(reg) BSP_FLD32GET(reg, 16, 29)
|
||||
#define DWMAC_DESC_ERX_DES0_FRAME_LENGTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 29)
|
||||
#define DWMAC_DESC_ERX_DES0_ERROR_SUMMARY BSP_BIT32(15)
|
||||
#define DWMAC_DESC_ERX_DES0_DESCRIPTOR_ERROR BSP_BIT32(14)
|
||||
#define DWMAC_DESC_ERX_DES0_SRC_ADDR_FILTER_FAIL BSP_BIT32(13)
|
||||
#define DWMAC_DESC_ERX_DES0_LENGTH_ERROR BSP_BIT32(12)
|
||||
#define DWMAC_DESC_ERX_DES0_OVERFLOW_ERROR BSP_BIT32(11)
|
||||
#define DWMAC_DESC_ERX_DES0_VLAN_TAG BSP_BIT32(10)
|
||||
#define DWMAC_DESC_ERX_DES0_FIRST_DESCRIPTOR BSP_BIT32(9)
|
||||
#define DWMAC_DESC_ERX_DES0_LAST_DESCRIPTOR BSP_BIT32(8)
|
||||
#define DWMAC_DESC_ERX_DES0_TIMESTAMP_AVAIL_OR_CHECKSUM_ERROR_OR_GIANT_FRAME BSP_BIT32(7)
|
||||
#define DWMAC_DESC_ERX_DES0_LATE_COLLISION BSP_BIT32(6)
|
||||
#define DWMAC_DESC_ERX_DES0_FREAME_TYPE BSP_BIT32(5)
|
||||
#define DWMAC_DESC_ERX_DES0_RECEIVE_WATCHDOG_TIMEOUT BSP_BIT32(4)
|
||||
#define DWMAC_DESC_ERX_DES0_RECEIVE_ERROR BSP_BIT32(3)
|
||||
#define DWMAC_DESC_ERX_DES0_DRIBBLE_BIT_ERROR BSP_BIT32(2)
|
||||
#define DWMAC_DESC_ERX_DES0_CRC_ERROR BSP_BIT32(1)
|
||||
#define DWMAC_DESC_ERX_DES0_EXT_STATUS_AVAIL_OR_RX_MAC_ADDR_STATUS BSP_BIT32(0)
|
||||
uint32_t des1;
|
||||
#define DWMAC_DESC_ERX_DES1_DISABLE_IRQ_ON_COMPLETION BSP_BIT32(31)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE(val) BSP_FLD32(val, 16, 28)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_GET(reg) BSP_FLD32GET(reg, 16, 28)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 28)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_END_OF_RING BSP_BIT32(15)
|
||||
#define DWMAC_DESC_ERX_DES1_SECOND_ADDR_CHAINED BSP_BIT32(14)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE(val) BSP_FLD32(val, 0, 12)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 12)
|
||||
#define DWMAC_DESC_ERX_DES1_RECEIVE_BUFF_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 12)
|
||||
uint32_t des2;
|
||||
#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_ERX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des3;
|
||||
#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_ERX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_erx;
|
||||
|
||||
typedef struct {
|
||||
uint32_t des0;
|
||||
#define DWMAC_DESC_ETX_DES0_OWN_BIT BSP_BIT32(31)
|
||||
#define DWMAC_DESC_ETX_DES0_IRQ_ON_COMPLETION BSP_BIT32(30)
|
||||
#define DWMAC_DESC_ETX_DES0_LAST_SEGMENT BSP_BIT32(29)
|
||||
#define DWMAC_DESC_ETX_DES0_FIRST_SEGMENT BSP_BIT32(28)
|
||||
#define DWMAC_DESC_ETX_DES0_DISABLE_CRC BSP_BIT32(27)
|
||||
#define DWMAC_DESC_ETX_DES0_DISABLE_PAD BSP_BIT32(26)
|
||||
#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_ENABLE BSP_BIT32(25)
|
||||
#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL(val) BSP_FLD32(val, 22, 23)
|
||||
#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_GET(reg) BSP_FLD32GET(reg, 22, 23)
|
||||
#define DWMAC_DESC_ETX_DES0_CHECKSUM_INSERTION_CONTROL_SET(reg, val) BSP_FLD32SET(reg, val, 22, 23)
|
||||
#define DWMAC_DESC_ETX_DES0_TRANSMIT_END_OF_RING BSP_BIT32(21)
|
||||
#define DWMAC_DESC_ETX_DES0_SECOND_ADDR_CHAINED BSP_BIT32(20)
|
||||
#define DWMAC_DESC_ETX_DES0_TRANSMIT_TIMESTAMP_STATUS BSP_BIT32(17)
|
||||
#define DWMAC_DESC_ETX_DES0_IP_HEADER_ERROR BSP_BIT32(16)
|
||||
#define DWMAC_DESC_ETX_DES0_ERROR_SUMMARY BSP_BIT32(15)
|
||||
#define DWMAC_DESC_ETX_DES0_JABBER_TIMEOUT BSP_BIT32(14)
|
||||
#define DWMAC_DESC_ETX_DES0_FRAME_FLUSHED BSP_BIT32(13)
|
||||
#define DWMAC_DESC_ETX_DES0_IP_PAYLOAD_ERROR BSP_BIT32(12)
|
||||
#define DWMAC_DESC_ETX_DES0_LOSS_OF_CARRIER BSP_BIT32(11)
|
||||
#define DWMAC_DESC_ETX_DES0_NO_CARRIER BSP_BIT32(10)
|
||||
#define DWMAC_DESC_ETX_DES0_EXCESSIVE_COLLISION BSP_BIT32(8)
|
||||
#define DWMAC_DESC_ETX_DES0_VLAN_FRAME BSP_BIT32(7)
|
||||
#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT(val) BSP_FLD32(val, 3, 6)
|
||||
#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_GET(reg) BSP_FLD32GET(reg, 3, 6)
|
||||
#define DWMAC_DESC_ETX_DES0_COLLISION_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6)
|
||||
#define DWMAC_DESC_ETX_DES0_EXCESSIVE_DEFERAL BSP_BIT32(2)
|
||||
#define DWMAC_DESC_ETX_DES0_UNDERFLOW_ERROR BSP_BIT32(1)
|
||||
#define DWMAC_DESC_ETX_DES0_DEFERRED_BIT BSP_BIT32(0)
|
||||
uint32_t des1;
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE(val) BSP_FLD32(val, 16, 28)
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_GET(reg) BSP_FLD32GET(reg, 16, 28)
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_2_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 28)
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE(val) BSP_FLD32(val, 0, 12)
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_GET(reg) BSP_FLD32GET(reg, 0, 12)
|
||||
#define DWMAC_DESC_ETX_DES1_TRANSMIT_BUFFER_1_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 12)
|
||||
uint32_t des2;
|
||||
#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_ETX_DES2_BUFF_1_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des3;
|
||||
#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_ETX_DES3_BUFF_2_ADDR_PTR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_etx;
|
||||
|
||||
typedef union {
|
||||
dwmac_desc_rx rx;
|
||||
dwmac_desc_tx tx;
|
||||
dwmac_desc_erx erx;
|
||||
dwmac_desc_etx etx;
|
||||
} dwmac_desc;
|
||||
|
||||
typedef struct {
|
||||
dwmac_desc_erx des0_3;
|
||||
uint32_t des4;
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED(val) BSP_FLD32(val, 26, 27)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_GET(reg) BSP_FLD32GET(reg, 26, 27)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_AND_LAYER4_FILTER_MATCHED_SET(reg, val) BSP_FLD32SET(reg, val, 26, 27)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_LAYER4_FILTER_MATCH BSP_BIT32(25)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_LAYER3_FILTER_MATCH BSP_BIT32(24)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_TIMESTAMP_DROPPED BSP_BIT32(14)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_PTP_VERSION BSP_BIT32(13)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_PTP_FRAME_TYPE BSP_BIT32(12)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE(val) BSP_FLD32(val, 8, 11)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_MESSAGE_TYPE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IPV6_PACKET_RECEIVED BSP_BIT32(7)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IPV4_PACKET_RECEIVED BSP_BIT32(6)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_CHECKSUM_BYPASSED BSP_BIT32(5)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_ERROR BSP_BIT32(4)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_HEADER_ERROR BSP_BIT32(3)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE(val) BSP_FLD32(val, 0, 2)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_GET(reg) BSP_FLD32GET(reg, 0, 2)
|
||||
#define DWMAC_DESC_EXT_ERX_DES4_IP_PAYLOAD_TYPE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
|
||||
uint32_t des5;
|
||||
uint32_t des6;
|
||||
#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ERX_DES6_RECEIVE_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des7;
|
||||
#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ERX_DES7_RECEIVE_FRAME_TIMESTAMP_HIGH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_ext_erx;
|
||||
|
||||
typedef struct {
|
||||
dwmac_desc_etx des0_3;
|
||||
uint32_t des4;
|
||||
uint32_t des5;
|
||||
uint32_t des6;
|
||||
#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ETX_DES6_TRANSMIT_FRAME_TIMESTAMP_LOW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t des7;
|
||||
#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH(val) BSP_FLD32(val, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DWMAC_DESC_EXT_ETX_DES7_TRANSMIT_FRAME_TIMESTAMP_HIGH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
} dwmac_desc_ext_etx;
|
||||
|
||||
typedef union {
|
||||
dwmac_desc_ext_erx erx;
|
||||
dwmac_desc_ext_etx etx;
|
||||
} dwmac_desc_ext;
|
||||
|
||||
#endif /* DWMAC_DESC_RX_REGS_H */
|
||||
515
c/src/libchip/network/dwmac-regs.h
Normal file
515
c/src/libchip/network/dwmac-regs.h
Normal file
@@ -0,0 +1,515 @@
|
||||
#ifndef MAC_REGS_H
|
||||
#define MAC_REGS_H
|
||||
|
||||
#include <bsp/utility.h>
|
||||
|
||||
typedef struct {
|
||||
uint32_t high;
|
||||
#define MAC_HIGH_ADDRHI(val) BSP_FLD32(val, 0, 15)
|
||||
#define MAC_HIGH_ADDRHI_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define MAC_HIGH_ADDRHI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
#define MAC_HIGH_MBC0 BSP_BIT32(24)
|
||||
#define MAC_HIGH_MBC1 BSP_BIT32(25)
|
||||
#define MAC_HIGH_MBC2 BSP_BIT32(26)
|
||||
#define MAC_HIGH_MBC3 BSP_BIT32(27)
|
||||
#define MAC_HIGH_MBC4 BSP_BIT32(28)
|
||||
#define MAC_HIGH_MBC5 BSP_BIT32(29)
|
||||
#define MAC_HIGH_SA BSP_BIT32(30)
|
||||
#define MAC_HIGH_AE BSP_BIT32(31)
|
||||
uint32_t low;
|
||||
#define MAC_LOW_ADDRLO(val) BSP_FLD32(val, 0, 32)
|
||||
#define MAC_LOW_ADDRLO_GET(reg) BSP_FLD32GET(reg, 0, 32)
|
||||
#define MAC_LOW_ADDRLO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 32)
|
||||
} mac;
|
||||
|
||||
typedef struct {
|
||||
uint32_t mac_configuration;
|
||||
#define MACGRP_MAC_CONFIGURATION_PRELEN(val) BSP_FLD32(val, 0, 1)
|
||||
#define MACGRP_MAC_CONFIGURATION_PRELEN_GET(reg) BSP_FLD32GET(reg, 0, 1)
|
||||
#define MACGRP_MAC_CONFIGURATION_PRELEN_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
|
||||
#define MACGRP_MAC_CONFIGURATION_RE BSP_BIT32(2)
|
||||
#define MACGRP_MAC_CONFIGURATION_TE BSP_BIT32(3)
|
||||
#define MACGRP_MAC_CONFIGURATION_DC BSP_BIT32(4)
|
||||
#define MACGRP_MAC_CONFIGURATION_BL(val) BSP_FLD32(val, 5, 6)
|
||||
#define MACGRP_MAC_CONFIGURATION_BL_GET(reg) BSP_FLD32GET(reg, 5, 6)
|
||||
#define MACGRP_MAC_CONFIGURATION_BL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
|
||||
#define MACGRP_MAC_CONFIGURATION_ACS BSP_BIT32(7)
|
||||
#define MACGRP_MAC_CONFIGURATION_LUD BSP_BIT32(8)
|
||||
#define MACGRP_MAC_CONFIGURATION_DR BSP_BIT32(9)
|
||||
#define MACGRP_MAC_CONFIGURATION_IPC BSP_BIT32(10)
|
||||
#define MACGRP_MAC_CONFIGURATION_DM BSP_BIT32(11)
|
||||
#define MACGRP_MAC_CONFIGURATION_LM BSP_BIT32(12)
|
||||
#define MACGRP_MAC_CONFIGURATION_DO BSP_BIT32(13)
|
||||
#define MACGRP_MAC_CONFIGURATION_FES BSP_BIT32(14)
|
||||
#define MACGRP_MAC_CONFIGURATION_PS BSP_BIT32(15)
|
||||
#define MACGRP_MAC_CONFIGURATION_DCRS BSP_BIT32(16)
|
||||
#define MACGRP_MAC_CONFIGURATION_IFG(val) BSP_FLD32(val, 17, 19)
|
||||
#define MACGRP_MAC_CONFIGURATION_IFG_GET(reg) BSP_FLD32GET(reg, 17, 19)
|
||||
#define MACGRP_MAC_CONFIGURATION_IFG_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19)
|
||||
#define MACGRP_MAC_CONFIGURATION_JE BSP_BIT32(20)
|
||||
#define MACGRP_MAC_CONFIGURATION_BE BSP_BIT32(21)
|
||||
#define MACGRP_MAC_CONFIGURATION_JD BSP_BIT32(22)
|
||||
#define MACGRP_MAC_CONFIGURATION_WD BSP_BIT32(23)
|
||||
#define MACGRP_MAC_CONFIGURATION_TC BSP_BIT32(24)
|
||||
#define MACGRP_MAC_CONFIGURATION_CST BSP_BIT32(25)
|
||||
#define MACGRP_MAC_CONFIGURATION_TWOKPE BSP_BIT32(27)
|
||||
uint32_t mac_frame_filter;
|
||||
#define MACGRP_MAC_FRAME_FILTER_PR BSP_BIT32(0)
|
||||
#define MACGRP_MAC_FRAME_FILTER_HUC BSP_BIT32(1)
|
||||
#define MACGRP_MAC_FRAME_FILTER_HMC BSP_BIT32(2)
|
||||
#define MACGRP_MAC_FRAME_FILTER_DAIF BSP_BIT32(3)
|
||||
#define MACGRP_MAC_FRAME_FILTER_PM BSP_BIT32(4)
|
||||
#define MACGRP_MAC_FRAME_FILTER_DBF BSP_BIT32(5)
|
||||
#define MACGRP_MAC_FRAME_FILTER_PCF(val) BSP_FLD32(val, 6, 7)
|
||||
#define MACGRP_MAC_FRAME_FILTER_PCF_GET(reg) BSP_FLD32GET(reg, 6, 7)
|
||||
#define MACGRP_MAC_FRAME_FILTER_PCF_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
|
||||
#define MACGRP_MAC_FRAME_FILTER_SAIF BSP_BIT32(8)
|
||||
#define MACGRP_MAC_FRAME_FILTER_SAF BSP_BIT32(9)
|
||||
#define MACGRP_MAC_FRAME_FILTER_HPF BSP_BIT32(10)
|
||||
#define MACGRP_MAC_FRAME_FILTER_VTFE BSP_BIT32(16)
|
||||
#define MACGRP_MAC_FRAME_FILTER_IPFE BSP_BIT32(20)
|
||||
#define MACGRP_MAC_FRAME_FILTER_DNTU BSP_BIT32(21)
|
||||
#define MACGRP_MAC_FRAME_FILTER_RA BSP_BIT32(31)
|
||||
uint32_t reserved_08[2];
|
||||
uint32_t gmii_address;
|
||||
#define MACGRP_GMII_ADDRESS_GMII_BUSY BSP_BIT32(0)
|
||||
#define MACGRP_GMII_ADDRESS_GMII_WRITE BSP_BIT32(1)
|
||||
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE(val) BSP_FLD32(val, 2, 5)
|
||||
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_GET(reg) BSP_FLD32GET(reg, 2, 5)
|
||||
#define MACGRP_GMII_ADDRESS_CSR_CLOCK_RANGE_SET(reg, val) BSP_FLD32SET(reg, val, 2, 5)
|
||||
#define MACGRP_GMII_ADDRESS_GMII_REGISTER(val) BSP_FLD32(val, 6, 10)
|
||||
#define MACGRP_GMII_ADDRESS_GMII_REGISTER_GET(reg) BSP_FLD32GET(reg, 6, 10)
|
||||
#define MACGRP_GMII_ADDRESS_GMII_REGISTER_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
|
||||
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS(val) BSP_FLD32(val, 11, 15)
|
||||
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_GET(reg) BSP_FLD32GET(reg, 11, 15)
|
||||
#define MACGRP_GMII_ADDRESS_PHYSICAL_LAYER_ADDRESS_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
|
||||
uint32_t gmii_data;
|
||||
#define MACGRP_GMII_DATA_GMII_DATA(val) BSP_FLD32(val, 0, 15)
|
||||
#define MACGRP_GMII_DATA_GMII_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define MACGRP_GMII_DATA_GMII_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
uint32_t reserved_18[9];
|
||||
uint32_t interrupt_mask;
|
||||
#define MACGRP_INTERRUPT_MASK_RGSMIIIM BSP_BIT32(0)
|
||||
#define MACGRP_INTERRUPT_MASK_PCSLCHGIM BSP_BIT32(1)
|
||||
#define MACGRP_INTERRUPT_MASK_PCSANCIM BSP_BIT32(2)
|
||||
#define MACGRP_INTERRUPT_MASK_TSIM BSP_BIT32(9)
|
||||
#define MACGRP_INTERRUPT_MASK_LPIIM BSP_BIT32(10)
|
||||
mac mac_addr0_15[16];
|
||||
uint32_t reserved_c0[16];
|
||||
uint32_t mmc_control;
|
||||
#define MACGRP_MMC_CONTROL_CNTRST BSP_BIT32(0)
|
||||
#define MACGRP_MMC_CONTROL_CNTSTOPRO BSP_BIT32(1)
|
||||
#define MACGRP_MMC_CONTROL_RSTONRD BSP_BIT32(2)
|
||||
#define MACGRP_MMC_CONTROL_CNTFREEZ BSP_BIT32(3)
|
||||
#define MACGRP_MMC_CONTROL_CNTPRST BSP_BIT32(4)
|
||||
#define MACGRP_MMC_CONTROL_CNTPRSTLVL BSP_BIT32(5)
|
||||
#define MACGRP_MMC_CONTROL_UCDBC BSP_BIT32(8)
|
||||
uint32_t mmc_receive_interrupt;
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBFRMIS BSP_BIT32(0)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGBOCTIS BSP_BIT32(1)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXGOCTIS BSP_BIT32(2)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXBCGFIS BSP_BIT32(3)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXMCGFIS BSP_BIT32(4)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCRCERFIS BSP_BIT32(5)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXALGNERFIS BSP_BIT32(6)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRUNTFIS BSP_BIT32(7)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXJABERFIS BSP_BIT32(8)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUSIZEGFIS BSP_BIT32(9)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXOSIZEGFIS BSP_BIT32(10)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX64OCTGBFIS BSP_BIT32(11)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX65T127OCTGBFIS BSP_BIT32(12)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX128T255OCTGBFIS BSP_BIT32(13)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX256T511OCTGBFIS BSP_BIT32(14)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX512T1023OCTGBFIS BSP_BIT32(15)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RX1024TMAXOCTGBFIS BSP_BIT32(16)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXUCGFIS BSP_BIT32(17)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXLENERFIS BSP_BIT32(18)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXORANGEFIS BSP_BIT32(19)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXPAUSFIS BSP_BIT32(20)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXFOVFIS BSP_BIT32(21)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXVLANGBFIS BSP_BIT32(22)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXWDOGFIS BSP_BIT32(23)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXRCVERRFIS BSP_BIT32(24)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_RXCTRLFIS BSP_BIT32(25)
|
||||
uint32_t mmc_transmit_interrupt;
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBOCTIS BSP_BIT32(0)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGBFRMIS BSP_BIT32(1)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGFIS BSP_BIT32(2)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGFIS BSP_BIT32(3)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX64OCTGBFIS BSP_BIT32(4)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX65T127OCTGBFIS BSP_BIT32(5)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX128T255OCTGBFIS BSP_BIT32(6)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX256T511OCTGBFIS BSP_BIT32(7)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX512T1023OCTGBFIS BSP_BIT32(8)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TX1024TMAXOCTGBFIS BSP_BIT32(9)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUCGBFIS BSP_BIT32(10)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCGBFIS BSP_BIT32(11)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXBCGBFIS BSP_BIT32(12)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXUFLOWERFIS BSP_BIT32(13)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXSCOLGFIS BSP_BIT32(14)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXMCOLGFIS BSP_BIT32(15)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXDEFFIS BSP_BIT32(16)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXLATCOLFIS BSP_BIT32(17)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXCOLFIS BSP_BIT32(18)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXCARERFIS BSP_BIT32(19)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGOCTIS BSP_BIT32(20)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXGFRMIS BSP_BIT32(21)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXEXDEFFIS BSP_BIT32(22)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXPAUSFIS BSP_BIT32(23)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXVLANGFIS BSP_BIT32(24)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_TXOSIZEGFIS BSP_BIT32(25)
|
||||
uint32_t mmc_receive_interrupt_mask;
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBFRMIM BSP_BIT32(0)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGBOCTIM BSP_BIT32(1)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXGOCTIM BSP_BIT32(2)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXBCGFIM BSP_BIT32(3)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXMCGFIM BSP_BIT32(4)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCRCERFIM BSP_BIT32(5)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXALGNERFIM BSP_BIT32(6)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRUNTFIM BSP_BIT32(7)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXJABERFIM BSP_BIT32(8)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUSIZEGFIM BSP_BIT32(9)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXOSIZEGFIM BSP_BIT32(10)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX64OCTGBFIM BSP_BIT32(11)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX65T127OCTGBFIM BSP_BIT32(12)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX128T255OCTGBFIM BSP_BIT32(13)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX256T511OCTGBFIM BSP_BIT32(14)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX512T1023OCTGBFIM BSP_BIT32(15)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RX1024TMAXOCTGBFIM BSP_BIT32(16)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXUCGFIM BSP_BIT32(17)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXLENERFIM BSP_BIT32(18)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXORANGEFIM BSP_BIT32(19)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXPAUSFIM BSP_BIT32(20)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXFOVFIM BSP_BIT32(21)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXVLANGBFIM BSP_BIT32(22)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXWDOGFIM BSP_BIT32(23)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXRCVERRFIM BSP_BIT32(24)
|
||||
#define MACGRP_MMC_RECEIVE_INTERRUPT_MASK_RXCTRLFIM BSP_BIT32(25)
|
||||
uint32_t mmc_transmit_interrupt_mask;
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBOCTIM BSP_BIT32(0)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGBFRMIM BSP_BIT32(1)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGFIM BSP_BIT32(2)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGFIM BSP_BIT32(3)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX64OCTGBFIM BSP_BIT32(4)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX65T127OCTGBFIM BSP_BIT32(5)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX128T255OCTGBFIM BSP_BIT32(6)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX256T511OCTGBFIM BSP_BIT32(7)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX512T1023OCTGBFIM BSP_BIT32(8)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TX1024TMAXOCTGBFIM BSP_BIT32(9)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUCGBFIM BSP_BIT32(10)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCGBFIM BSP_BIT32(11)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXBCGBFIM BSP_BIT32(12)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXUFLOWERFIM BSP_BIT32(13)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXSCOLGFIM BSP_BIT32(14)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXMCOLGFIM BSP_BIT32(15)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXDEFFIM BSP_BIT32(16)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXLATCOLFIM BSP_BIT32(17)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXCOLFIM BSP_BIT32(18)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXCARERFIM BSP_BIT32(19)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGOCTIM BSP_BIT32(20)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXGFRMIM BSP_BIT32(21)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXEXDEFFIM BSP_BIT32(22)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXPAUSFIM BSP_BIT32(23)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXVLANGFIM BSP_BIT32(24)
|
||||
#define MACGRP_MMC_TRANSMIT_INTERRUPT_MASK_TXOSIZEGFIM BSP_BIT32(25)
|
||||
uint32_t txoctetcount_gb;
|
||||
uint32_t txframecount_gb;
|
||||
uint32_t txbroadcastframes_g;
|
||||
uint32_t txmulticastframes_g;
|
||||
uint32_t tx64octets_gb;
|
||||
uint32_t tx65to127octets_gb;
|
||||
uint32_t tx128to255octets_gb;
|
||||
uint32_t tx256to511octets_gb;
|
||||
uint32_t tx512to1023octets_gb;
|
||||
uint32_t tx1024tomaxoctets_gb;
|
||||
uint32_t txunicastframes_gb;
|
||||
uint32_t txmulticastframes_gb;
|
||||
uint32_t txbroadcastframes_gb;
|
||||
uint32_t txunderflowerror;
|
||||
uint32_t txsinglecol_g;
|
||||
uint32_t txmulticol_g;
|
||||
uint32_t txdeferred;
|
||||
uint32_t txlatecol;
|
||||
uint32_t txexesscol;
|
||||
uint32_t txcarriererr;
|
||||
uint32_t txoctetcnt;
|
||||
uint32_t txframecount_g;
|
||||
uint32_t txexcessdef;
|
||||
uint32_t txpauseframes;
|
||||
uint32_t txvlanframes_g;
|
||||
uint32_t txoversize_g;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t rxframecount_gb;
|
||||
uint32_t rxoctetcount_gb;
|
||||
uint32_t rxoctetcount_g;
|
||||
uint32_t rxbroadcastframes_g;
|
||||
uint32_t rxmulticastframes_g;
|
||||
uint32_t rxcrcerror;
|
||||
uint32_t rxalignmenterror;
|
||||
uint32_t rxrunterror;
|
||||
uint32_t rxjabbererror;
|
||||
uint32_t rxundersize_g;
|
||||
uint32_t rxoversize_g;
|
||||
uint32_t rx64octets_gb;
|
||||
uint32_t rx65to127octets_gb;
|
||||
uint32_t rx128to255octets_gb;
|
||||
uint32_t rx256to511octets_gb;
|
||||
uint32_t rx512to1023octets_gb;
|
||||
uint32_t rx1024tomaxoctets_gb;
|
||||
uint32_t rxunicastframes_g;
|
||||
uint32_t rxlengtherror;
|
||||
uint32_t rxoutofrangetype;
|
||||
uint32_t rxpauseframes;
|
||||
uint32_t rxfifooverflow;
|
||||
uint32_t rxvlanframes_gb;
|
||||
uint32_t rxwatchdogerror;
|
||||
uint32_t rxrcverror;
|
||||
uint32_t rxctrlframes_g;
|
||||
uint32_t reserved_1e8[6];
|
||||
uint32_t mmc_ipc_receive_interrupt_mask;
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GFIM BSP_BIT32(0)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HERFIM BSP_BIT32(1)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYFIM BSP_BIT32(2)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGFIM BSP_BIT32(3)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLFIM BSP_BIT32(4)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GFIM BSP_BIT32(5)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HERFIM BSP_BIT32(6)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYFIM BSP_BIT32(7)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGFIM BSP_BIT32(8)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPERFIM BSP_BIT32(9)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGFIM BSP_BIT32(10)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPERFIM BSP_BIT32(11)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGFIM BSP_BIT32(12)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPERFIM BSP_BIT32(13)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4GOIM BSP_BIT32(16)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4HEROIM BSP_BIT32(17)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4NOPAYOIM BSP_BIT32(18)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4FRAGOIM BSP_BIT32(19)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV4UDSBLOIM BSP_BIT32(20)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6GOIM BSP_BIT32(21)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6HEROIM BSP_BIT32(22)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXIPV6NOPAYOIM BSP_BIT32(23)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPGOIM BSP_BIT32(24)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXUDPEROIM BSP_BIT32(25)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPGOIM BSP_BIT32(26)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXTCPEROIM BSP_BIT32(27)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPGOIM BSP_BIT32(28)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_MASK_RXICMPEROIM BSP_BIT32(29)
|
||||
uint32_t reserved_204;
|
||||
uint32_t mmc_ipc_receive_interrupt;
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GFIS BSP_BIT32(0)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HERFIS BSP_BIT32(1)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYFIS BSP_BIT32(2)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGFIS BSP_BIT32(3)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLFIS BSP_BIT32(4)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GFIS BSP_BIT32(5)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HERFIS BSP_BIT32(6)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYFIS BSP_BIT32(7)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGFIS BSP_BIT32(8)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPERFIS BSP_BIT32(9)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGFIS BSP_BIT32(10)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPERFIS BSP_BIT32(11)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGFIS BSP_BIT32(12)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPERFIS BSP_BIT32(13)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4GOIS BSP_BIT32(16)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4HEROIS BSP_BIT32(17)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4NOPAYOIS BSP_BIT32(18)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4FRAGOIS BSP_BIT32(19)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV4UDSBLOIS BSP_BIT32(20)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6GOIS BSP_BIT32(21)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6HEROIS BSP_BIT32(22)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXIPV6NOPAYOIS BSP_BIT32(23)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPGOIS BSP_BIT32(24)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXUDPEROIS BSP_BIT32(25)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPGOIS BSP_BIT32(26)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXTCPEROIS BSP_BIT32(27)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPGOIS BSP_BIT32(28)
|
||||
#define MACGRP_MMC_IPC_RECEIVE_INTERRUPT_RXICMPEROIS BSP_BIT32(29)
|
||||
uint32_t reserved_20c;
|
||||
uint32_t rxipv4_gd_frms;
|
||||
uint32_t rxipv4_hdrerr_frms;
|
||||
uint32_t rxipv4_nopay_frms;
|
||||
uint32_t rxipv4_frag_frms;
|
||||
uint32_t rxipv4_udsbl_frms;
|
||||
uint32_t rxipv6_gd_frms;
|
||||
uint32_t rxipv6_hdrerr_frms;
|
||||
uint32_t rxipv6_nopay_frms;
|
||||
uint32_t rxudp_gd_frms;
|
||||
uint32_t rxudp_err_frms;
|
||||
uint32_t rxtcp_gd_frms;
|
||||
uint32_t rxtcp_err_frms;
|
||||
uint32_t rxicmp_gd_frms;
|
||||
uint32_t rxicmp_err_frms;
|
||||
uint32_t reserved_248[2];
|
||||
uint32_t rxipv4_gd_octets;
|
||||
uint32_t rxipv4_hdrerr_octets;
|
||||
uint32_t rxipv4_nopay_octets;
|
||||
uint32_t rxipv4_frag_octets;
|
||||
uint32_t rxipv4_udsbl_octets;
|
||||
uint32_t rxipv6_gd_octets;
|
||||
uint32_t rxipv6_hdrerr_octets;
|
||||
uint32_t rxipv6_nopay_octets;
|
||||
uint32_t rxudp_gd_octets;
|
||||
uint32_t rxudp_err_octets;
|
||||
uint32_t rxtcp_gd_octets;
|
||||
uint32_t rxtcperroctets;
|
||||
uint32_t rxicmp_gd_octets;
|
||||
uint32_t rxicmp_err_octets;
|
||||
uint32_t reserved_288[158];
|
||||
uint32_t hash_table_reg[8];
|
||||
uint32_t reserved_520[184];
|
||||
mac mac_addr16_127[112];
|
||||
} macgrp;
|
||||
|
||||
typedef struct {
|
||||
uint32_t bus_mode;
|
||||
#define DMAGRP_BUS_MODE_SWR BSP_BIT32(0)
|
||||
#define DMAGRP_BUS_MODE_DSL(val) BSP_FLD32(val, 2, 6)
|
||||
#define DMAGRP_BUS_MODE_DSL_GET(reg) BSP_FLD32GET(reg, 2, 6)
|
||||
#define DMAGRP_BUS_MODE_DSL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 6)
|
||||
#define DMAGRP_BUS_MODE_ATDS BSP_BIT32(7)
|
||||
#define DMAGRP_BUS_MODE_PBL(val) BSP_FLD32(val, 8, 13)
|
||||
#define DMAGRP_BUS_MODE_PBL_GET(reg) BSP_FLD32GET(reg, 8, 13)
|
||||
#define DMAGRP_BUS_MODE_PBL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 13)
|
||||
#define DMAGRP_BUS_MODE_FB BSP_BIT32(16)
|
||||
#define DMAGRP_BUS_MODE_RPBL(val) BSP_FLD32(val, 17, 22)
|
||||
#define DMAGRP_BUS_MODE_RPBL_GET(reg) BSP_FLD32GET(reg, 17, 22)
|
||||
#define DMAGRP_BUS_MODE_RPBL_SET(reg, val) BSP_FLD32SET(reg, val, 17, 22)
|
||||
#define DMAGRP_BUS_MODE_USP BSP_BIT32(23)
|
||||
#define DMAGRP_BUS_MODE_EIGHTXPBL BSP_BIT32(24)
|
||||
#define DMAGRP_BUS_MODE_AAL BSP_BIT32(25)
|
||||
#define DMAGRP_BUS_MODE_MB BSP_BIT32(26)
|
||||
uint32_t transmit_poll_demand;
|
||||
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD(val) BSP_FLD32(val, 0, 31)
|
||||
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DMAGRP_TRANSMIT_POLL_DEMAND_TPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t receive_poll_demand;
|
||||
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD(val) BSP_FLD32(val, 0, 31)
|
||||
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define DMAGRP_RECEIVE_POLL_DEMAND_RPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t receive_descr_list_addr;
|
||||
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT(val) BSP_FLD32(val, 2, 31)
|
||||
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31)
|
||||
#define DMAGRP_RECEIVE_DESCR_LIST_ADDR_RDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31)
|
||||
uint32_t transmit_descr_list_addr;
|
||||
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT(val) BSP_FLD32(val, 2, 31)
|
||||
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_GET(reg) BSP_FLD32GET(reg, 2, 31)
|
||||
#define DMAGRP_TRANSMIT_DESCR_LIST_ADDR_TDESLA_32BIT_SET(reg, val) BSP_FLD32SET(reg, val, 2, 31)
|
||||
uint32_t status;
|
||||
#define DMAGRP_STATUS_TI BSP_BIT32(0)
|
||||
#define DMAGRP_STATUS_TPS BSP_BIT32(1)
|
||||
#define DMAGRP_STATUS_TU BSP_BIT32(2)
|
||||
#define DMAGRP_STATUS_TJT BSP_BIT32(3)
|
||||
#define DMAGRP_STATUS_OVF BSP_BIT32(4)
|
||||
#define DMAGRP_STATUS_UNF BSP_BIT32(5)
|
||||
#define DMAGRP_STATUS_RI BSP_BIT32(6)
|
||||
#define DMAGRP_STATUS_RU BSP_BIT32(7)
|
||||
#define DMAGRP_STATUS_RPS BSP_BIT32(8)
|
||||
#define DMAGRP_STATUS_RWT BSP_BIT32(9)
|
||||
#define DMAGRP_STATUS_ETI BSP_BIT32(10)
|
||||
#define DMAGRP_STATUS_FBI BSP_BIT32(13)
|
||||
#define DMAGRP_STATUS_ERI BSP_BIT32(14)
|
||||
#define DMAGRP_STATUS_AIS BSP_BIT32(15)
|
||||
#define DMAGRP_STATUS_NIS BSP_BIT32(16)
|
||||
#define DMAGRP_STATUS_RS(val) BSP_FLD32(val, 17, 19)
|
||||
#define DMAGRP_STATUS_RS_GET(reg) BSP_FLD32GET(reg, 17, 19)
|
||||
#define DMAGRP_STATUS_RS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 19)
|
||||
#define DMAGRP_STATUS_TS(val) BSP_FLD32(val, 20, 22)
|
||||
#define DMAGRP_STATUS_TS_GET(reg) BSP_FLD32GET(reg, 20, 22)
|
||||
#define DMAGRP_STATUS_TS_SET(reg, val) BSP_FLD32SET(reg, val, 20, 22)
|
||||
#define DMAGRP_STATUS_EB(val) BSP_FLD32(val, 23, 25)
|
||||
#define DMAGRP_STATUS_EB_GET(reg) BSP_FLD32GET(reg, 23, 25)
|
||||
#define DMAGRP_STATUS_EB_SET(reg, val) BSP_FLD32SET(reg, val, 23, 25)
|
||||
#define DMAGRP_STATUS_GLI BSP_BIT32(26)
|
||||
#define DMAGRP_STATUS_GMI BSP_BIT32(27)
|
||||
#define DMAGRP_STATUS_TTI BSP_BIT32(29)
|
||||
#define DMAGRP_STATUS_GLPII BSP_BIT32(30)
|
||||
uint32_t operation_mode;
|
||||
#define DMAGRP_OPERATION_MODE_SR BSP_BIT32(1)
|
||||
#define DMAGRP_OPERATION_MODE_OSF BSP_BIT32(2)
|
||||
#define DMAGRP_OPERATION_MODE_RTC(val) BSP_FLD32(val, 3, 4)
|
||||
#define DMAGRP_OPERATION_MODE_RTC_GET(reg) BSP_FLD32GET(reg, 3, 4)
|
||||
#define DMAGRP_OPERATION_MODE_RTC_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
|
||||
#define DMAGRP_OPERATION_MODE_FUF BSP_BIT32(6)
|
||||
#define DMAGRP_OPERATION_MODE_FEF BSP_BIT32(7)
|
||||
#define DMAGRP_OPERATION_MODE_EFC BSP_BIT32(8)
|
||||
#define DMAGRP_OPERATION_MODE_RFA(val) BSP_FLD32(val, 9, 10)
|
||||
#define DMAGRP_OPERATION_MODE_RFA_GET(reg) BSP_FLD32GET(reg, 9, 10)
|
||||
#define DMAGRP_OPERATION_MODE_RFA_SET(reg, val) BSP_FLD32SET(reg, val, 9, 10)
|
||||
#define DMAGRP_OPERATION_MODE_RFD(val) BSP_FLD32(val, 11, 12)
|
||||
#define DMAGRP_OPERATION_MODE_RFD_GET(reg) BSP_FLD32GET(reg, 11, 12)
|
||||
#define DMAGRP_OPERATION_MODE_RFD_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12)
|
||||
#define DMAGRP_OPERATION_MODE_ST BSP_BIT32(13)
|
||||
#define DMAGRP_OPERATION_MODE_TTC(val) BSP_FLD32(val, 14, 16)
|
||||
#define DMAGRP_OPERATION_MODE_TTC_GET(reg) BSP_FLD32GET(reg, 14, 16)
|
||||
#define DMAGRP_OPERATION_MODE_TTC_SET(reg, val) BSP_FLD32SET(reg, val, 14, 16)
|
||||
#define DMAGRP_OPERATION_MODE_FTF BSP_BIT32(20)
|
||||
#define DMAGRP_OPERATION_MODE_TSF BSP_BIT32(21)
|
||||
#define DMAGRP_OPERATION_MODE_DFF BSP_BIT32(24)
|
||||
#define DMAGRP_OPERATION_MODE_RSF BSP_BIT32(25)
|
||||
#define DMAGRP_OPERATION_MODE_DT BSP_BIT32(26)
|
||||
uint32_t interrupt_enable;
|
||||
#define DMAGRP_INTERRUPT_ENABLE_TIE BSP_BIT32(0)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_TSE BSP_BIT32(1)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_TUE BSP_BIT32(2)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_TJE BSP_BIT32(3)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_OVE BSP_BIT32(4)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_UNE BSP_BIT32(5)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_RIE BSP_BIT32(6)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_RUE BSP_BIT32(7)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_RSE BSP_BIT32(8)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_RWE BSP_BIT32(9)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_ETE BSP_BIT32(10)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_FBE BSP_BIT32(13)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_ERE BSP_BIT32(14)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_AIE BSP_BIT32(15)
|
||||
#define DMAGRP_INTERRUPT_ENABLE_NIE BSP_BIT32(16)
|
||||
uint32_t reserved_20[2];
|
||||
uint32_t axi_bus_mode;
|
||||
#define DMAGRP_AXI_BUS_MODE_UNDEFINED BSP_BIT32(0)
|
||||
#define DMAGRP_AXI_BUS_MODE_BLEND4 BSP_BIT32(1)
|
||||
#define DMAGRP_AXI_BUS_MODE_BLEND8 BSP_BIT32(2)
|
||||
#define DMAGRP_AXI_BUS_MODE_BLEND16 BSP_BIT32(3)
|
||||
#define DMAGRP_AXI_BUS_MODE_AXI_AAL BSP_BIT32(12)
|
||||
#define DMAGRP_AXI_BUS_MODE_ONEKBBE BSP_BIT32(13)
|
||||
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT(val) BSP_FLD32(val, 16, 19)
|
||||
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DMAGRP_AXI_BUS_MODE_RD_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT(val) BSP_FLD32(val, 20, 23)
|
||||
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_GET(reg) BSP_FLD32GET(reg, 20, 23)
|
||||
#define DMAGRP_AXI_BUS_MODE_WR_OSR_LMT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23)
|
||||
#define DMAGRP_AXI_BUS_MODE_LPI_XIT_FRM BSP_BIT32(30)
|
||||
#define DMAGRP_AXI_BUS_MODE_EN_LPI BSP_BIT32(31)
|
||||
uint32_t reserved_2c[11];
|
||||
uint32_t hw_feature;
|
||||
#define DMAGRP_HW_FEATURE_MIISEL BSP_BIT32(0)
|
||||
#define DMAGRP_HW_FEATURE_GMIISEL BSP_BIT32(1)
|
||||
#define DMAGRP_HW_FEATURE_HDSEL BSP_BIT32(2)
|
||||
#define DMAGRP_HW_FEATURE_HASHSEL BSP_BIT32(4)
|
||||
#define DMAGRP_HW_FEATURE_ADDMACADRSEL BSP_BIT32(5)
|
||||
#define DMAGRP_HW_FEATURE_PCSSEL BSP_BIT32(6)
|
||||
#define DMAGRP_HW_FEATURE_SMASEL BSP_BIT32(8)
|
||||
#define DMAGRP_HW_FEATURE_RWKSEL BSP_BIT32(9)
|
||||
#define DMAGRP_HW_FEATURE_MGKSEL BSP_BIT32(10)
|
||||
#define DMAGRP_HW_FEATURE_MMCSEL BSP_BIT32(11)
|
||||
#define DMAGRP_HW_FEATURE_TSVER1SEL BSP_BIT32(12)
|
||||
#define DMAGRP_HW_FEATURE_TSVER2SEL BSP_BIT32(13)
|
||||
#define DMAGRP_HW_FEATURE_EEESEL BSP_BIT32(14)
|
||||
#define DMAGRP_HW_FEATURE_AVSEL BSP_BIT32(15)
|
||||
#define DMAGRP_HW_FEATURE_TXOESEL BSP_BIT32(16)
|
||||
#define DMAGRP_HW_FEATURE_RXTYP1COE BSP_BIT32(17)
|
||||
#define DMAGRP_HW_FEATURE_RXTYP2COE BSP_BIT32(18)
|
||||
#define DMAGRP_HW_FEATURE_RXFIFOSIZE BSP_BIT32(19)
|
||||
#define DMAGRP_HW_FEATURE_RXCHCNT(val) BSP_FLD32(val, 20, 21)
|
||||
#define DMAGRP_HW_FEATURE_RXCHCNT_GET(reg) BSP_FLD32GET(reg, 20, 21)
|
||||
#define DMAGRP_HW_FEATURE_RXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21)
|
||||
#define DMAGRP_HW_FEATURE_TXCHCNT(val) BSP_FLD32(val, 22, 23)
|
||||
#define DMAGRP_HW_FEATURE_TXCHCNT_GET(reg) BSP_FLD32GET(reg, 22, 23)
|
||||
#define DMAGRP_HW_FEATURE_TXCHCNT_SET(reg, val) BSP_FLD32SET(reg, val, 22, 23)
|
||||
#define DMAGRP_HW_FEATURE_ENHDESSEL BSP_BIT32(24)
|
||||
#define DMAGRP_HW_FEATURE_ACTPHYIF(val) BSP_FLD32(val, 28, 30)
|
||||
#define DMAGRP_HW_FEATURE_ACTPHYIF_GET(reg) BSP_FLD32GET(reg, 28, 30)
|
||||
#define DMAGRP_HW_FEATURE_ACTPHYIF_SET(reg, val) BSP_FLD32SET(reg, val, 28, 30)
|
||||
} dmagrp;
|
||||
|
||||
#endif /* MAC_REGS_H */
|
||||
2325
c/src/libchip/network/dwmac.c
Normal file
2325
c/src/libchip/network/dwmac.c
Normal file
File diff suppressed because it is too large
Load Diff
878
c/src/libchip/network/dwmac.h
Normal file
878
c/src/libchip/network/dwmac.h
Normal file
@@ -0,0 +1,878 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @brief API header for the DWMAC 10/100/1000 Network Interface Controllers
|
||||
*
|
||||
* DWMAC 10/100/1000 on-chip Ethernet controllers are a Synopsys IP Core.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
|
||||
*
|
||||
* embedded brains GmbH
|
||||
* Dornierstr. 4
|
||||
* 82178 Puchheim
|
||||
* Germany
|
||||
* <rtems@embedded-brains.de>
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.org/license/LICENSE.
|
||||
*/
|
||||
|
||||
#ifndef DWMAC_H_
|
||||
#define DWMAC_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <rtems/rtems_bsdnet.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @brief PHY event.
|
||||
*
|
||||
* Data type to be used for PHY events and event sets.
|
||||
*/
|
||||
typedef uint8_t dwmac_phy_event;
|
||||
|
||||
/** @brief PHY event Jabber. */
|
||||
extern const dwmac_phy_event PHY_EVENT_JABBER;
|
||||
|
||||
/** @brief PHY event Receive Error. */
|
||||
extern const dwmac_phy_event PHY_EVENT_RECEIVE_ERROR;
|
||||
|
||||
/** @brief PHY event Page Receive. */
|
||||
extern const dwmac_phy_event PHY_EVENT_PAGE_RECEIVE;
|
||||
|
||||
/** @brief PHY event Parallel Detect Fault. */
|
||||
extern const dwmac_phy_event PHY_EVENT_PARALLEL_DETECT_FAULT;
|
||||
|
||||
/** @brief PHY event Link Partner Acknowledge. */
|
||||
extern const dwmac_phy_event PHY_EVENT_LINK_PARTNER_ACK;
|
||||
|
||||
/** @brief PHY event Link Down. */
|
||||
extern const dwmac_phy_event PHY_EVENT_LINK_DOWN;
|
||||
|
||||
/** @brief PHY event Remote Fault. */
|
||||
extern const dwmac_phy_event PHY_EVENT_REMOTE_FAULT;
|
||||
|
||||
/** @brief PHY event Link Up. */
|
||||
extern const dwmac_phy_event PHY_EVENT_LINK_UP;
|
||||
|
||||
/** @brief NIC enable
|
||||
*
|
||||
* Enables (e.g. powers up) the network interface card.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_nic_enable)( void *arg );
|
||||
|
||||
/** @brief NIC disable.
|
||||
*
|
||||
* Disables (e.g. powers down) the network interface card.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_nic_disable)( void *arg );
|
||||
|
||||
/** @brief PHY enable.
|
||||
*
|
||||
* Enables (e.g. powers up) the network PHY.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_phy_enable)( void *arg );
|
||||
|
||||
/** @brief PHY disable.
|
||||
*
|
||||
* Disables (e.g. powers down) the network PHY.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_phy_disable)( void *arg );
|
||||
|
||||
/** @brief PHY event enable.
|
||||
*
|
||||
* Enables generation of events for an event set.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @param[in] event_set Set of events. For these events shall get generated
|
||||
* upon PHY status change.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_phy_event_enable)(
|
||||
void *arg,
|
||||
const dwmac_phy_event event_set );
|
||||
|
||||
/** @brief Clear phy event status.
|
||||
*
|
||||
* Clears all PHY event statuses.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_phy_event_status_clear)( void *arg );
|
||||
|
||||
/**
|
||||
* @brief Get the PHY event status.
|
||||
*
|
||||
* Reports status on PHY events (e.g. PHY interrupts).
|
||||
* @param[in,out] arg The void pointer argument passed to the
|
||||
* attach_detach method.
|
||||
* @param[out] event_set Pointer to a buffer for a set of events for which a
|
||||
* PHY status change was detected.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
* @see dwmac_phy_event for events.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_phy_events_status_get)(
|
||||
void *arg,
|
||||
dwmac_phy_event *event_set );
|
||||
|
||||
/**
|
||||
* @brief Start the network PHY.
|
||||
*
|
||||
* Do anything necessary to start the network PHY (start generating
|
||||
* events, ...).
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwcmac_if_phy_start)( void *arg );
|
||||
|
||||
/**
|
||||
* @brief Stop the network PHY.
|
||||
*
|
||||
* Do anything necessary to stop the network PHY (stop generating events, ...).
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwcmac_if_phy_stop)( void *arg );
|
||||
|
||||
/**
|
||||
* @brief Allocate nocache RAM.
|
||||
*
|
||||
* Allocate uncached RAM.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @param[out] memory Pointer of a buffer to write the address of the
|
||||
* allocated memory to.
|
||||
* @param[in] size Number of bytes to be allocated
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_mem_alloc_nocache)(
|
||||
void *arg,
|
||||
void **memory,
|
||||
const size_t size );
|
||||
|
||||
/**
|
||||
* @brief Free nocache RAM.
|
||||
*
|
||||
* Release uncached RAM.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @param[in] memory Pointer to the memory to be freed.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_mem_free_nocache)(
|
||||
void *arg,
|
||||
void *memory );
|
||||
|
||||
/**
|
||||
* @brief Bus setup.
|
||||
*
|
||||
* Callback method for setting up the system bus for the network driver.
|
||||
* @param[in,out] arg The void pointer argument passed to the attach_detach
|
||||
* method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach for the attach_detach method.
|
||||
*/
|
||||
typedef int
|
||||
(*dwmac_if_bus_setup)( void *arg );
|
||||
|
||||
/**
|
||||
* @brief Callback methods.
|
||||
*
|
||||
* The address of an instance of such a callback struct must get passed
|
||||
* to the attach_detach method of the network driver.
|
||||
* Via these callback methods, those parts of the network driver which
|
||||
* are micro controller specific or PCB specific will get handled.
|
||||
* @see dwmac_network_if_attach_detach() for the drivers attach_detach method.
|
||||
*/
|
||||
typedef struct {
|
||||
/** @brief Enable the network interface controller. */
|
||||
dwmac_if_nic_enable nic_enable;
|
||||
|
||||
/** @brief Disable the network interface controller. */
|
||||
dwmac_if_nic_disable nic_disable;
|
||||
|
||||
/** @brief Enable (power up, ... ) the network PHY. */
|
||||
dwmac_if_phy_enable phy_enable;
|
||||
|
||||
/** @brief Disable (power down, ... ) the network PHY. */
|
||||
dwmac_if_phy_disable phy_disable;
|
||||
|
||||
/** @brief Enable a set of PHY events for generation upon status change. */
|
||||
dwmac_if_phy_event_enable phy_event_enable;
|
||||
|
||||
/** @brief Clear the event status (e.g. interrupt staus) of the PHY. */
|
||||
dwmac_if_phy_event_status_clear phy_event_clear;
|
||||
|
||||
/** @brief Get set of tripped events from PHY. */
|
||||
dwmac_if_phy_events_status_get phy_events_get;
|
||||
|
||||
/** @brief Start the phy (start generating events, ...). */
|
||||
dwcmac_if_phy_start phy_start;
|
||||
|
||||
/** @brief Stop the phy (stop generating events, ...). */
|
||||
dwcmac_if_phy_stop phy_stop;
|
||||
|
||||
/** @brief Allocate uncached memory. */
|
||||
dwmac_if_mem_alloc_nocache mem_alloc_nocache;
|
||||
|
||||
/** @brief Free uncached memory. */
|
||||
dwmac_if_mem_free_nocache mem_free_nocache;
|
||||
|
||||
/** @brief Setup handling for bus upon device startup. */
|
||||
dwmac_if_bus_setup bus_setup;
|
||||
} dwmac_callback_cfg;
|
||||
|
||||
/** @brief Initializer for callback methods.
|
||||
*
|
||||
* Initializes a struct which contains pointers to the callback methods
|
||||
* required by the driver.
|
||||
* @see dwmac_callback_cfg for the struct.
|
||||
* @param[in] nic_enable Callback method for for enabling the
|
||||
* network interface controller.
|
||||
* @param[in] nic_disable Callback method for disabling the
|
||||
* network interface controller.
|
||||
* @param[in] phy_enable Callback method for enabling the
|
||||
* network PHY.
|
||||
* @param[in] phy_disable Callback method for disabling the
|
||||
* network PHY.
|
||||
* @param[in] phy_event_enable Callback method for enabling PHY status
|
||||
* changes for event generation.
|
||||
* @param[in] phy_event_clear Callback method for
|
||||
* clearing/acknowledging PHY events.
|
||||
* @param[in] phy_events_get Callback method for reading the status of
|
||||
* PHY events.
|
||||
* @param[in] phy_start Callback method for starting event
|
||||
* generation by the network PHY.
|
||||
* @param[in] phy_stop Callback method for stoping event
|
||||
* generation by the network PHY.
|
||||
* @param[in] mem_alloc_nocache Callback method for allocating uncached
|
||||
* RAM.
|
||||
* @param[in] mem_free_nocache Callback method for releasing uncached
|
||||
* RAM.
|
||||
* @param[in] bus_setup Callback method for setting up the system
|
||||
* bus.
|
||||
* @returns An initialized struct of pointers to callback methods.
|
||||
* @see dwmac_if_nic_enable for the NIC enable methods.
|
||||
* @see dwmac_if_nic_disable for NIC disable methods.
|
||||
* @see dwmac_if_phy_enable for PHY enable methods.
|
||||
* @see dwmac_if_phy_disable for PHY disable methods.
|
||||
* @see dwmac_if_phy_event_enable for PHY envent enable methods.
|
||||
* @see dwmac_if_phy_event_status_clear for PHY event status clear methods.
|
||||
* @see dwmac_if_phy_events_status_get for PHY event status get methods.
|
||||
* @see dwcmac_if_phy_start for PHY start methods.
|
||||
* @see dwcmac_if_phy_stop for PHY stop methods.
|
||||
* @see dwmac_if_mem_alloc_nocache for nocache mem alloc methods.
|
||||
* @see dwmac_if_mem_free_nocache for nocache mem free methods.
|
||||
* @see dwmac_if_bus_setup for bus setup methods.
|
||||
*/
|
||||
#define DWMAC_CALLBACK_CFG_INITIALIZER( \
|
||||
nic_enable, \
|
||||
nic_disable, \
|
||||
phy_enable, \
|
||||
phy_disable, \
|
||||
phy_event_enable, \
|
||||
phy_event_clear, \
|
||||
phy_events_get, \
|
||||
phy_start, \
|
||||
phy_stop, \
|
||||
mem_alloc_nocache, \
|
||||
mem_free_nocache, \
|
||||
bus_setup \
|
||||
) \
|
||||
{ \
|
||||
nic_enable, \
|
||||
nic_disable, \
|
||||
phy_enable, \
|
||||
phy_disable, \
|
||||
phy_event_enable, \
|
||||
phy_event_clear, \
|
||||
phy_events_get, \
|
||||
phy_start, \
|
||||
phy_stop, \
|
||||
mem_alloc_nocache, \
|
||||
mem_free_nocache, \
|
||||
bus_setup \
|
||||
}
|
||||
|
||||
/** @brief Ethernet MAC operations.
|
||||
*
|
||||
* Actually this is a mere wrapper which contains void ponters to the core
|
||||
* operations and DMA operations to be used by the driver (void pointer
|
||||
* for the purpose of information hiding).
|
||||
* There will be two instances of such a struct:
|
||||
* One for DWMAC 10/100 ethernet operations and one for DWMAC 1000 ethernet
|
||||
* operations.
|
||||
* The address of either of these must get passed to the initializer of the
|
||||
* driver configuration for configuring the driver.
|
||||
* @see DWMAC_100_ETHERNET_MAC_OPS for DWMAC 10/100 ethernet operations.
|
||||
* @see DWMAC_1000_ETHERNET_MAC_OPS for DWMAC 1000 ethernet operations.
|
||||
* @see DWMAC_CFG_INITIALIZER driver configuration initializer.
|
||||
* @see DWMAC_ETHERNET_MAC_OPS_INITIALIZER for an initializer for the MAC
|
||||
* operations
|
||||
*/
|
||||
typedef struct {
|
||||
const void *core;
|
||||
const void *dma;
|
||||
} dwmac_ethernet_mac_ops;
|
||||
|
||||
/** @brief Ethernet MAC operations initializer.
|
||||
*
|
||||
* Initializes a structure of ethernet MAC operations.
|
||||
* @see dwmac_ethernet_mac_ops for the struct.
|
||||
* @param[in] core_ops_addr Address of the core operations to be used by the
|
||||
* driver.
|
||||
* @param[in] dma_ops_addr Address of the DMA operations to be used by the
|
||||
* driver.
|
||||
* @returns An initialized struct of ethernet mac operations.
|
||||
*/
|
||||
#define DWMAC_ETHERNET_MAC_OPS_INITIALIZER( \
|
||||
core_ops_addr, \
|
||||
dma_ops_addr \
|
||||
) \
|
||||
{ \
|
||||
core_ops_addr, \
|
||||
dma_ops_addr \
|
||||
}
|
||||
|
||||
/** @brief Descriptor operations.
|
||||
*
|
||||
* Actually this is a mere wrapper which contains a void pointer to a
|
||||
* descriptor operations struct which can be used by the driver (void pointer
|
||||
* for the purpose of information hiding).
|
||||
* There will be two instances of such a struct:
|
||||
* One for normal DMA descriptors and one for enhanced DMA descriptors.
|
||||
* The address of either of these must get passed to the configuration
|
||||
* initializer for configuring the driver.
|
||||
* @see DWMAC_DESCRIPTOR_OPS_NORMAL for normal DMA descriptor operations.
|
||||
* @see DWMAC_DESCRIPTOR_OPS_ENHANCED for enhanced DMA descriptor operations.
|
||||
* @see DWMAC_CFG_INITIALIZER for the configuration initializer.
|
||||
* @see DWMAC_DESCRIPTOR_OPS_INITIALIZER for an initializer an initializer
|
||||
* for descriptor operations.
|
||||
*/
|
||||
typedef struct {
|
||||
/** @brief Address of the descriptor operations to be used by the driver */
|
||||
const void *ops;
|
||||
} dwmac_descriptor_ops;
|
||||
|
||||
/** @brief Initializer for descriptor operations.
|
||||
*
|
||||
* Initializes a struct which simply makes up a wrapper for DMA descriptor
|
||||
* operations.
|
||||
* @param[in] desc_ops_addr Address of the descriptor operations.
|
||||
* @returns an initialized descriptor operations struct.
|
||||
* @see dwmac_descriptor_ops for the struct.
|
||||
*/
|
||||
#define DWMAC_DESCRIPTOR_OPS_INITIALIZER( \
|
||||
desc_ops_addr \
|
||||
) \
|
||||
{ \
|
||||
desc_ops_addr \
|
||||
}
|
||||
|
||||
/** @brief Ethernet MAC operations for DWMAC 1000.
|
||||
*
|
||||
* Pass the address of DWMAC_1000_ETHERNET_MAC_OPS to the configuration
|
||||
* initializer if the driver is supposed to control a DWMAC 1000.
|
||||
* @see DWMAC_CFG_INITIALIZER for the configuration initializer.
|
||||
*/
|
||||
extern const dwmac_ethernet_mac_ops DWMAC_1000_ETHERNET_MAC_OPS;
|
||||
|
||||
/** @brief Ethernet MAC operations for DWMAC 10/100.
|
||||
*
|
||||
* Pass the address of DWMAC_100_ETHERNET_MAC_OPS to the configuration
|
||||
* initializer if the driver is supposed to control a DWMAC 10/100.
|
||||
* NOTE: Currently the DWMAC_100_ETHERNET_MAC_OPS are not yet implemented.
|
||||
* @see DWMAC_CFG_INITIALIZER for the configuration initializer.
|
||||
*/
|
||||
extern const dwmac_ethernet_mac_ops DWMAC_100_ETHERNET_MAC_OPS;
|
||||
|
||||
/** @brief DMA descriptor operations for normal descriptors.
|
||||
*
|
||||
* Pass the address of DWMAC_DESCRIPTOR_OPS_NORMAL to the configuration
|
||||
* initializer if you intend to use the normal DMA descriptors.
|
||||
* NOTE: Currently the DWMAC_DESCRIPTOR_OPS_NORMAL are not yet implmented.
|
||||
* @see DWMAC_CFG_INITIALIZER for the configuration initializer.
|
||||
*/
|
||||
extern const dwmac_descriptor_ops DWMAC_DESCRIPTOR_OPS_NORMAL;
|
||||
|
||||
/** @brief DMA descriptor operations for enhanced descriptors.
|
||||
*
|
||||
* Pass the address of DWMAC_DESCRIPTOR_OPS_ENHANCED to the configuration
|
||||
* initializer if you intend to use the enhanced DMA descriptors.
|
||||
* @see DWMAC_CFG_INITIALIZER for the configuration initializer.
|
||||
*/
|
||||
extern const dwmac_descriptor_ops DWMAC_DESCRIPTOR_OPS_ENHANCED;
|
||||
|
||||
/** @brief Burst size. */
|
||||
typedef enum {
|
||||
/** @brief Burst size = 1. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_1 = 0,
|
||||
|
||||
/** @brief Burst size = 2. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_2 = 1,
|
||||
|
||||
/** @brief Burst size = 4. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_4 = 3,
|
||||
|
||||
/** @brief Burst size = 8. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_8 = 7,
|
||||
|
||||
/** @brief Burst size = 16. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_16 = 15,
|
||||
|
||||
/** @brief Burst size = 32. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_32 = 31,
|
||||
|
||||
/** @brief Burst size = 64. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_64 = 63,
|
||||
|
||||
/** @brief Burst size = 128. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_128 = 127,
|
||||
|
||||
/** @brief Burst size = 256. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_LENGTH_256 = 255
|
||||
} dwmac_dma_cfg_bus_mode_burst_length;
|
||||
|
||||
/** @brief Burst mode. */
|
||||
typedef enum {
|
||||
/** @brief Single burst or incrment bursts. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_MODE_SINGLE_OR_INCR,
|
||||
|
||||
/** @brief Fixed burst size. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_MODE_FIXED
|
||||
} dwmac_dma_cfg_bus_mode_burst_mode;
|
||||
|
||||
/** @brief Mixed burst mode support. */
|
||||
typedef enum {
|
||||
/** @brief Mixed burst mode is not supported. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_NOT_MIXED,
|
||||
/** @brief Mixed burst mode is supported. */
|
||||
DWMAC_DMA_CFG_BUS_MODE_BURST_MIXED
|
||||
} dwmac_dma_cfg_bus_mode_burst_mixed;
|
||||
|
||||
/** @brief Burst length 4 support. */
|
||||
typedef enum {
|
||||
/** @brief Bursts of length 4 are not supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_4_NOT_SUPPORTED,
|
||||
|
||||
/** @brief Bursts of length 4 are supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_4_SUPPORTED
|
||||
} dwmac_dma_cfg_axi_burst_length_4_support;
|
||||
|
||||
/** @brief Burst length 8 support. */
|
||||
typedef enum {
|
||||
/** @brief Bursts of length 8 are not supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_8_NOT_SUPPORTED,
|
||||
|
||||
/** @brief Bursts of length 8 are supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_8_SUPPORTED
|
||||
} dwmac_dma_cfg_axi_burst_length_8_support;
|
||||
|
||||
/** @brief Burst length 16 support. */
|
||||
typedef enum {
|
||||
/** @brief Bursts of length 16 are not supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_16_NOT_SUPPORTED,
|
||||
|
||||
/** @brief Bursts of length 16 are supported. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_LENGTH_16_SUPPORTED
|
||||
} dwmac_dma_cfg_axi_burst_length_16_support;
|
||||
|
||||
/** @brief DMA Burst Boundary parameters. */
|
||||
typedef enum {
|
||||
/** @brief Transfers do not cross 4 kB boundary. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_BOUNDARY_4_KB,
|
||||
|
||||
/** @brief Transfers do not cross 1 kB boundary. */
|
||||
DWMAC_DMA_CFG_AXI_BURST_BOUNDARY_1_KB
|
||||
} dwmac_dma_cfg_axi_burst_boundary;
|
||||
|
||||
/**
|
||||
* @brief DMA configuration.
|
||||
*
|
||||
* Configuration data for the DMA of the network driver.
|
||||
* @see DWMAC_DMA_CFG_INITIALIZER for an inititializer.
|
||||
*/
|
||||
typedef union {
|
||||
uint16_t raw;
|
||||
struct {
|
||||
/** @brief Maximum number of beats to be transferred in one DMA transaction.
|
||||
*
|
||||
* This is the maximum value that is used in a single block Read or Write.
|
||||
* The DMA always attempts to burst as specified in bus_mode_burst_length
|
||||
* each time it starts a Burst transfer on the host bus.
|
||||
* Any non-permissible value results in undefined behavior.
|
||||
* The bus_mode_burst_length values have the following limitation:
|
||||
* The maximum number of possible beats (bus_mode_burst_length) is limited
|
||||
* by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus
|
||||
* width on the DMA.
|
||||
* The FIFO has a constraint that the maximum beat supported is half the
|
||||
* depth of the FIFO, except when specified.
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_length for permissible values */
|
||||
uint16_t bus_mode_burst_length : 6;
|
||||
|
||||
/** @brief Controls whether the AXI Master performs fixed bursts or not.
|
||||
*
|
||||
* When set to DWMAC_DMA_CFG_BUS_MODE_BURST_MODE_FIXED, the AXI interface
|
||||
* uses FIXED bursts during the start of the normal burst transfers.
|
||||
* When set to DWMAC_DMA_CFG_BUS_MODE_BURST_MODE_SINGLE_OR_INCR, the AXI
|
||||
* interface uses SINGLE and INCR burst transfer operations.
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_mode for valid parameters. */
|
||||
uint16_t bus_mode_burst_mode : 1;
|
||||
|
||||
/** @brief Controls whether mixed bursts will be used or not.
|
||||
*
|
||||
* Mixed burst has no effect when if DWMAC_DMA_CFG_BUS_MODE_BURST_MODE_FIXED is set.
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_mixed for valid parameters. */
|
||||
uint16_t bus_mode_burst_mixed : 1;
|
||||
|
||||
/** @brief Controls support of burst length 4.
|
||||
*
|
||||
* When set to DWMAC_DMA_CFG_AXI_BURST_LENGTH_4_SUPPORTED, the GMAC-AXI is
|
||||
* allowed to select a burst length of 4 on the AXI Master interface.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_4_support for valid parameters see. */
|
||||
uint16_t axi_burst_length_4_support : 1;
|
||||
|
||||
/** @brief Controls support of burst length 8.
|
||||
*
|
||||
* When set to DWMAC_DMA_CFG_AXI_BURST_LENGTH_8_SUPPORTED, the GMAC-AXI is
|
||||
* allowed to select a burst length of 8 on the AXI Master interface.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_8_support For valid parameters. */
|
||||
uint16_t axi_burst_length_8_support : 1;
|
||||
|
||||
/** @brief Controls support of burst length 16.
|
||||
*
|
||||
* When set to DWMAC_DMA_CFG_AXI_BURST_LENGTH_16_SUPPORTED fixed bust is
|
||||
* not selected, the GMAC-AXI is allowed to select a burst length of 16 on
|
||||
* the AXI Master interface.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_16_support for valid parameters see. */
|
||||
uint16_t axi_burst_length_16_support : 1;
|
||||
|
||||
/** @brief Select Burst Boundary.
|
||||
*
|
||||
* When set to DWMAC_DMA_CFG_AXI_BURST_BOUNDARY_1_KB, the GMAC-AXI Master
|
||||
* performs burst transfers that do not cross 1 KB boundary.
|
||||
* When set to DWMAC_DMA_CFG_AXI_BURST_BOUNDARY_4_KB, the GMAC-AXI Master
|
||||
* performs burst transfers that do not cross 4 KB boundary.
|
||||
* @see dwmac_dma_cfg_axi_burst_boundary for valid parameters see. */
|
||||
uint16_t axi_burst_boundary : 1;
|
||||
|
||||
uint16_t unused : 4;
|
||||
};
|
||||
} dwmac_dma_cfg;
|
||||
|
||||
/** @brief DMA Configuration initializer.
|
||||
*
|
||||
* Initializer for a DMA configuration struct.
|
||||
*
|
||||
* @param[in] bus_mode_burst_length Number of bytes to be sent in one
|
||||
* burst within a DMA transfer on the
|
||||
* bus .
|
||||
* @param[in] bus_mode_burst_mode Mode to be used for burst transfers.
|
||||
* @param[in] bus_mode_burst_mixed Use mixed bursts or not. Fixed bursts
|
||||
* have priority over mixed bursts.
|
||||
* @param[in] axi_burst_length_4_support Support or don't support burst
|
||||
* lengths of 4.
|
||||
* @param[in] axi_burst_length_8_support Support or don't support burst
|
||||
* lengths of 8.
|
||||
* @param[in] axi_burst_length_16_support Support or don't support burst
|
||||
* lengths of 16.
|
||||
* @param[in] axi_burst_boundary Select the burst boundary.
|
||||
* @returns An initialized struct of DMA configuration parameters.
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_length for burst lengths.
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_mode for burst modes
|
||||
* @see dwmac_dma_cfg_bus_mode_burst_mixed for burst mixing.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_4_support for burst length 4 support.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_8_support for burst length 8 support.
|
||||
* @see dwmac_dma_cfg_axi_burst_length_16_support for burst length 16 support.
|
||||
* @see dwmac_dma_cfg_axi_burst_boundary for burst boundaries.
|
||||
*/
|
||||
#define DWMAC_DMA_CFG_INITIALIZER( \
|
||||
bus_mode_burst_length, \
|
||||
bus_mode_burst_mode, \
|
||||
bus_mode_burst_mixed, \
|
||||
axi_burst_length_4_support, \
|
||||
axi_burst_length_8_support, \
|
||||
axi_burst_length_16_support, \
|
||||
axi_burst_boundary \
|
||||
) \
|
||||
{ \
|
||||
BSP_FLD16( bus_mode_burst_length, 0, 5 ) \
|
||||
| BSP_FLD16( bus_mode_burst_mode, 6, 6 ) \
|
||||
| BSP_FLD16( bus_mode_burst_mixed, 7, 7 ) \
|
||||
| BSP_FLD16( axi_burst_length_4_support, 8, 8 ) \
|
||||
| BSP_FLD16( axi_burst_length_8_support, 9, 9 ) \
|
||||
| BSP_FLD16( axi_burst_length_16_support, 10, 10 ) \
|
||||
| BSP_FLD16( axi_burst_boundary, 11, 11 ) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Driver configuration.
|
||||
*
|
||||
* Configuration data for the network driver.
|
||||
* See @see DWMAC_CFG_INITIALIZER for an initializer.
|
||||
*/
|
||||
typedef struct {
|
||||
/** @brief The clock to be used for the gmii interface in Hz. */
|
||||
const uint32_t GMII_CLK_RATE;
|
||||
|
||||
/** @brief Start address of the MAC group registers. */
|
||||
volatile void *addr_gmac_regs;
|
||||
|
||||
/** @brief Start address of the DMA group registers. */
|
||||
volatile void *addr_dma_regs;
|
||||
|
||||
/** @brief Address of the PHY on the mdio bus (5 bit). */
|
||||
const uint8_t MDIO_BUS_ADDR;
|
||||
|
||||
/** @brief Bytes per L1 cache line. */
|
||||
const uint8_t L1_CACHE_LINE_SIZE;
|
||||
|
||||
/** @brief Interrupt vector number for EMAC IRQs. */
|
||||
const rtems_vector_number IRQ_EMAC;
|
||||
|
||||
/** @brief Optional configuration for bus mode and axi bus mode. */
|
||||
const dwmac_dma_cfg *DMA_CFG;
|
||||
|
||||
/** @brief Methods which must get provided to the by the micro controller. */
|
||||
const dwmac_callback_cfg CALLBACK;
|
||||
|
||||
/** @brief Operations which are specific to the ethernet MAC. */
|
||||
const dwmac_ethernet_mac_ops *MAC_OPS;
|
||||
|
||||
/** @brief DMA descriptor operations. */
|
||||
const dwmac_descriptor_ops *DESC_OPS;
|
||||
} dwmac_cfg;
|
||||
|
||||
/**
|
||||
* @brief Configuration initializer.
|
||||
*
|
||||
* Initializes the configuration data to be passed to
|
||||
* the initialization method.
|
||||
* @see dwmac_network_if_attach_detach().
|
||||
*
|
||||
* @param[in] mdio_clk_rate The clock to be used for the gmii
|
||||
* interface in Hz.
|
||||
* @param[in] macgrp_regs_addr Base address of the MAC group registers.
|
||||
* @param[in] dmagrp_regs_addr Base address of the DMA group registers.
|
||||
* @param[in] mdio_bus_addr Address of the network PHY on the
|
||||
* mdio bus.
|
||||
* @param[in] l1_cache_line_size Size of a cache line in the level 1 cache.
|
||||
* @param[in] irq_emac Number of the EMAC interrupt.
|
||||
* @param[in] arch_has_prefetch True if architecture supports.
|
||||
* prefetching, false if not.
|
||||
* @param[in] dma_cfg_addr Address of the optional DMA configuration.
|
||||
* Set to NULL for defaults.
|
||||
* @param[in] nic_enable Callback method for for enabling the
|
||||
* network interface controller.
|
||||
* @param[in] nic_disable Callback method for disabling the
|
||||
* network interface controller.
|
||||
* @param[in] phy_enable Callback method for enabling the
|
||||
* network PHY.
|
||||
* @param[in] phy_disable Callback method for disabling the
|
||||
* network PHY.
|
||||
* @param[in] phy_event_enable Callback method for enabling PHY status
|
||||
* changes for event generation.
|
||||
* @param[in] phy_event_clear Callback method for
|
||||
* clearing/acknowledging PHY events.
|
||||
* @param[in] phy_events_get Callback method for reading the status of
|
||||
* PHY events.
|
||||
* @param[in] phy_start Callback method for starting event
|
||||
* generation by the network PHY.
|
||||
* @param[in] phy_stop Callback method for stoping event
|
||||
* generation by the network PHY.
|
||||
* @param[in] mem_alloc_nocache Callback method for allocating uncached
|
||||
* RAM.
|
||||
* @param[in] mem_free_nocache Callback method for releasing uncached
|
||||
* RAM.
|
||||
* @param[in] bus_setup Callback method for setting up the system
|
||||
* bus.
|
||||
* @param[in] ethernet_mac_ops_addr Address of a struct encapsulating
|
||||
* ethernet MAC operations for DWMAC 1000 or
|
||||
* DWMAC 10/100.
|
||||
* @param[in] descriptor_ops_addr Address of a struct encasulating DMA
|
||||
* descriptor operations for either normal
|
||||
* descriptors or enhanced descriptors.
|
||||
* @returns An initialized struct of configuration parameters.
|
||||
* @see dwmac_cfg for the struct returned.
|
||||
* @see dwmac_dma_cfg for DMA configurations.
|
||||
* @see dwmac_if_nic_enable for NIC enable methods.
|
||||
* @see dwmac_if_nic_disable for NIC disable methods.
|
||||
* @see dwmac_if_phy_enable for PHY enable methods.
|
||||
* @see dwmac_if_phy_disable for PHY disable methods.
|
||||
* @see dwmac_if_phy_event_enable for PHY event enble methods.
|
||||
* @see dwmac_if_phy_event_status_clear for PHY status clear methods.
|
||||
* @see dwmac_if_phy_events_status_get for PHY status get mehods.
|
||||
* @see dwcmac_if_phy_start for PHY start methods.
|
||||
* @see dwcmac_if_phy_stop for PHY stop methods.
|
||||
* @see dwmac_if_mem_alloc_nocache for nocache memory allocate methods.
|
||||
* @see dwmac_if_mem_free_nocache for nocache memory release methods.
|
||||
* @see dwmac_if_bus_setup for bus setup methods.
|
||||
* @see DWMAC_1000_ETHERNET_MAC_OPS for DWMAC 1000 MAC operations.
|
||||
* @see DWMAC_100_ETHERNET_MAC_OPS for DWMAC 10/100 MAC operations.
|
||||
* @see DWMAC_DESCRIPTOR_OPS_NORMAL for normal DMA descriptor operations.
|
||||
* @see DWMAC_DESCRIPTOR_OPS_ENHANCED for enhanced DMA descriptor operations.
|
||||
*/
|
||||
#define DWMAC_CFG_INITIALIZER( \
|
||||
mdio_clk_rate, \
|
||||
macgrp_regs_addr, \
|
||||
dmagrp_regs_addr, \
|
||||
mdio_bus_addr, \
|
||||
l1_cache_line_size, \
|
||||
irq_emac, \
|
||||
dma_cfg_addr, \
|
||||
nic_enable, \
|
||||
nic_disable, \
|
||||
phy_enable, \
|
||||
phy_disable, \
|
||||
phy_event_enable, \
|
||||
phy_event_clear, \
|
||||
phy_events_get, \
|
||||
phy_start, \
|
||||
phy_stop, \
|
||||
mem_alloc_nocache, \
|
||||
mem_free_nocache, \
|
||||
bus_setup, \
|
||||
ethernet_mac_ops_addr, \
|
||||
descriptor_ops_addr \
|
||||
) \
|
||||
{ \
|
||||
mdio_clk_rate, \
|
||||
macgrp_regs_addr, \
|
||||
dmagrp_regs_addr, \
|
||||
mdio_bus_addr, \
|
||||
l1_cache_line_size, \
|
||||
irq_emac, \
|
||||
dma_cfg_addr, \
|
||||
DWMAC_CALLBACK_CFG_INITIALIZER( \
|
||||
nic_enable, \
|
||||
nic_disable, \
|
||||
phy_enable, \
|
||||
phy_disable, \
|
||||
phy_event_enable, \
|
||||
phy_event_clear, \
|
||||
phy_events_get, \
|
||||
phy_start, \
|
||||
phy_stop, \
|
||||
mem_alloc_nocache, \
|
||||
mem_free_nocache, \
|
||||
bus_setup \
|
||||
), \
|
||||
ethernet_mac_ops_addr, \
|
||||
descriptor_ops_addr \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialization method.
|
||||
*
|
||||
* Initializes the network driver and "links" it to the network stack.
|
||||
*
|
||||
* @param[in] bsd_config The BSD configuation passed to all
|
||||
* network_if_attach_detach() methods.
|
||||
* @param[in] driver_config Address of of a struct containing driver
|
||||
* specific configuration data.
|
||||
* @param[in] arg An optional argument which will get passed to all
|
||||
* callback methods.
|
||||
* @param[in] attaching 1 for attching and 0 for detaching.
|
||||
* NOTE: Detaching is not supported!
|
||||
* @returns Address of the drivers context if successful or NULL if not
|
||||
* successful.
|
||||
* @see dwmac_cfg for the driver configuration struct
|
||||
* @see DWMAC_CFG_INITIALIZER() for an initializer for the driver configuration
|
||||
*/
|
||||
void *dwmac_network_if_attach_detach(
|
||||
struct rtems_bsdnet_ifconfig *bsd_config,
|
||||
const dwmac_cfg *driver_config,
|
||||
void *arg,
|
||||
int attaching );
|
||||
|
||||
/**
|
||||
* @brief Read from PHY
|
||||
*
|
||||
* Read a value from a register of the network PHY.
|
||||
*
|
||||
* @param[in,out] arg Pointer returned from the attach_detach method.
|
||||
* @param[in] phy_reg The PHY register to be read from.
|
||||
* @param[out] val Buffer address for the value to be read.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach() for the attach detach method.
|
||||
*/
|
||||
int dwmac_if_read_from_phy(
|
||||
void *arg,
|
||||
const unsigned phy_reg,
|
||||
uint16_t *val );
|
||||
|
||||
/**
|
||||
* @brief Write to PHY.
|
||||
*
|
||||
* Write a value to a register of the network PHY.
|
||||
*
|
||||
* @param[in,out] arg Pointer returned from the attach_detach method.
|
||||
* @param[in] phy_reg The PHY register to be written to.
|
||||
* @param[in] val The value to be written.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach() for the attach_detach method.
|
||||
*/
|
||||
int dwmac_if_write_to_phy(
|
||||
void *arg,
|
||||
const unsigned phy_reg,
|
||||
const uint16_t val );
|
||||
|
||||
/**
|
||||
* @brief Handle PHY event.
|
||||
*
|
||||
* Handle an event from the network PHY.
|
||||
*
|
||||
* @param[in,out] arg Pointer returned from the attach_detach method.
|
||||
* @returns 0 on success, error code from errno.h on failure.
|
||||
* @see dwmac_network_if_attach_detach() for the attach_detach method.
|
||||
*/
|
||||
int dwmac_if_handle_phy_event( void *arg );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* DWMAC_H_ */
|
||||
@@ -97,6 +97,10 @@ PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/smc91111.h
|
||||
$(PROJECT_INCLUDE)/libchip/smc91111exp.h: network/smc91111exp.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/smc91111exp.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/smc91111exp.h
|
||||
|
||||
$(PROJECT_INCLUDE)/libchip/dwmac.h: network/dwmac.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/dwmac.h
|
||||
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/dwmac.h
|
||||
endif
|
||||
$(PROJECT_INCLUDE)/libchip/rtc.h: rtc/rtc.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
|
||||
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/rtc.h
|
||||
|
||||
Reference in New Issue
Block a user