forked from Imagelibrary/rtems
Renamed callconv.texi to callconv.t.
This commit is contained in:
Joel Sherrill
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@c
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@c COPYRIGHT (c) 1988-1998.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@ifinfo
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@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Low Power Model, Top
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@end ifinfo
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@chapter Calling Conventions
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@ifinfo
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@menu
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* Calling Conventions Introduction::
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* Calling Conventions Programming Model::
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* Calling Conventions Call and Return Mechanism::
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* Calling Conventions Calling Mechanism::
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* Calling Conventions Register Usage::
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* Calling Conventions Parameter Passing::
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* Calling Conventions User-Provided Routines::
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@end menu
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@end ifinfo
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@ifinfo
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@node Calling Conventions Introduction, Calling Conventions Programming Model, Calling Conventions, Calling Conventions
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@end ifinfo
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@section Introduction
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Each high-level language compiler generates
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subroutine entry and exit code based upon a set of rules known
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as the compiler's calling convention. These rules address the
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following issues:
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@itemize @bullet
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@item register preservation and usage
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@item parameter passing
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@item call and return mechanism
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@end itemize
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A compiler's calling convention is of importance when
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interfacing to subroutines written in another language either
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assembly or high-level. Even when the high-level language and
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target processor are the same, different compilers may use
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different calling conventions. As a result, calling conventions
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are both processor and compiler dependent.
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RTEMS supports the Embedded Application Binary Interface (EABI)
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calling convention. Documentation for EABI is available by sending
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a message with a subject line of "EABI" to eabi@@goth.sis.mot.com.
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@ifinfo
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@node Calling Conventions Programming Model, Calling Conventions Non-Floating Point Registers, Calling Conventions Introduction, Calling Conventions
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@end ifinfo
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@section Programming Model
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@ifinfo
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@menu
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* Calling Conventions Non-Floating Point Registers::
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* Calling Conventions Floating Point Registers::
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* Calling Conventions Special Registers::
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@end menu
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@end ifinfo
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This section discusses the programming model for the
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PowerPC architecture.
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@ifinfo
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@node Calling Conventions Non-Floating Point Registers, Calling Conventions Floating Point Registers, Calling Conventions Programming Model, Calling Conventions Programming Model
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@end ifinfo
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@subsection Non-Floating Point Registers
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The PowerPC architecture defines thirty-two non-floating point registers
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directly visible to the programmer. In thirty-two bit implementations, each
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register is thirty-two bits wide. In sixty-four bit implementations, each
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register is sixty-four bits wide.
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These registers are referred to as @code{gpr0} to @code{gpr31}.
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Some of the registers serve defined roles in the EABI programming model.
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The following table describes the role of each of these registers:
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@ifset use-ascii
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@example
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@group
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+---------------+----------------+------------------------------+
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| Register Name | Alternate Name | Description |
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+---------------+----------------+------------------------------+
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| r1 | sp | stack pointer |
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+---------------+----------------+------------------------------+
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| | | global pointer to the Small |
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| r2 | na | Constant Area (SDA2) |
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+---------------+----------------+------------------------------+
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| r3 - r12 | na | parameter and result passing |
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+---------------+----------------+------------------------------+
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| | | global pointer to the Small |
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| r13 | na | Data Area (SDA) |
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+---------------+----------------+------------------------------+
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@end group
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@end example
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@end ifset
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@ifset use-tex
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@sp 1
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@tex
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\centerline{\vbox{\offinterlineskip\halign{
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\vrule\strut#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#&
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\hbox to 1.75in{\enskip\hfil#\hfil}&
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\vrule#&
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\hbox to 2.50in{\enskip\hfil#\hfil}&
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\vrule#\cr
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\noalign{\hrule}
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&\bf Register Name &&\bf Alternate Names&&\bf Description&\cr\noalign{\hrule}
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&r1&&sp&&stack pointer&\cr\noalign{\hrule}
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&r2&&NA&&global pointer to the Small&\cr
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&&&&&Constant Area (SDA2)&\cr\noalign{\hrule}
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&r3 - r12&&NA&¶meter and result passing&\cr\noalign{\hrule}
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&r13&&NA&&global pointer to the Small&\cr
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&&&&&Data Area (SDA2)&\cr\noalign{\hrule}
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}}\hfil}
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@end tex
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@end ifset
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@ifset use-html
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@html
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<CENTER>
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<TABLE COLS=3 WIDTH="80%" BORDER=2>
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<TR><TD ALIGN=center><STRONG>Register Name</STRONG></TD>
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<TD ALIGN=center><STRONG>Alternate Name</STRONG></TD>
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<TD ALIGN=center><STRONG>Description</STRONG></TD></TR>
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<TR><TD ALIGN=center>r1</TD>
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<TD ALIGN=center>sp</TD>
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<TD ALIGN=center>stack pointer</TD></TR>
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<TR><TD ALIGN=center>r2</TD>
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<TD ALIGN=center>na</TD>
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<TD ALIGN=center>global pointer to the Small Constant Area (SDA2)</TD></TR>
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<TR><TD ALIGN=center>r3 - r12</TD>
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<TD ALIGN=center>NA</TD>
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<TD ALIGN=center>parameter and result passing</TD></TR>
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<TR><TD ALIGN=center>r13</TD>
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<TD ALIGN=center>NA</TD>
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<TD ALIGN=center>global pointer to the Small Data Area (SDA)</TD></TR>
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</TABLE>
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</CENTER>
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@end html
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@end ifset
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@ifinfo
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@node Calling Conventions Floating Point Registers, Calling Conventions Special Registers, Calling Conventions Non-Floating Point Registers, Calling Conventions Programming Model
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@end ifinfo
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@subsection Floating Point Registers
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The PowerPC architecture includes thirty-two, sixty-four bit
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floating point registers. All PowerPC floating point instructions
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interpret these registers as 32 double precision floating point registers,
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regardless of whether the processor has 64-bit or 32-bit implementation.
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The floating point status and control register (fpscr) records exceptions
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and the type of result generated by floating-point operations.
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Additionally, it controls the rounding mode of operations and allows the
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reporting of floating exceptions to be enabled or disabled.
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@ifinfo
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@node Calling Conventions Special Registers, Calling Conventions Call and Return Mechanism, Calling Conventions Floating Point Registers, Calling Conventions Programming Model
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@end ifinfo
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@subsection Special Registers
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The PowerPC architecture includes a number of special registers
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which are critical to the programming model:
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@table @b
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@item Machine State Register
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The MSR contains the processor mode, power management mode, endian mode,
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exception information, privilege level, floating point available and
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floating point excepiton mode, address translation information and
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the exception prefix.
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@item Link Register
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The LR contains the return address after a function call. This register
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must be saved before a subsequent subroutine call can be made. The
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use of this register is discussed further in the @b{Call and Return
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Mechanism} section below.
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@item Count Register
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The CTR contains the iteration variable for some loops. It may also be used
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for indirect function calls and jumps.
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@end table
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@ifinfo
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@node Calling Conventions Call and Return Mechanism, Calling Conventions Calling Mechanism, Calling Conventions Special Registers, Calling Conventions
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@end ifinfo
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@section Call and Return Mechanism
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The PowerPC architecture supports a simple yet effective call
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and return mechanism. A subroutine is invoked
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via the "branch and link" (@code{bl}) and
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"brank and link absolute" (@code{bla})
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instructions. This instructions place the return address
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in the Link Register (LR). The callee returns to the caller by
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executing a "branch unconditional to the link register" (@code{blr})
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instruction. Thus the callee returns to the caller via a jump
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to the return address which is stored in the LR.
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The previous contents of the LR are not automatically saved
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by either the @code{bl} or @code{bla}. It is the responsibility
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of the callee to save the contents of the LR before invoking
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another subroutine. If the callee invokes another subroutine,
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it must restore the LR before executing the @code{blr} instruction
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to return to the caller.
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It is important to note that the PowerPC subroutine
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call and return mechanism does not automatically save and
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restore any registers.
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The LR may be accessed as special purpose register 8 (@code{SPR8}) using the
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"move from special register" (@code{mfspr}) and
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"move to special register" (@code{mtspr}) instructions.
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@ifinfo
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@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Call and Return Mechanism, Calling Conventions
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@end ifinfo
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@section Calling Mechanism
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All RTEMS directives are invoked using the regular
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PowerPC EABI calling convention via the @code{bl} or
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@code{bla} instructions.
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@ifinfo
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@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions
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@end ifinfo
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@section Register Usage
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As discussed above, the call instruction does not
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automatically save any registers. It is the responsibility
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of the callee to save and restore any registers which must be preserved
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across subroutine calls. The callee is responsible for saving
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callee-preserved registers to the program stack and restoring them
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before returning to the caller.
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@ifinfo
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@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions
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@end ifinfo
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@section Parameter Passing
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RTEMS assumes that arguments are placed in the
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general purpose registers with the first argument in
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register 3 (@code{r3}), the second argument in general purpose
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register 4 (@code{r4}), and so forth until the seventh
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argument is in general purpose register 10 (@code{r10}).
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If there are more than seven arguments, then subsequent arguments
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are placed on the program stack. The following pseudo-code
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illustrates the typical sequence used to call a RTEMS directive
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with three (3) arguments:
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@example
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load third argument into r5
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load second argument into r4
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load first argument into r3
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invoke directive
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@end example
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@ifinfo
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@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions
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@end ifinfo
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@section User-Provided Routines
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All user-provided routines invoked by RTEMS, such as
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user extensions, device drivers, and MPCI routines, must also
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adhere to these same calling conventions.
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