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2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>

Browse Source 
* sh7032/clock/ckinit.c, sh7032/delay/delay.c,
	sh7032/include/ispsh7032.h, sh7032/sci/sci.c,
	sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/clock/ckinit.c,
	sh7045/include/ispsh7045.h, sh7045/sci/sci.c,
	sh7045/sci/sci_termios.c, sh7045/score/cpu_asm.c,
	sh7045/timer/timer.c, sh7750/clock/ckinit.c,
	sh7750/include/rtems/score/ispsh7750.h, sh7750/include/sh/sh4uart.h,
	sh7750/sci/sh4uart.c, sh7750/score/cpu_asm.c,
	sh7750/score/ispsh7750.c, sh7750/timer/timer.c: Convert to using c99
	fixed size types.
This commit is contained in:
Ralf Corsepius
2004-03-31 02:00:03 +00:00
parent 8bc4430b7b
commit e96a950bcf
20 changed files with 139 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
c/src/lib/libcpu/sh/ChangeLog
View File

@@ -1,3 +1,16 @@
2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
* sh7032/clock/ckinit.c, sh7032/delay/delay.c,
sh7032/include/ispsh7032.h, sh7032/sci/sci.c,
sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/clock/ckinit.c,
sh7045/include/ispsh7045.h, sh7045/sci/sci.c,
sh7045/sci/sci_termios.c, sh7045/score/cpu_asm.c,
sh7045/timer/timer.c, sh7750/clock/ckinit.c,
sh7750/include/rtems/score/ispsh7750.h, sh7750/include/sh/sh4uart.h,
sh7750/sci/sh4uart.c, sh7750/score/cpu_asm.c,
sh7750/score/ispsh7750.c, sh7750/timer/timer.c: Convert to using c99
fixed size types.
2004-03-26 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: Add 2nd argument (rtems_updir) to RTEMS_TOP.

22
c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
View File

@@ -103,7 +103,7 @@ static unsigned int sh_clicks_per_tick(
#else
double fclicks_per_tick =
((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
return (unsigned32) fclicks_per_tick ;
return (uint32_t ) fclicks_per_tick ;
#endif
}
@@ -119,7 +119,7 @@ static unsigned int sh_clicks_per_tick(
* number of clock ticks since the driver was initialized.
*/
volatile rtems_unsigned32 Clock_driver_ticks;
volatile uint32_t Clock_driver_ticks;
static void Clock_exit( void );
static rtems_isr Clock_isr( rtems_vector_number vector );
@@ -132,8 +132,8 @@ static rtems_isr Clock_isr( rtems_vector_number vector );
* has passed.
*/
rtems_unsigned32 Clock_isrs; /* ISRs until next tick */
static rtems_unsigned32 Clock_isrs_const; /* only calculated once */
uint32_t Clock_isrs; /* ISRs until next tick */
static uint32_t Clock_isrs_const; /* only calculated once */
/*
* These are set by clock driver during its init
@@ -164,7 +164,7 @@ rtems_isr Clock_isr(
*
* perform any timer dependent tasks
*/
unsigned8 temp;
uint8_t temp;
/* reset the flags of the status register */
temp = read8( ITU_TSR0) & ITU_STAT_MASK;
@@ -194,10 +194,10 @@ void Install_clock(
rtems_isr_entry clock_isr
)
{
unsigned8 temp8 = 0;
unsigned32 microseconds_per_tick ;
unsigned32 cclicks_per_tick ;
unsigned16 Clock_limit ;
uint8_t temp8 = 0;
uint32_t microseconds_per_tick ;
uint32_t cclicks_per_tick ;
uint16_t Clock_limit ;
/*
* Initialize the clock tick device driver variables
@@ -280,7 +280,7 @@ void Install_clock(
void Clock_exit( void )
{
unsigned8 temp8 = 0;
uint8_t temp8 = 0;
/* turn off the timer interrupts */
/* set interrupt priority to 0 */
@@ -329,7 +329,7 @@ rtems_device_driver Clock_control(
void *pargp
)
{
rtems_unsigned32 isrlevel;
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)

6
c/src/lib/libcpu/sh/sh7032/delay/delay.c
View File

@@ -36,11 +36,11 @@
* => 4 * 5e-8 secs per delay loop
*/
void CPU_delay( unsigned32 microseconds )
void CPU_delay( uint32_t microseconds )
{
register unsigned32 clicks_per_usec =
register uint32_t clicks_per_usec =
rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
register unsigned32 _delay =
register uint32_t _delay =
(microseconds) * (clicks_per_usec);
asm volatile (
"0: add #-4,%0\n\

2
c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h
View File

@@ -31,7 +31,7 @@ extern "C" {
#include <rtems/score/types.h>
extern void __ISR_Handler( unsigned32 vector );
extern void __ISR_Handler( uint32_t vector );
/*

12
c/src/lib/libcpu/sh/sh7032/sci/sci.c
View File

@@ -44,7 +44,7 @@
struct scidev_t {
char * name ;
unsigned32 addr ;
uint32_t addr ;
rtems_device_minor_number minor ;
unsigned short opened ;
tcflag_t cflags ;
@@ -65,8 +65,8 @@ static int _sci_set_cflags(
struct scidev_t *sci_dev,
tcflag_t c_cflag )
{
unsigned8 smr ;
unsigned8 brr ;
uint8_t smr ;
uint8_t brr ;
if ( c_cflag & CBAUD )
{
@@ -108,7 +108,7 @@ static int _sci_set_cflags(
static void _sci_init(
rtems_device_minor_number minor )
{
unsigned16 temp16 ;
uint16_t temp16 ;
/* Pin function controller initialisation for asynchronous mode */
if( minor == 0)
@@ -146,7 +146,7 @@ static void _sci_tx_polled(
const char buf )
{
struct scidev_t *scidev = &sci_device[minor] ;
signed8 ssr ;
int8_t ssr ;
while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE ))
;
@@ -220,7 +220,7 @@ rtems_device_driver sh_sci_open(
rtems_device_minor_number minor,
void * arg )
{
unsigned8 temp8;
uint8_t temp8;
/* check for valid minor number */
if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))

12
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
View File

@@ -68,10 +68,10 @@ unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
unsigned32 shiftcount;
unsigned32 prioreg;
unsigned16 temp16;
unsigned32 level;
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
uint32_t level;
/*
* first check for valid interrupt
@@ -255,9 +255,9 @@ asm volatile(
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
void __ISR_Handler( uint32_t vector)
{
register unsigned32 level;
register uint32_t level;
_CPU_ISR_Disable( level );

16
c/src/lib/libcpu/sh/sh7032/timer/timer.c
View File

@@ -64,17 +64,17 @@
rtems_isr timerisr();
static rtems_unsigned32 Timer_interrupts;
static uint32_t Timer_interrupts;
rtems_boolean Timer_driver_Find_average_overhead;
static rtems_unsigned32 Timer_HZ ;
static uint32_t Timer_HZ ;
void Timer_initialize( void )
{
rtems_unsigned8 temp8;
rtems_unsigned16 temp16;
rtems_unsigned32 level;
uint8_t temp8;
uint16_t temp16;
uint32_t level;
rtems_isr *ignored;
Timer_HZ = rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE ;
@@ -149,8 +149,8 @@ void Timer_initialize( void )
int Read_timer( void )
{
rtems_unsigned32 cclicks;
rtems_unsigned32 total ;
uint32_t cclicks;
uint32_t total ;
/*
* Read the timer and see how many clicks it has been since we started.
*/
@@ -201,7 +201,7 @@ void Set_find_average_overhead(
#pragma interrupt
void timerisr( void )
{
unsigned8 temp8;
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK;

18
c/src/lib/libcpu/sh/sh7045/clock/ckinit.c
View File

@@ -71,11 +71,11 @@
* number of clock ticks since the driver was initialized.
*/
volatile rtems_unsigned32 Clock_driver_ticks;
volatile uint32_t Clock_driver_ticks;
static void Clock_exit( void );
static rtems_isr Clock_isr( rtems_vector_number vector );
static rtems_unsigned32 Clock_MHZ ;
static uint32_t Clock_MHZ ;
/*
* Clock_isrs is the number of clock ISRs until the next invocation of
@@ -85,8 +85,8 @@ static rtems_unsigned32 Clock_MHZ ;
* has passed.
*/
rtems_unsigned32 Clock_isrs; /* ISRs until next tick */
static rtems_unsigned32 Clock_isrs_const; /* only calculated once */
uint32_t Clock_isrs; /* ISRs until next tick */
static uint32_t Clock_isrs_const; /* only calculated once */
/*
* These are set by clock driver during its init
@@ -118,7 +118,7 @@ rtems_isr Clock_isr(
*
* perform any timer dependent tasks
*/
unsigned8 temp;
uint8_t temp;
/* reset the flags of the status register */
temp = read8( MTU_TSR0) & MTU0_STAT_MASK;
@@ -148,8 +148,8 @@ void Install_clock(
rtems_isr_entry clock_isr
)
{
unsigned8 temp8 = 0;
unsigned32 factor = 1000000;
uint8_t temp8 = 0;
uint32_t factor = 1000000;
/*
@@ -222,7 +222,7 @@ void Install_clock(
void Clock_exit( void )
{
unsigned8 temp8 = 0;
uint8_t temp8 = 0;
/* turn off the timer interrupts */
/* set interrupt priority to 0 */
@@ -271,7 +271,7 @@ rtems_device_driver Clock_control(
void *pargp
)
{
rtems_unsigned32 isrlevel;
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)

2
c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h
View File

@@ -43,7 +43,7 @@ extern "C" {
#include <rtems/score/types.h>
extern void __ISR_Handler( unsigned32 vector );
extern void __ISR_Handler( uint32_t vector );
/*

18
c/src/lib/libcpu/sh/sh7045/sci/sci.c
View File

@@ -78,7 +78,7 @@
struct scidev_t {
char * name ;
unsigned32 addr ;
uint32_t addr ;
rtems_device_minor_number minor ;
unsigned short opened ;
tcflag_t cflags ;
@@ -104,8 +104,8 @@ static int _sci_set_cflags(
struct scidev_t *sci_dev,
tcflag_t c_cflag )
{
unsigned8 smr ;
unsigned8 brr ;
uint8_t smr ;
uint8_t brr ;
if ( c_cflag & CBAUD )
{
@@ -150,7 +150,7 @@ static int _sci_set_cflags(
*/
rtems_boolean wrtSCI0(unsigned char ch)
{
unsigned8 temp;
uint8_t temp;
rtems_boolean result=FALSE;
if ((read8(SCI_SSR0) & SCI_TDRE) != 0x00) {
@@ -166,7 +166,7 @@ rtems_boolean wrtSCI0(unsigned char ch)
rtems_boolean wrtSCI1(unsigned char ch)
{
unsigned8 temp;
uint8_t temp;
rtems_boolean result=FALSE;
if ((read8(SCI_SSR1) & SCI_TDRE) != 0x00) {
@@ -203,7 +203,7 @@ void outbyte(
rtems_boolean rdSCI0(unsigned char *ch)
{
unsigned8 temp;
uint8_t temp;
rtems_boolean result=FALSE;
if ((read8(SCI_SSR0) & SCI_RDRF) != 0x00) {
@@ -227,7 +227,7 @@ rtems_boolean rdSCI0(unsigned char *ch)
rtems_boolean rdSCI1(unsigned char *ch)
{
unsigned8 temp;
uint8_t temp;
rtems_boolean result=FALSE;
if ((read8(SCI_SSR1) & SCI_RDRF) != 0x00) {
@@ -339,8 +339,8 @@ rtems_device_driver sh_sci_open(
rtems_device_minor_number minor,
void * arg )
{
unsigned8 temp8;
unsigned16 temp16;
uint8_t temp8;
uint16_t temp16;
unsigned a ;

12
c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c
View File

@@ -71,8 +71,8 @@ int sh_sci_set_attributes(
const struct termios *t
)
{
unsigned8 smr ;
unsigned8 brr ;
uint8_t smr ;
uint8_t brr ;
int a;
tcflag_t c_cflag = t->c_cflag;
@@ -135,7 +135,7 @@ rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
{
if(Console_Port_Tbl[minor].ulIntVector == vector)
{
unsigned8 temp8;
uint8_t temp8;
/*
* FIXME: error handling should be added
@@ -193,7 +193,7 @@ rtems_isr sh_sci_tx_isr(rtems_vector_number vector)
*/
void sh_sci_init(int minor)
{
unsigned16 temp16;
uint16_t temp16;
/*
* set PFC registers to enable I/O pins
@@ -285,7 +285,7 @@ int sh_sci_first_open(
int minor,
void *arg )
{
unsigned8 temp8;
uint8_t temp8;
unsigned int a ;
/*
@@ -439,7 +439,7 @@ void sh_sci_write_polled(
*/
int sh_sci_inbyte_nonblocking_polled(int minor)
{
unsigned8 inbyte;
uint8_t inbyte;
/*
* Check if input buffer is full

12
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
View File

@@ -67,10 +67,10 @@ unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
unsigned32 shiftcount;
unsigned32 prioreg;
unsigned16 temp16;
unsigned32 level;
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
uint32_t level;
/*
* first check for valid interrupt
@@ -257,9 +257,9 @@ __CPU_Context_restore:\n\
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
void __ISR_Handler( uint32_t vector)
{
register unsigned32 level;
register uint32_t level;
_CPU_ISR_Disable( level );

16
c/src/lib/libcpu/sh/sh7045/timer/timer.c
View File

@@ -55,17 +55,17 @@
rtems_isr timerisr();
static rtems_unsigned32 Timer_interrupts;
static uint32_t Timer_interrupts;
rtems_boolean Timer_driver_Find_average_overhead;
static rtems_unsigned32 Timer_MHZ ;
static uint32_t Timer_MHZ ;
void Timer_initialize( void )
{
rtems_unsigned8 temp8;
rtems_unsigned16 temp16;
rtems_unsigned32 level;
uint8_t temp8;
uint16_t temp16;
uint32_t level;
rtems_isr *ignored;
Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
@@ -145,8 +145,8 @@ void Timer_initialize( void )
int Read_timer( void )
{
rtems_unsigned32 clicks;
rtems_unsigned32 total ;
uint32_t clicks;
uint32_t total ;
/*
* Read the timer and see how many clicks it has been since we started.
*/
@@ -197,7 +197,7 @@ void Set_find_average_overhead(
#pragma interrupt
void timerisr( void )
{
unsigned8 temp8;
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK;

16
c/src/lib/libcpu/sh/sh7750/clock/ckinit.c
View File

@@ -44,7 +44,7 @@
* number of clock ticks since the driver was initialized.
*/
volatile rtems_unsigned32 Clock_driver_ticks;
volatile uint32_t Clock_driver_ticks;
static void Clock_exit( void );
static rtems_isr Clock_isr( rtems_vector_number vector );
@@ -77,7 +77,7 @@ rtems_isr_entry Old_ticker;
rtems_isr
Clock_isr(rtems_vector_number vector)
{
unsigned16 tcr;
uint16_t tcr;
/* reset the timer underflow flag */
tcr = read16(SH7750_TCR0);
@@ -108,9 +108,9 @@ Install_clock(rtems_isr_entry clock_isr)
{
int cpudiv = 1; /* CPU frequency divider */
int tidiv = 1; /* Timer input frequency divider */
unsigned32 timer_divider; /* Calculated Timer Divider value */
unsigned8 temp8;
unsigned16 temp16;
uint32_t timer_divider; /* Calculated Timer Divider value */
uint8_t temp8;
uint16_t temp16;
/*
* Initialize the clock tick device driver variables
@@ -236,8 +236,8 @@ Install_clock(rtems_isr_entry clock_isr)
void
Clock_exit(void)
{
unsigned8 temp8 = 0;
unsigned16 temp16 = 0;
uint8_t temp8 = 0;
uint16_t temp16 = 0;
/* turn off the timer interrupts */
/* Stop the Timer 0 */
@@ -296,7 +296,7 @@ Clock_control(rtems_device_major_number major,
rtems_device_minor_number minor,
void *pargp)
{
rtems_unsigned32 isrlevel;
uint32_t isrlevel;
rtems_libio_ioctl_args_t *args = pargp;
if (args != 0)

2
c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h
View File

@@ -50,7 +50,7 @@ extern "C" {
/* dummy ISP */
extern void _dummy_isp( void );
extern void __ISR_Handler( unsigned32 vector );
extern void __ISR_Handler( uint32_t vector );
/* This variable contains VBR value used to pass control when debug, error
* or virtual memory exceptions occured.

40
c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h
View File

@@ -35,35 +35,35 @@
/*
* Macros to call UART registers
*/
#define SCRDR(n) (*(volatile rtems_unsigned8 *)SH7750_SCRDR(n))
#define SCRDR(n) (*(volatile uint8_t *)SH7750_SCRDR(n))
#define SCRDR1 SCRDR(1)
#define SCRDR2 SCRDR(2)
#define SCTDR(n) (*(volatile rtems_unsigned8 *)SH7750_SCTDR(n))
#define SCTDR(n) (*(volatile uint8_t *)SH7750_SCTDR(n))
#define SCTDR1 SCTDR(1)
#define SCTDR2 SCTDR(2)
#define SCSMR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSMR1 : \
*(volatile rtems_unsigned16 *)SH7750_SCSMR2)
#define SCSMR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSMR1 : \
*(volatile uint16_t *)SH7750_SCSMR2)
#define SCSMR1 SCSMR(1)
#define SCSMR2 SCSMR(2)
#define SCSCR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSCR1 : \
*(volatile rtems_unsigned16 *)SH7750_SCSCR2)
#define SCSCR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSCR1 : \
*(volatile uint16_t *)SH7750_SCSCR2)
#define SCSCR1 SCSCR(1)
#define SCSCR2 SCSCR(2)
#define SCSSR(n) ((n) == 1 ? *(volatile rtems_unsigned8 *)SH7750_SCSSR1 : \
*(volatile rtems_unsigned16 *)SH7750_SCSSR2)
#define SCSSR(n) ((n) == 1 ? *(volatile uint8_t *)SH7750_SCSSR1 : \
*(volatile uint16_t *)SH7750_SCSSR2)
#define SCSSR1 SCSSR(1)
#define SCSSR2 SCSSR(2)
#define SCSPTR1 (*(volatile rtems_unsigned8 *)SH7750_SCSPTR1)
#define SCSPTR2 (*(volatile rtems_unsigned16 *)SH7750_SCSPTR2)
#define SCBRR(n) (*(volatile rtems_unsigned8 *)SH7750_SCBRR(n))
#define SCSPTR1 (*(volatile uint8_t *)SH7750_SCSPTR1)
#define SCSPTR2 (*(volatile uint16_t *)SH7750_SCSPTR2)
#define SCBRR(n) (*(volatile uint8_t *)SH7750_SCBRR(n))
#define SCBRR1 SCBRR(1)
#define SCBRR2 SCBRR(2)
#define SCFCR2 (*(volatile rtems_unsigned16 *)SH7750_SCFCR2)
#define SCFDR2 (*(volatile rtems_unsigned16 *)SH7750_SCFDR2)
#define SCLSR2 (*(volatile rtems_unsigned16 *)SH7750_SCLSR2)
#define SCFCR2 (*(volatile uint16_t *)SH7750_SCFCR2)
#define SCFDR2 (*(volatile uint16_t *)SH7750_SCFDR2)
#define SCLSR2 (*(volatile uint16_t *)SH7750_SCLSR2)
#define IPRB (*(volatile rtems_unsigned16 *)SH7750_IPRB)
#define IPRC (*(volatile rtems_unsigned16 *)SH7750_IPRC)
#define IPRB (*(volatile uint16_t *)SH7750_IPRB)
#define IPRC (*(volatile uint16_t *)SH7750_IPRC)
/*
* The following structure is a descriptor of single UART channel.
@@ -71,14 +71,14 @@
* current operating values
*/
typedef struct sh4uart {
rtems_unsigned8 chn; /* UART channel number */
rtems_unsigned8 int_driven; /* UART interrupt vector number, or
uint8_t chn; /* UART channel number */
uint8_t int_driven; /* UART interrupt vector number, or
0 if polled I/O */
void *tty; /* termios channel descriptor */
volatile const char *tx_buf; /* Transmit buffer from termios */
volatile rtems_unsigned32 tx_buf_len; /* Transmit buffer length */
volatile rtems_unsigned32 tx_ptr; /* Index of next char to transmit*/
volatile uint32_t tx_buf_len; /* Transmit buffer length */
volatile uint32_t tx_ptr; /* Index of next char to transmit*/
rtems_isr_entry old_handler_transmit; /* Saved interrupt handlers */
rtems_isr_entry old_handler_receive;

20
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
View File

@@ -80,11 +80,11 @@ sh4uart_init(sh4uart *uart, void *tty, int chn, int int_driven)
* RETURNS:
* peripheral module clock in Hz.
*/
rtems_unsigned32
uint32_t
sh4uart_get_Pph(void)
{
rtems_unsigned16 frqcr = *(volatile rtems_unsigned16 *)SH7750_FRQCR;
rtems_unsigned32 Pph = CPU_CLOCK_RATE_HZ;
uint16_t frqcr = *(volatile uint16_t *)SH7750_FRQCR;
uint32_t Pph = CPU_CLOCK_RATE_HZ;
switch (frqcr & SH7750_FRQCR_IFC)
{
@@ -161,10 +161,10 @@ sh4uart_get_Pph(void)
static void
sh4uart_set_baudrate(sh4uart *uart, speed_t baud)
{
rtems_unsigned32 rate;
rtems_signed16 div;
uint32_t rate;
int16_t div;
int n;
rtems_unsigned32 Pph = sh4uart_get_Pph();
uint32_t Pph = sh4uart_get_Pph();
switch (baud)
{
@@ -250,7 +250,7 @@ sh4uart_reset(sh4uart *uart)
if (int_driven)
{
rtems_unsigned16 ipr;
uint16_t ipr;
if (chn == SH4_SCI)
{
@@ -358,9 +358,9 @@ sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
{
int level;
speed_t baud;
rtems_unsigned16 smr;
uint16_t smr;
smr = (rtems_unsigned16)(*(rtems_unsigned8 *)SH7750_SCSMR(uart->chn));
smr = (uint16_t )(*(uint8_t *)SH7750_SCSMR(uart->chn));
baud = cfgetospeed(t);
@@ -403,7 +403,7 @@ sh4uart_set_attributes(sh4uart *uart, const struct termios *t)
SCSCR(uart->chn) &= ~(SH7750_SCSCR_TE | SH7750_SCSCR_RE);
sh4uart_set_baudrate(uart, baud);
SCSMR(uart->chn) = (rtems_unsigned8)smr;
SCSMR(uart->chn) = (uint8_t )smr;
/* enable operations */
SCSCR(uart->chn) |= SH7750_SCSCR_TE | SH7750_SCSCR_RE;

4
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
View File

@@ -254,9 +254,9 @@ __CPU_Context_restore:\n\
* This routine provides the RTEMS interrupt management.
*/
void __ISR_Handler( unsigned32 vector)
void __ISR_Handler( uint32_t vector)
{
register unsigned32 level;
register uint32_t level;
_CPU_ISR_Disable( level );

2
c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c
View File

@@ -72,7 +72,7 @@ void *_VBR_Saved;
*
*/
void _CPU_ISR_install_vector(
unsigned32 vector,
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)

20
c/src/lib/libcpu/sh/sh7750/timer/timer.c
View File

@@ -39,13 +39,13 @@
rtems_isr timerisr();
static rtems_unsigned32 Timer_interrupts;
static uint32_t Timer_interrupts;
/* Counter should be divided to this value to obtain time in microseconds */
static rtems_unsigned32 microseconds_divider;
static uint32_t microseconds_divider;
/* Interrupt period in microseconds */
static rtems_unsigned32 microseconds_per_int;
static uint32_t microseconds_per_int;
rtems_boolean Timer_driver_Find_average_overhead;
@@ -65,8 +65,8 @@ rtems_boolean Timer_driver_Find_average_overhead;
void
Timer_initialize(void)
{
rtems_unsigned8 temp8;
rtems_unsigned16 temp16;
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
int cpudiv = 1;
@@ -203,11 +203,11 @@ Timer_initialize(void)
int
Read_timer(void)
{
rtems_unsigned32 clicks;
rtems_unsigned32 ints;
rtems_unsigned32 total ;
uint32_t clicks;
uint32_t ints;
uint32_t total ;
rtems_interrupt_level level;
rtems_unsigned32 tcr;
uint32_t tcr;
_CPU_ISR_Disable(level);
@@ -281,7 +281,7 @@ Set_find_average_overhead(rtems_boolean find_flag)
void
timerisr(void)
{
unsigned8 temp8;
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF;