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2007-09-06 Daniel Hellstrom <daniel@gaisler.com>

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* Makefile.am: Add the following new drivers: PCI, b1553BRM,
	SpaceWire(GRSPW), CAN (GRCAN,OC_CAN), Raw UART.
	* shared/include/apbuart.h, shared/include/apbuart_pci.h,
	shared/include/apbuart_rasta.h, shared/include/b1553brm.h,
	shared/include/b1553brm_pci.h, shared/include/b1553brm_rasta.h,
	shared/include/debug_defs.h, shared/include/grcan.h,
	shared/include/grcan_rasta.h, shared/include/grcan_spwrtc.h,
	shared/include/grspw.h, shared/include/grspw_pci.h,
	shared/include/grspw_rasta.h, shared/include/occan.h,
	shared/include/occan_pci.h, shared/include/pci.h: New files.
This commit is contained in:
Joel Sherrill
2007-09-06 13:25:42 +00:00
parent ce40d306b3
commit e16e0caf72
18 changed files with 2402 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
c/src/lib/libbsp/sparc/ChangeLog
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@@ -1,3 +1,17 @@
2007-09-06 Daniel Hellstrom <daniel@gaisler.com>
* Makefile.am: Add the following new drivers: PCI, b1553BRM,
SpaceWire(GRSPW), CAN (GRCAN,OC_CAN), Raw UART.
* shared/include/apbuart.h, shared/include/apbuart_pci.h,
shared/include/apbuart_rasta.h, shared/include/b1553brm.h,
shared/include/b1553brm_pci.h, shared/include/b1553brm_rasta.h,
shared/include/debug_defs.h, shared/include/grcan.h,
shared/include/grcan_rasta.h, shared/include/grcan_spwrtc.h,
shared/include/grspw.h, shared/include/grspw_pci.h,
shared/include/grspw_rasta.h, shared/include/occan.h,
shared/include/occan_pci.h, shared/include/pci.h: New files.
2007-09-05 Daniel Hellstrom <daniel@gaisler.com>
* shared/bspstart.c: LEON2 and LEON3 Data cache snooping detection on

41
c/src/lib/libbsp/sparc/Makefile.am
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@@ -18,5 +18,46 @@ EXTRA_DIST += shared/start.S
EXTRA_DIST += shared/include/ambapp.h
EXTRA_DIST += shared/amba/ambapp.c
# PCI bus
EXTRA_DIST += shared/include/pci.h
EXTRA_DIST += shared/pci/pcifinddevice.c
# DEBUG
EXTRA_DIST += shared/include/debug_defs.h
# SpaceWire (GRSPW)
EXTRA_DIST += shared/spw/grspw.c
EXTRA_DIST += shared/spw/grspw_pci.c
EXTRA_DIST += shared/spw/grspw_rasta.c
EXTRA_DIST += shared/include/grspw.h
EXTRA_DIST += shared/include/grspw_pci.h
EXTRA_DIST += shared/include/grspw_rasta.h
# UART (APBUART)
EXTRA_DIST += shared/uart/apbuart.c
EXTRA_DIST += shared/uart/apbuart_pci.c
EXTRA_DIST += shared/uart/apbuart_rasta.c
EXTRA_DIST += shared/include/apbuart.h
EXTRA_DIST += shared/include/apbuart_pci.h
EXTRA_DIST += shared/include/apbuart_rasta.h
# CAN (OC_CAN, GRCAN)
EXTRA_DIST += shared/can/occan.c
EXTRA_DIST += shared/can/occan_pci.c
EXTRA_DIST += shared/can/grcan.c
EXTRA_DIST += shared/can/grcan_rasta.c
EXTRA_DIST += shared/include/occan.h
EXTRA_DIST += shared/include/occan_pci.h
EXTRA_DIST += shared/include/grcan.h
EXTRA_DIST += shared/include/grcan_rasta.h
# MIL-STD-B1553 (Core1553BRM)
EXTRA_DIST += shared/1553/b1553brm.c
EXTRA_DIST += shared/1553/b1553brm_pci.c
EXTRA_DIST += shared/1553/b1553brm_rasta.c
EXTRA_DIST += shared/include/b1553brm.h
EXTRA_DIST += shared/include/b1553brm_pci.h
EXTRA_DIST += shared/include/b1553brm_rasta.h
include $(top_srcdir)/../../../automake/subdirs.am
include $(top_srcdir)/../../../automake/local.am

83
c/src/lib/libbsp/sparc/shared/include/apbuart.h Normal file
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@@ -0,0 +1,83 @@
/*
* Driver interface for APBUART
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __APBUART_H__
#define __APBUART_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
unsigned int hw_dovr;
unsigned int hw_parity;
unsigned int hw_frame;
unsigned int sw_dovr;
unsigned int rx_cnt;
unsigned int tx_cnt;
} apbuart_stats;
#define APBUART_START 0
#define APBUART_STOP 1
#define APBUART_SET_RXFIFO_LEN 2
#define APBUART_SET_TXFIFO_LEN 3
#define APBUART_SET_BAUDRATE 4
#define APBUART_SET_SCALER 5
#define APBUART_SET_BLOCKING 6
#define APBUART_SET_ASCII_MODE 7
#define APBUART_GET_STATS 16
#define APBUART_CLR_STATS 17
#define APBUART_BLK_RX 0x1
#define APBUART_BLK_TX 0x2
#define APBUART_BLK_FLUSH 0x4
#define APBUART_CTRL_RE 0x1
#define APBUART_CTRL_TE 0x2
#define APBUART_CTRL_RI 0x4
#define APBUART_CTRL_TI 0x8
#define APBUART_CTRL_PS 0x10
#define APBUART_CTRL_PE 0x20
#define APBUART_CTRL_FL 0x40
#define APBUART_CTRL_LB 0x80
#define APBUART_CTRL_EC 0x100
#define APBUART_CTRL_TF 0x200
#define APBUART_CTRL_RF 0x400
#define APBUART_STATUS_DR 0x1
#define APBUART_STATUS_TS 0x2
#define APBUART_STATUS_TE 0x4
#define APBUART_STATUS_BR 0x8
#define APBUART_STATUS_OV 0x10
#define APBUART_STATUS_PE 0x20
#define APBUART_STATUS_FE 0x40
#define APBUART_STATUS_TH 0x80
#define APBUART_STATUS_RH 0x100
#define APBUART_STATUS_TF 0x200
#define APBUART_STATUS_RF 0x400
/* Register APBUART driver
* bus = pointer to AMBA bus description used to search for APBUART(s).
* (&amba_conf for LEON3), (LEON2: see amba_scan)
*/
int apbuart_register (amba_confarea_type * bus);
#ifdef __cplusplus
}
#endif
#endif /* __APBUART_H__ */

43
c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h Normal file
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@@ -0,0 +1,43 @@
/*
* APBUART via PCI - driver interface
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __APBUART_PCI_H__
#define __APBUART_PCI_H__
#include <apbuart.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register APBUART driver, if APBUART devices are found.
* bus = pointer to AMBA bus description used to search for APBUART(s).
*
*/
int apbuart_pci_register (amba_confarea_type * bus);
/* This function must be called on APBUART interrupt. Called from the
* PCI interrupt handler.
* irq = AMBA IRQ assigned to the APBUART device, is found by reading
* pending register on IRQMP connected to the APBUART device.
*
*/
void apbuartpci_interrupt_handler (int irq, void *arg);
extern void (*apbuart_pci_int_reg) (void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __APBUART_PCI_H__ */

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c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h Normal file
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@@ -0,0 +1,43 @@
/*
* APBUART RASTA via PCI - driver interface
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __APBUART_RASTA_H__
#define __APBUART_RASTA_H__
#include <apbuart.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register APBUART driver, if APBUART devices are found.
* bus = pointer to AMBA bus description used to search for APBUART(s).
*
*/
int apbuart_rasta_register(amba_confarea_type *bus);
/* This function must be called on APBUART interrupt. Called from the
* RASTA interrupt handler.
* irq = AMBA IRQ assigned to the APBUART device, is found by reading
* pending register on IRQMP connected to the APBUART device.
*
*/
void apbuartrasta_interrupt_handler(int irq, void *arg);
extern void (*apbuart_rasta_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __APBUART_RASTA_H__ */

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c/src/lib/libbsp/sparc/shared/include/b1553brm.h Normal file
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@@ -0,0 +1,169 @@
/*
* Macros used for brm controller
*
* COPYRIGHT (c) 2006.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __B1553BRM_H__
#define __B1553BRM_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
struct brm_reg {
volatile unsigned int ctrl; /* 0x00 */
volatile unsigned int oper; /* 0x04 */
volatile unsigned int cur_cmd; /* 0x08 */
volatile unsigned int imask; /* 0x0C */
volatile unsigned int ipend; /* 0x10 */
volatile unsigned int ipoint; /* 0x14 */
volatile unsigned int bit_reg; /* 0x18 */
volatile unsigned int ttag; /* 0x1C */
volatile unsigned int dpoint; /* 0x20 */
volatile unsigned int sw; /* 0x24 */
volatile unsigned int initcount; /* 0x28 */
volatile unsigned int mcpoint; /* 0x2C */
volatile unsigned int mdpoint; /* 0x30 */
volatile unsigned int mbc; /* 0x34 */
volatile unsigned int mfilta; /* 0x38 */
volatile unsigned int mfiltb; /* 0x3C */
volatile unsigned int rt_cmd_leg[16]; /* 0x40-0x80 */
volatile unsigned int enhanced; /* 0x84 */
volatile unsigned int dummy[31];
volatile unsigned int w_ctrl; /* 0x100 */
volatile unsigned int w_irqctrl; /* 0x104 */
volatile unsigned int w_ahbaddr; /* 0x108 */
};
struct bm_msg {
unsigned short miw;
unsigned short cw1;
unsigned short cw2;
unsigned short sw1;
unsigned short sw2;
unsigned short time;
unsigned short data[32];
};
struct rt_msg {
unsigned short miw;
unsigned short time;
unsigned short data[32];
unsigned short desc;
};
/*
* rtaddr[0] and subaddr[0] : RT address and subaddress (for rt-rt receive addresses)
* rtaddr[1] and subaddr[1] : Only for RT-RT. Transmit addresses.
*
* wc : word count, or mode code if subaddress 0 or 31.
*
* ctrl, bit 0 (TR) : 1 - transmit, 0 - receive. Ignored for rt-rt
* bit 1 (RTRT) : 1 - rt to rt, 0 - normal
* bit 2 (AB) : 1 - Bus B, 0 - Bus A
* bit 4:3 (Retry) : 1 - 1, 2 - 2, 3 - 3, 0 - 4
* bit 5 (END) : End of list
* bit 15 (BAME) : Message error. Set by BRM if protocol error is detected
*
* tsw[0] : status word
* tsw[1] : Only for rt-rt, status word 2
*
* data : data to be transmitted, or received data
*
*/
struct bc_msg {
unsigned char rtaddr[2];
unsigned char subaddr[2];
unsigned short wc;
unsigned short ctrl;
unsigned short tsw[2];
unsigned short data[32];
};
/* BC control bits */
#define BC_TR 0x0001
#define BC_RTRT 0x0002
#define BC_BUSA 0x0004
#define BC_EOL 0x0020
#define BC_BAME 0x8000
#define BRM_MBC_IRQ 1 /* Monitor Block Counter irq */
#define BRM_CBA_IRQ 2 /* Command Block Accessed irq */
#define BRM_RTF_IRQ 4 /* Retry Fail irq */
#define BRM_ILLOP_IRQ 8 /* Illogical Opcode irq */
#define BRM_BC_ILLCMD_IRQ 16 /* BC Illocigal Command irq */
#define BRM_EOL_IRQ 32 /* End Of List irq */
#define BRM_RT_ILLCMD_IRQ 128 /* RT Illegal Command irq */
#define BRM_IXEQ0_IRQ 256 /* Index Equal Zero irq */
#define BRM_BDRCV_IRQ 512 /* Broadcast Command Received irq */
#define BRM_SUBAD_IRQ 1024 /* Subaddress Accessed irq */
#define BRM_MERR_IRQ 4096 /* Message Error irq */
#define BRM_TAPF_IRQ 8192 /* Terminal Address Parity Fail irq */
#define BRM_WRAPF_IRQ 16384 /* Wrap Fail irq */
#define BRM_DMAF_IRQ 32768 /* DMA Fail irq */
#define BRM_SET_MODE 0
#define BRM_SET_BUS 1
#define BRM_SET_MSGTO 2
#define BRM_SET_RT_ADDR 3
#define BRM_SET_STD 4
#define BRM_SET_BCE 5
#define BRM_TX_BLOCK 7
#define BRM_RX_BLOCK 8
#define BRM_DO_LIST 10
#define BRM_LIST_DONE 11
#define BRM_CLR_STATUS 12
#define BRM_GET_STATUS 13
#define BRM_SET_EVENTID 14
#define GET_ERROR_DESCRIPTOR(event_in) (event_in>>16)
#define BRM_MODE_BC 0x0
#define BRM_MODE_RT 0x1
#define BRM_MODE_BM 0x2
#define BRM_MODE_BM_RT 0x3 /* both RT and BM */
/* Register RAMON FPGA BRM driver, calls brm_register */
int brm_register_leon3_ramon_fpga(void);
/* Register RAMON ASIC BRM driver, calls brm_register */
int brm_register_leon3_ramon_asic(void);
#define BRM_FREQ_12MHZ 0
#define BRM_FREQ_16MHZ 1
#define BRM_FREQ_20MHZ 2
#define BRM_FREQ_24MHZ 3
#define BRM_FREQ_MASK 0x3
#define CLKDIV_MASK 0xf
#define CLKSEL_MASK 0x7
/* Register BRM driver
* See (struct brm_reg).w_ctrl for clksel and clkdiv.
* See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
* bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver)
*/
int b1553brm_register(amba_confarea_type *bus, unsigned int clksel, unsigned int clkdiv, unsigned int brm_freq);
#ifdef __cplusplus
}
#endif
#endif /* __BRM_H__ */

57
c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h Normal file
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@@ -0,0 +1,57 @@
/*
* Macros used for brm controller
*
* COPYRIGHT (c) 2006.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __B1553BRM_PCI_H__
#define __B1553BRM_PCI_H__
#include <b1553brm.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register BRM driver
* See (struct brm_reg).w_ctrl for clksel and clkdiv.
* See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
* bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver)
*
* Memory setup:
* memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
* hw_address = address that HW must use to access memarea. (used in the translation process)
*/
int b1553brm_pci_register(
amba_confarea_type *bus,
unsigned int clksel,
unsigned int clkdiv,
unsigned int brm_freq,
unsigned int memarea,
unsigned int hw_address
);
/* This function must be called on BRM interrupt. Called from the
* PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
* is found by reading pending register on IRQMP connected to BRM
* device.
*
* Return 0=not handled. nono-zero=handled
*/
int b1553brm_pci_interrupt_handler(int irq, void *arg);
extern void (*b1553brm_pci_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __B1553BRM_PCI_H__ */

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c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h Normal file
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@@ -0,0 +1,57 @@
/*
* Macros used for brm controller
*
* COPYRIGHT (c) 2006.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __B1553BRM_RASTA_H__
#define __B1553BRM_RASTA_H__
#include <b1553brm.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register BRM driver
* See (struct brm_reg).w_ctrl for clksel and clkdiv.
* See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
* bus = &amba_conf for LEON3. (LEON2 not yet supported for this driver)
*
* Memory setup:
* memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
* hw_address = address that HW must use to access memarea. (used in the translation process)
*/
int b1553brm_rasta_register(
amba_confarea_type *bus,
unsigned int clksel,
unsigned int clkdiv,
unsigned int brm_freq,
unsigned int memarea,
unsigned int hw_address
);
/* This function must be called on BRM interrupt. Called from the
* PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
* is found by reading pending register on IRQMP connected to BRM
* device.
*
* Return 0=not handled. nono-zero=handled
*/
int b1553brm_rasta_interrupt_handler(int irq, void *arg);
extern void (*b1553brm_rasta_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __B1553BRM_RASTA_H__ */

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c/src/lib/libbsp/sparc/shared/include/debug_defs.h Normal file
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#ifndef __DEBUG_DEFS_H__
#define __DEBUG_DEFS_H__
#ifdef __cplusplus
extern "C" {
#endif
#ifdef DEBUG
#ifndef DEBUG_FLAGS
#define DEBUG_FLAGS 0
#endif
extern int DEBUG_printf(const char *fmt, ...);
#define DBG(fmt, args...) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); } while(0)
#define DBG2(fmt) do { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__); } while(0)
#define DBGC(c,fmt, args...) do { if (DEBUG_FLAGS & c) { printk(" : %03d @ %18s()]:" fmt , __LINE__,__FUNCTION__,## args); }} while(0)
#else
#define DBG(fmt, args...)
#define DBG2(fmt, args...)
#define DBGC(c, fmt, args...)
#endif
#ifdef DEBUGFUNCS
#define FUNCDBG() do { printk("%s\n\r",__FUNCTION__); } while(0)
extern int DEBUG_printf(const char *fmt, ...);
#else
#define FUNCDBG()
#endif
#ifdef __cplusplus
}
#endif
#endif /* __DEBUG_DEFS_H__ */

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c/src/lib/libbsp/sparc/shared/include/grcan.h Normal file
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/*
* Macros used for grcan controller
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __GRCAN_H__
#define __GRCAN_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
struct grcan_regs {
volatile unsigned int conf; /* 0x00 */
volatile unsigned int stat; /* 0x04 */
volatile unsigned int ctrl; /* 0x08 */
volatile unsigned int dummy0[3]; /* 0x0C-0x014 */
volatile unsigned int smask; /* 0x18 */
volatile unsigned int scode; /* 0x1C */
volatile unsigned int dummy1[56]; /* 0x20-0xFC */
volatile unsigned int pimsr; /* 0x100 */
volatile unsigned int pimr; /* 0x104 */
volatile unsigned int pisr; /* 0x108 */
volatile unsigned int pir; /* 0x10C */
volatile unsigned int imr; /* 0x110 */
volatile unsigned int picr; /* 0x114 */
volatile unsigned int dummy2[58]; /* 0x118-0x1FC */
volatile unsigned int tx0ctrl; /* 0x200 */
volatile unsigned int tx0addr; /* 0x204 */
volatile unsigned int tx0size; /* 0x208 */
volatile unsigned int tx0wr; /* 0x20C */
volatile unsigned int tx0rd; /* 0x210 */
volatile unsigned int tx0irq; /* 0x214 */
volatile unsigned int dummy3[58]; /* 0x218-0x2FC */
volatile unsigned int rx0ctrl; /* 0x300 */
volatile unsigned int rx0addr; /* 0x304 */
volatile unsigned int rx0size; /* 0x308 */
volatile unsigned int rx0wr; /* 0x30C */
volatile unsigned int rx0rd; /* 0x310 */
volatile unsigned int rx0irq; /* 0x314 */
volatile unsigned int rx0mask; /* 0x318 */
volatile unsigned int rx0code; /* 0x31C */
};
struct grcan_stats {
unsigned int passive_cnt;
unsigned int overrun_cnt;
unsigned int rxsync_cnt;
unsigned int txsync_cnt;
unsigned int txloss_cnt;
unsigned int ahberr_cnt;
unsigned int ints;
};
struct grcan_timing {
unsigned char scaler;
unsigned char ps1;
unsigned char ps2;
unsigned int rsj;
unsigned char bpr;
};
struct grcan_selection {
int selection;
int enable0;
int enable1;
};
struct grcan_filter {
unsigned long long mask;
unsigned long long code;
};
/* CAN MESSAGE */
typedef struct {
char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */
char rtr; /* RTR - Remote Transmission Request */
char unused; /* unused */
unsigned char len;
unsigned char data[8];
unsigned int id;
} CANMsg;
#define GRCAN_CFG_ABORT 0x00000001
#define GRCAN_CFG_ENABLE0 0x00000002
#define GRCAN_CFG_ENABLE1 0x00000004
#define GRCAN_CFG_SELECTION 0x00000008
#define GRCAN_CFG_SILENT 0x00000010
#define GRCAN_CFG_BPR 0x00000300
#define GRCAN_CFG_RSJ 0x00007000
#define GRCAN_CFG_PS1 0x00f00000
#define GRCAN_CFG_PS2 0x000f0000
#define GRCAN_CFG_SCALER 0xff000000
#define GRCAN_CFG_BPR_BIT 8
#define GRCAN_CFG_RSJ_BIT 12
#define GRCAN_CFG_PS1_BIT 20
#define GRCAN_CFG_PS2_BIT 16
#define GRCAN_CFG_SCALER_BIT 24
#define GRCAN_CTRL_RESET 0x2
#define GRCAN_CTRL_ENABLE 0x1
#define GRCAN_TXCTRL_ENABLE 1
#define GRCAN_TXCTRL_ONGOING 1
#define GRCAN_RXCTRL_ENABLE 1
#define GRCAN_RXCTRL_ONGOING 1
/* Relative offset of IRQ sources to AMBA Plug&Play */
#define GRCAN_IRQ_IRQ 0
#define GRCAN_IRQ_TXSYNC 1
#define GRCAN_IRQ_RXSYNC 2
#define GRCAN_ERR_IRQ 0x1
#define GRCAN_OFF_IRQ 0x2
#define GRCAN_OR_IRQ 0x4
#define GRCAN_RXAHBERR_IRQ 0x8
#define GRCAN_TXAHBERR_IRQ 0x10
#define GRCAN_RXIRQ_IRQ 0x20
#define GRCAN_TXIRQ_IRQ 0x40
#define GRCAN_RXFULL_IRQ 0x80
#define GRCAN_TXEMPTY_IRQ 0x100
#define GRCAN_RX_IRQ 0x200
#define GRCAN_TX_IRQ 0x400
#define GRCAN_RXSYNC_IRQ 0x800
#define GRCAN_TXSYNC_IRQ 0x1000
#define GRCAN_RXERR_IRQ 0x2000
#define GRCAN_TXERR_IRQ 0x4000
#define GRCAN_RXMISS_IRQ 0x8000
#define GRCAN_TXLOSS_IRQ 0x10000
#define GRCAN_STAT_PASS 0x1
#define GRCAN_STAT_OFF 0x2
#define GRCAN_STAT_OR 0x4
#define GRCAN_STAT_AHBERR 0x8
#define GRCAN_STAT_ACTIVE 0x10
#define GRCAN_STAT_RXERRCNT 0xff00
#define GRCAN_STAT_TXERRCNT 0xff0000
/* IOCTL Commands controlling operational
* mode
*/
#define GRCAN_IOC_START 1 /* Bring the link up after open or bus-off */
#define GRCAN_IOC_STOP 2 /* stop to change baud rate/config or closing down */
#define GRCAN_IOC_ISSTARTED 3 /* return RTEMS_SUCCESSFUL when started, othervise EBUSY */
#define GRCAN_IOC_FLUSH 4 /* Waits until all TX messages has been sent */
/* IOCTL Commands that require connection
* to be stopped
*/
#define GRCAN_IOC_SET_SILENT 16 /* enable silent mode read only state */
#define GRCAN_IOC_SET_ABORT 17 /* enable/disable stopping link on AHB Error */
#define GRCAN_IOC_SET_SELECTION 18 /* Set Enable0,Enable1,Selection */
#define GRCAN_IOC_SET_SPEED 19 /* Set baudrate by using driver's baud rate timing calculation routines */
#define GRCAN_IOC_SET_BTRS 20 /* Set baudrate by specifying the timing registers manually */
/* IOCTL Commands can be called whenever */
#define GRCAN_IOC_SET_RXBLOCK 32 /* Enable/disable Blocking on reception (until at least one message has been received) */
#define GRCAN_IOC_SET_TXBLOCK 33 /* Enable/disable Blocking on transmission (until at least one message has been transmitted) */
#define GRCAN_IOC_SET_TXCOMPLETE 34 /* Enable/disable Blocking until all requested messages has been sent */
#define GRCAN_IOC_SET_RXCOMPLETE 35 /* Enable/disable Blocking until all requested has been received */
#define GRCAN_IOC_GET_STATS 36 /* Get Statistics */
#define GRCAN_IOC_CLR_STATS 37 /* Clear Statistics */
#define GRCAN_IOC_SET_AFILTER 38 /* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */
#define GRCAN_IOC_SET_SFILTER 40 /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */
#define GRCAN_IOC_GET_STATUS 41 /* Get status register of GRCAN core */
struct grcan_device_info {
unsigned int base_address;
int irq;
};
/* Use hard coded addresses and IRQs to find hardware */
int grcan_register_abs(struct grcan_device_info *devices, int dev_cnt);
/* Use prescanned AMBA Plug&Play information to find all GRFIFO cores */
int grcan_register(amba_confarea_type *abus);
#if 0
void grcan_register(unsigned int baseaddr, unsigned int ram_base);
void grcan_interrupt_handler(rtems_vector_number v);
#endif
#ifdef __cplusplus
}
#endif
#endif

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c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h Normal file
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#ifndef __GRCAN_RASTA_H__
#define __GRCAN_RASTA_H__
#include <grcan.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Registers the GRCAN for RASTA
*
* rambase is address of the first GRCAN core has it's TX buffer, followed by
* it's RX buffer
*/
int grcan_rasta_ram_register(amba_confarea_type *abus, int rambase);
extern void (*grcan_rasta_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif

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c/src/lib/libbsp/sparc/shared/include/grcan_spwrtc.h Normal file
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#ifndef __GRCAN_SPWRTC_H__
#define __GRCAN_SPWRTC_H__
#include <grcan.h>
/* Registers the GRCAN for SPW-RTC */
#endif

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/*
* Macros used for Spacewire bus
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef __GRSPW_H__
#define __GRSPW_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
#define SPW_LINKERR_EVENT RTEMS_EVENT_0
typedef struct {
unsigned int rxsize;
unsigned int txdsize;
unsigned int txhsize;
} spw_ioctl_packetsize;
typedef struct {
unsigned int hlen;
char *hdr;
unsigned int dlen;
char *data;
unsigned int sent;
} spw_ioctl_pkt_send;
typedef struct {
unsigned int tx_link_err;
unsigned int rx_rmap_header_crc_err;
unsigned int rx_rmap_data_crc_err;
unsigned int rx_eep_err;
unsigned int rx_truncated;
unsigned int parity_err;
unsigned int escape_err;
unsigned int credit_err;
unsigned int write_sync_err;
unsigned int disconnect_err;
unsigned int early_ep;
unsigned int invalid_address;
unsigned int packets_sent;
unsigned int packets_received;
} spw_stats;
typedef struct {
unsigned int nodeaddr;
unsigned int destkey;
unsigned int clkdiv;
unsigned int rxmaxlen;
unsigned int timer;
unsigned int disconnect;
unsigned int promiscuous;
unsigned int rmapen;
unsigned int rmapbufdis;
unsigned int linkdisabled;
unsigned int linkstart;
unsigned int check_rmap_err; /* check incoming packets for rmap errors */
unsigned int rm_prot_id; /* remove protocol id from incoming packets */
unsigned int tx_blocking; /* use blocking tx */
unsigned int tx_block_on_full; /* block when all tx_buffers are used */
unsigned int rx_blocking; /* block when no data is available */
unsigned int disable_err; /* disable link automatically when link error is detected */
unsigned int link_err_irq; /* generate an interrupt when link error occurs */
rtems_id event_id; /* task id that should receive link err irq event */
unsigned int is_rmap;
unsigned int is_rxunaligned;
unsigned int is_rmapcrc;
} spw_config;
#define SPACEWIRE_IOCTRL_SET_NODEADDR 1
#define SPACEWIRE_IOCTRL_SET_RXBLOCK 2
#define SPACEWIRE_IOCTRL_SET_DESTKEY 4
#define SPACEWIRE_IOCTRL_SET_CLKDIV 5
#define SPACEWIRE_IOCTRL_SET_TIMER 6
#define SPACEWIRE_IOCTRL_SET_DISCONNECT 7
#define SPACEWIRE_IOCTRL_SET_PROMISCUOUS 8
#define SPACEWIRE_IOCTRL_SET_RMAPEN 9
#define SPACEWIRE_IOCTRL_SET_RMAPBUFDIS 10
#define SPACEWIRE_IOCTRL_SET_CHECK_RMAP 11
#define SPACEWIRE_IOCTRL_SET_RM_PROT_ID 12
#define SPACEWIRE_IOCTRL_SET_TXBLOCK 14
#define SPACEWIRE_IOCTRL_SET_DISABLE_ERR 15
#define SPACEWIRE_IOCTRL_SET_LINK_ERR_IRQ 16
#define SPACEWIRE_IOCTRL_SET_EVENT_ID 17
#define SPACEWIRE_IOCTRL_SET_PACKETSIZE 20
#define SPACEWIRE_IOCTRL_GET_LINK_STATUS 23
#define SPACEWIRE_IOCTRL_GET_CONFIG 25
#define SPACEWIRE_IOCTRL_GET_STATISTICS 26
#define SPACEWIRE_IOCTRL_CLR_STATISTICS 27
#define SPACEWIRE_IOCTRL_SEND 28
#define SPACEWIRE_IOCTRL_LINKDISABLE 29
#define SPACEWIRE_IOCTRL_LINKSTART 30
#define SPACEWIRE_IOCTRL_SET_TXBLOCK_ON_FULL 31
#define SPACEWIRE_IOCTRL_SET_COREFREQ 32
#define SPACEWIRE_IOCTRL_START 64
#define SPACEWIRE_IOCTRL_STOP 65
int grspw_register(amba_confarea_type *bus);
#if 0
struct grspw_buf;
struct grspw_buf {
grspw_buf *next; /* next packet in chain */
/* Always used */
unsigned int dlen; /* data length of '*data' */
unsigned int max_dlen; /* allocated length of '*data' */
void *data; /* pointer to beginning of cargo data */
/* Only used when transmitting */
unsigned int hlen; /* length of header '*header' */
unsigned int max_hlen; /* allocated length of '*header' */
void *header; /* pointer to beginning of header data */
};
#endif
#ifdef __cplusplus
}
#endif
#endif /* __GRSPW_H__ */

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c/src/lib/libbsp/sparc/shared/include/grspw_pci.h Normal file
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/*
* Macros used for GRSPW controller
*
* COPYRIGHT (c) 2006.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __GRSPW_PCI_H__
#define __GRSPW_PCI_H__
#include <grspw.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register GRSPW Driver
* bus = &amba_conf for LEON3
*
* Memory setup:
* memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
* hw_address = address that HW must use to access memarea. (used in the translation process)
*/
int grspw_pci_register (amba_confarea_type * bus,
unsigned int memarea, unsigned int hw_address);
/* This function must be called on BRM interrupt. Called from the
* PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
* is found by reading pending register on IRQMP connected to BRM
* device.
*
* Return 0=not handled. nono-zero=handled
*/
unsigned int grspw_pci_interrupt_handler (int irq, void *arg);
extern void (*grspw_pci_int_reg) (void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __GRSPW_PCI_H__ */

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c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h Normal file
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/*
* Macros used for RASTA PCI GRSPW controller
*
* COPYRIGHT (c) 2006.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __GRSPW_RASTA_H__
#define __GRSPW_RASTA_H__
#include <grspw.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register GRSPW Driver
* bus = &amba_conf for LEON3
*
* Memory setup:
* ram_base = 128k aligned pointer to memory (as the CPU sees it)
*/
int grspw_rasta_register(
amba_confarea_type *bus,
unsigned int ram_base
);
/* This function must be called on GRSPW interrupt. Called from the
* PCI interrupt handler. irq = AMBA IRQ MASK assigned to the GRSPW device,
* is found by reading pending register on IRQMP connected to GRSPW
* device.
*
*/
void grspw_rasta_interrupt_handler(unsigned int status);
/* callback to register interrupt handler */
extern void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __GRSPW_RASTA_PCI_H__ */

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c/src/lib/libbsp/sparc/shared/include/occan.h Normal file
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/* Gaisler wrapper to OpenCores CAN, driver interface
*
* COPYRIGHT (c) 2007.
* Gaisler Research.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* Author: Daniel Hellstr<74>m, Gaisler Research AB, www.gaisler.com
*/
#ifndef __OCCAN_H__
#define __OCCAN_H__
#include <ambapp.h>
#ifdef __cplusplus
extern "C" {
#endif
/* CAN MESSAGE */
typedef struct {
char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */
char rtr; /* RTR - Remote Transmission Request */
char sshot; /* single shot */
unsigned char len;
unsigned char data[8];
unsigned int id;
} CANMsg;
typedef struct {
/* tx/rx stats */
unsigned int rx_msgs;
unsigned int tx_msgs;
/* Error Interrupt counters */
unsigned int err_warn;
unsigned int err_dovr;
unsigned int err_errp;
unsigned int err_arb;
unsigned int err_bus;
/**** BUS ERRORS (err_arb) ****/
/* ALC 4-0 */
unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */
/******************************/
/**** BUS ERRORS (err_bus) ****/
/* ECC 7-6 */
unsigned int err_bus_bit; /* Bit error */
unsigned int err_bus_form; /* Form Error */
unsigned int err_bus_stuff; /* Stuff Error */
unsigned int err_bus_other; /* Other Error */
/* ECC 5 */
unsigned int err_bus_rx; /* Errors during Reception */
unsigned int err_bus_tx; /* Errors during Transmission */
/* ECC 4:0 */
unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured)
* See OCCAN_SEG_* defines for indexes
*/
/******************************/
/* total number of interrupts */
unsigned int ints;
/* software monitoring hw errors */
unsigned int tx_buf_error;
/* Software fifo overrun */
unsigned int rx_sw_dovr;
} occan_stats;
/* indexes into occan_stats.err_bus_segs[index] */
#define OCCAN_SEG_ID28 0x02 /* ID field bit 28:21 */
#define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */
#define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */
#define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */
#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */
#define OCCAN_SEG_START 0x03 /* Start of Frame */
#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */
#define OCCAN_SEG_IDE 0x05 /* Bit IDE */
#define OCCAN_SEG_RTR 0x0c /* Bit RTR */
#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */
#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */
#define OCCAN_SEG_DLEN 0x0b /* Data Length code */
#define OCCAN_SEG_DFIELD 0x0a /* Data Field */
#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */
#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */
#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */
#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */
#define OCCAN_SEG_EOF 0x1a /* End Of Frame */
#define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */
#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */
#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */
#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */
#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */
#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */
#define CANMSG_OPT_RTR 0x40 /* RTR Frame */
#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */
#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */
#define OCCAN_IOC_START 1
#define OCCAN_IOC_STOP 2
#define OCCAN_IOC_GET_CONF 3
#define OCCAN_IOC_GET_STATS 4
#define OCCAN_IOC_GET_STATUS 5
#define OCCAN_IOC_SET_SPEED 6
#define OCCAN_IOC_SPEED_AUTO 7
#define OCCAN_IOC_SET_LINK 8
#define OCCAN_IOC_SET_FILTER 9
#define OCCAN_IOC_SET_BLK_MODE 10
#define OCCAN_IOC_SET_BUFLEN 11
#define OCCAN_IOC_SET_BTRS 12
struct occan_afilter {
unsigned char code[4];
unsigned char mask[4];
int single_mode;
};
#define OCCAN_STATUS_RESET 0x01
#define OCCAN_STATUS_OVERRUN 0x02
#define OCCAN_STATUS_WARN 0x04
#define OCCAN_STATUS_ERR_PASSIVE 0x08
#define OCCAN_STATUS_ERR_BUSOFF 0x10
#define OCCAN_STATUS_QUEUE_ERROR 0x80
#define OCCAN_BLK_MODE_RX 0x1
#define OCCAN_BLK_MODE_TX 0x2
int occan_register(amba_confarea_type *bus);
#define OCCAN_SPEED_500K 500000
#define OCCAN_SPEED_250K 250000
#define OCCAN_SPEED_125K 125000
#define OCCAN_SPEED_75K 75000
#define OCCAN_SPEED_50K 50000
#define OCCAN_SPEED_25K 25000
#define OCCAN_SPEED_10K 10000
#ifdef __cplusplus
}
#endif
#endif

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c/src/lib/libbsp/sparc/shared/include/occan_pci.h Normal file
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/*
* OC_CAN controller via PCI - driver interface
*
* COPYRIGHT (c) 2007.
* Gaisler Research
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*/
#ifndef __OCCAN_PCI_H__
#define __OCCAN_PCI_H__
#include <occan.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register OC_CAN driver
* bus = pointer to AMBA bus description used to search for OC_CAN contrller(s).
*/
int occan_pci_register(amba_confarea_type *bus);
/* This function must be called on OC_CAN interrupt. Called from the
* PCI interrupt handler. irq = AMBA IRQ assigned to the OC_CAN device,
* is found by reading pending register on IRQMP connected to the OC_CAN
* device.
*
*/
void occanpci_interrupt_handler(int irq, void *arg);
extern void (*occan_pci_int_reg)(void *handler, int irq, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* __OCCAN_PCI_H__ */

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