forked from Imagelibrary/rtems
2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
* startup/cpuinit.h: Uses now powerpc-utility.h. Changed invalid usage of a boolean type to a proper integer type in calc_dbat_regvals(). Througout code formatting.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,9 @@
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2008-08-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* startup/cpuinit.h: Uses now powerpc-utility.h. Changed invalid usage
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of a boolean type to a proper integer type in calc_dbat_regvals().
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Througout code formatting.
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2008-08-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
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* include/tm27.h: Uses now a decrementer exception handler. Replaces
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@@ -70,183 +70,229 @@
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/* */
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/***********************************************************************/
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#include <bsp.h>
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#include <rtems/powerpc/registers.h>
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#include <mpc83xx/mpc83xx.h>
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#include <libcpu/mmu.h>
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#include <libcpu/spr.h>
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#include <stdbool.h>
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#include <string.h>
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#define USE_IMMU
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#include <libcpu/powerpc-utility.h>
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#include <libcpu/mmu.h>
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/* Macros for HID0 access */
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#define SET_HID0(r) __asm__ volatile ("mtspr 0x3F0,%0\n" ::"r"(r))
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#define GET_HID0(r) __asm__ volatile ("mfspr %0,0x3F0\n" :"=r"(r))
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#include <mpc83xx/mpc83xx.h>
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#define DBAT_MTSPR(val,name) __MTSPR(val,name);
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#define SET_DBAT(n,uv,lv) {DBAT_MTSPR(lv,DBAT##n##L);DBAT_MTSPR(uv,DBAT##n##U);}
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#if defined(USE_IMMU )
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#define IBAT_MTSPR(val,name) __MTSPR(val,name);
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#define SET_IBAT(n,uv,lv) {IBAT_MTSPR(lv,IBAT##n##L);IBAT_MTSPR(uv,IBAT##n##U);}
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#endif
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#include <bsp.h>
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static void calc_dbat_regvals(BAT *bat_ptr,
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uint32_t base_addr,
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uint32_t size,
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boolean flg_w,
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boolean flg_i,
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boolean flg_m,
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boolean flg_g,
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boolean flg_bpp)
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#define SET_DBAT( n, uv, lv) \
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do { \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
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} while (0)
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#define SET_IBAT( n, uv, lv) \
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do { \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \
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PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \
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} while (0)
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static void calc_dbat_regvals(
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BAT *bat_ptr,
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uint32_t base_addr,
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uint32_t size,
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bool flg_w,
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bool flg_i,
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bool flg_m,
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bool flg_g,
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uint32_t flg_bpp
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)
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{
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uint32_t block_mask;
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uint32_t end_addr;
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uint32_t block_mask = 0xffffffff;
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uint32_t end_addr = base_addr + size - 1;
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/*
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* determine block mask, that overlaps the whole block
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*/
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end_addr = base_addr+size-1;
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block_mask = 0xffffffff;
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/* Determine block mask, that overlaps the whole block */
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while ((end_addr & block_mask) != (base_addr & block_mask)) {
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block_mask <<= 1;
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}
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bat_ptr->batu.bepi = base_addr >> (32-15);
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bat_ptr->batu.bl = ~(block_mask >> (28-11));
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bat_ptr->batu.vs = 1;
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bat_ptr->batu.vp = 1;
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bat_ptr->batu.bepi = base_addr >> (32 - 15);
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bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
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bat_ptr->batu.vs = 1;
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bat_ptr->batu.vp = 1;
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bat_ptr->batl.brpn = base_addr >> (32-15);
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bat_ptr->batl.w = flg_w;
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bat_ptr->batl.i = flg_i;
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bat_ptr->batl.m = flg_m;
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bat_ptr->batl.g = flg_g;
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bat_ptr->batl.pp = flg_bpp;
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bat_ptr->batl.brpn = base_addr >> (32 - 15);
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bat_ptr->batl.w = flg_w;
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bat_ptr->batl.i = flg_i;
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bat_ptr->batl.m = flg_m;
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bat_ptr->batl.g = flg_g;
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bat_ptr->batl.pp = flg_bpp;
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}
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static void clear_mmu_regs(void)
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static void clear_mmu_regs( void)
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{
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uint32_t i;
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/*
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* clear segment registers
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*/
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/* Clear segment registers */
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for (i = 0;i < 16;i++) {
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asm volatile(" mtsrin %0, %1\n"::"r" (i * 0x1000),"r"(i<<(31-3)));
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asm volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3)));
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}
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/*
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* clear TLBs
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*/
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/* Clear TLBs */
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for (i = 0;i < 32;i++) {
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asm volatile(" tlbie %0\n"::"r" (i << (31-19)));
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asm volatile( "tlbie %0\n" : : "r" (i << (31 - 19)));
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}
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}
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void cpu_init(void)
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void cpu_init( void)
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{
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register unsigned long reg;
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BAT dbat,ibat;
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BAT dbat, ibat;
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uint32_t msr;
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/*
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* clear MMU/Segment registers
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*/
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/* Clear MMU and segment registers */
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clear_mmu_regs();
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/*
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* clear caches
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*/
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GET_HID0(reg);
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reg = (reg & ~(HID0_ILOCK | HID0_DLOCK)) | HID0_ICFI | HID0_DCI;
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SET_HID0(reg);
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reg &= ~(HID0_ICFI | HID0_DCI);
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SET_HID0(reg);
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/* Clear caches */
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PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ILOCK | HID0_DLOCK);
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PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
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PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_ICFI | HID0_DCI);
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/*
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* set up IBAT registers in MMU
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* Set up IBAT registers in MMU
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*/
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memset(&ibat,0,sizeof(ibat));
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SET_IBAT(2,ibat.batu,ibat.batl);
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SET_IBAT(3,ibat.batu,ibat.batl);
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SET_IBAT(4,ibat.batu,ibat.batl);
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SET_IBAT(5,ibat.batu,ibat.batl);
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SET_IBAT(6,ibat.batu,ibat.batl);
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SET_IBAT(7,ibat.batu,ibat.batl);
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#ifdef HAS_UBOOT
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calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RX);
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#else /* HAS_UBOOT */
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calc_dbat_regvals(&ibat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RX);
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#endif /* HAS_UBOOT */
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SET_IBAT(0,ibat.batu,ibat.batl);
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memset(&ibat, 0, sizeof( ibat));
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SET_IBAT( 2, ibat.batu, ibat.batl);
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SET_IBAT( 3, ibat.batu, ibat.batl);
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SET_IBAT( 4, ibat.batu, ibat.batl);
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SET_IBAT( 5, ibat.batu, ibat.batl);
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SET_IBAT( 6, ibat.batu, ibat.batl);
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SET_IBAT( 7, ibat.batu, ibat.batl);
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#ifdef HAS_UBOOT
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calc_dbat_regvals(&ibat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
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#else /* HAS_UBOOT */
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calc_dbat_regvals(&ibat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
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#endif /* HAS_UBOOT */
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calc_dbat_regvals(
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&ibat,
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#ifdef HAS_UBOOT
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mpc83xx_uboot_board_info.bi_memstart,
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mpc83xx_uboot_board_info.bi_memsize,
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#else /* HAS_UBOOT */
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(uint32_t) bsp_ram_start,
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(uint32_t) bsp_ram_size,
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#endif /* HAS_UBOOT */
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false,
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false,
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false,
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false,
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BPP_RX
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);
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SET_IBAT( 0, ibat.batu, ibat.batl);
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SET_IBAT(1,ibat.batu,ibat.batl);
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calc_dbat_regvals(
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&ibat,
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#ifdef HAS_UBOOT
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mpc83xx_uboot_board_info.bi_flashstart,
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mpc83xx_uboot_board_info.bi_flashsize,
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#else /* HAS_UBOOT */
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(uint32_t) bsp_rom_start,
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(uint32_t) bsp_rom_size,
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#endif /* HAS_UBOOT */
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false,
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false,
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false,
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false,
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BPP_RX
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);
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SET_IBAT( 1, ibat.batu, ibat.batl);
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/*
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* set up DBAT registers in MMU
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* Set up DBAT registers in MMU
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*/
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memset(&dbat,0,sizeof(dbat));
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SET_DBAT(3,dbat.batu,dbat.batl);
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SET_DBAT(4,dbat.batu,dbat.batl);
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SET_DBAT(5,dbat.batu,dbat.batl);
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SET_DBAT(6,dbat.batu,dbat.batl);
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SET_DBAT(7,dbat.batu,dbat.batl);
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#ifdef HAS_UBOOT
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calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_memstart,mpc83xx_uboot_board_info.bi_memsize,0,0,0,0,BPP_RW);
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#else /* HAS_UBOOT */
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calc_dbat_regvals(&dbat,(uint32_t) bsp_ram_start,(uint32_t) bsp_ram_size,0,0,0,0,BPP_RW);
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#endif /* HAS_UBOOT */
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memset(&dbat, 0, sizeof( dbat));
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SET_DBAT( 3, dbat.batu, dbat.batl);
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SET_DBAT( 4, dbat.batu, dbat.batl);
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SET_DBAT( 5, dbat.batu, dbat.batl);
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SET_DBAT( 6, dbat.batu, dbat.batl);
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SET_DBAT( 7, dbat.batu, dbat.batl);
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SET_DBAT(0,dbat.batu,dbat.batl);
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calc_dbat_regvals(
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&dbat,
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#ifdef HAS_UBOOT
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mpc83xx_uboot_board_info.bi_memstart,
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mpc83xx_uboot_board_info.bi_memsize,
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#else /* HAS_UBOOT */
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(uint32_t) bsp_ram_start,
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(uint32_t) bsp_ram_size,
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#endif /* HAS_UBOOT */
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false,
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false,
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false,
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false,
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BPP_RW
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);
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SET_DBAT( 0, dbat.batu, dbat.batl);
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#ifdef HAS_UBOOT
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calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_flashstart,mpc83xx_uboot_board_info.bi_flashsize,0,0,0,0,BPP_RX);
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#else /* HAS_UBOOT */
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calc_dbat_regvals(&dbat,(uint32_t) bsp_rom_start,(uint32_t) bsp_rom_size,0,0,0,0,BPP_RX);
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#endif /* HAS_UBOOT */
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calc_dbat_regvals(
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&dbat,
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#ifdef HAS_UBOOT
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mpc83xx_uboot_board_info.bi_flashstart,
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mpc83xx_uboot_board_info.bi_flashsize,
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#else /* HAS_UBOOT */
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(uint32_t) bsp_rom_start,
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(uint32_t) bsp_rom_size,
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#endif /* HAS_UBOOT */
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false,
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false,
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false,
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false,
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BPP_RX
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);
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SET_DBAT( 1, dbat.batu, dbat.batl);
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SET_DBAT(1,dbat.batu,dbat.batl);
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#ifdef HAS_UBOOT
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calc_dbat_regvals(&dbat,mpc83xx_uboot_board_info.bi_immrbar,1024*1024,0,1,0,1,BPP_RW);
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#else /* HAS_UBOOT */
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calc_dbat_regvals(&dbat,(uint32_t) IMMRBAR,1024*1024,0,1,0,1,BPP_RW);
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#endif /* HAS_UBOOT */
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SET_DBAT(2,dbat.batu,dbat.batl);
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calc_dbat_regvals(
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&dbat,
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#ifdef HAS_UBOOT
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mpc83xx_uboot_board_info.bi_immrbar,
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#else /* HAS_UBOOT */
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(uint32_t) IMMRBAR,
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#endif /* HAS_UBOOT */
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1024 * 1024,
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false,
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true,
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false,
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true,
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BPP_RW
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);
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SET_DBAT( 2, dbat.batu, dbat.batl);
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#ifdef MPC8313ERDB
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/* Enhanced Local Bus Controller (eLBC) */
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calc_dbat_regvals( &dbat, 0xfa000000, 128 * 1024, 0, 1, 0, 1, BPP_RW);
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calc_dbat_regvals(
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&dbat,
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0xfa000000,
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128 * 1024,
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false,
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true,
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false,
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true,
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BPP_RW
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);
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SET_DBAT( 3, dbat.batu, dbat.batl);
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#endif /* MPC8313ERDB */
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/*
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* enable data/instruction MMU in MSR
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*/
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_write_MSR(_read_MSR() | MSR_DR | MSR_IR);
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/* Read MSR */
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msr = ppc_machine_state_register();
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/* Enable data and instruction MMU in MSR */
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msr |= MSR_DR | MSR_IR;
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/* Enable FPU in MSR */
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msr |= MSR_FP;
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/* Update MSR */
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ppc_set_machine_state_register( msr);
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/*
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* enable FPU in MSR
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* In HID0:
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* - Enable dynamic power management
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* - Enable machine check interrupts
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*/
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_write_MSR(_read_MSR() | MSR_FP);
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PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_EMCP | HID0_DPM);
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/*
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* in HID0:
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* - enable dynamic power management
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* - enable machine check interrupts
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*/
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GET_HID0(reg);
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reg |= (HID0_EMCP | HID0_DPM) ;
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SET_HID0(reg);
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/*
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* enable timebase clock
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*/
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/* Enable timebase clock */
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mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN;
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}
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