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* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:

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correct some init values for HSC_CM01 boards
This commit is contained in:
Thomas Doerfler
2009-03-19 10:49:55 +00:00
parent 434bc85b02
commit ce7d6e62b7
4 changed files with 25 additions and 9 deletions
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5
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
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@@ -1,3 +1,8 @@
2009-03-18 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
correct some init values for HSC_CM01 boards
2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com> 2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>
* startup/bspstart.c: Change prototype of IDLE thread to consistently * startup/bspstart.c: Change prototype of IDLE thread to consistently

14
c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
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@@ -207,26 +207,26 @@
#define LBLAWBAR0_VAL bsp_rom_start #define LBLAWBAR0_VAL bsp_rom_start
#define LBLAWAR0_VAL 0x80000018 #define LBLAWAR0_VAL 0x80000018
#define LBLAWBAR1_VAL (FPGA_CONFIG_START) #define LBLAWBAR1_VAL (FPGA_CONFIG_START)
#define LBLAWAR1_VAL 0x80000015 #define LBLAWAR1_VAL 0x80000018
#define DDRLAWBAR0_VAL bsp_ram_start #define DDRLAWBAR0_VAL bsp_ram_start
#define DDRLAWAR0_VAL 0x8000001B #define DDRLAWAR0_VAL 0x8000001B
/* /*
* Local Bus (Memory) Controller * Local Bus (Memory) Controller
* FIXME: decode bit settings * FIXME: decode bit settings
*/ */
#define BR0_VAL 0xFE001001 #define BR0_VAL (0xFE000000 | 0x01001)
#define OR0_VAL 0xFE000E54 #define OR0_VAL 0xFE000E54
// fpga config access range (UPM_A) (32 kByte) // fpga config access range (UPM_A) (32 kByte)
#define BR2_VAL (FPGA_CONFIG_START | 0x01881) #define BR2_VAL (FPGA_CONFIG_START | 0x01881)
#define OR2_VAL 0xFFF80100 #define OR2_VAL 0xFFFF9100
// fpga register access range (UPM_B) (8 MByte) // fpga register access range (UPM_B) (8 MByte)
#define BR3_VAL (FPGA_REGISTER_START | 0x018A1) #define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
#define OR3_VAL 0xFF800100 #define OR3_VAL 0xFF801100
// fpga fifo access range (UPM_B) (8 MByte) // fpga fifo access range (UPM_C) (8 MByte)
#define BR4_VAL (FPGA_FIFO_START | 0x018A1) #define BR4_VAL (FPGA_FIFO_START | 0x018C1)
#define OR4_VAL 0xFF800100 #define OR4_VAL 0xFF801100
/* /*
* SDRAM registers * SDRAM registers

13
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
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@@ -199,7 +199,18 @@ start_code_in_rom:
#ifdef OR3_VAL #ifdef OR3_VAL
SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
#endif #endif
#ifdef BR4_VAL
SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
#endif
#ifdef OR4_VAL
SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
#endif
#ifdef BR5_VAL
SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
#endif
#ifdef OR5_VAL
SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
#endif
/* /*
* ROM startup: init SDRAM access window * ROM startup: init SDRAM access window
*/ */

2
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
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@@ -235,7 +235,7 @@ void cpu_init( void)
(uint32_t) bsp_rom_start, (uint32_t) bsp_rom_start,
(uint32_t) bsp_rom_size, (uint32_t) bsp_rom_size,
#endif /* HAS_UBOOT */ #endif /* HAS_UBOOT */
false, true,
false, false,
false, false,
false, false,