RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:

Browse Source 
correct some init values for HSC_CM01 boards
This commit is contained in:
Thomas Doerfler
2009-03-19 10:49:55 +00:00
parent 434bc85b02
commit ce7d6e62b7
4 changed files with 25 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
View File

@@ -1,3 +1,8 @@
2009-03-18 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
correct some init values for HSC_CM01 boards
2009-02-12 Joel Sherrill <joel.sherrill@oarcorp.com>
* startup/bspstart.c: Change prototype of IDLE thread to consistently

14
c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
View File

@@ -207,26 +207,26 @@
#define LBLAWBAR0_VAL bsp_rom_start
#define LBLAWAR0_VAL 0x80000018
#define LBLAWBAR1_VAL (FPGA_CONFIG_START)
#define LBLAWAR1_VAL 0x80000015
#define LBLAWAR1_VAL 0x80000018
#define DDRLAWBAR0_VAL bsp_ram_start
#define DDRLAWAR0_VAL 0x8000001B
/*
* Local Bus (Memory) Controller
* FIXME: decode bit settings
*/
#define BR0_VAL 0xFE001001
#define BR0_VAL (0xFE000000 | 0x01001)
#define OR0_VAL 0xFE000E54
// fpga config access range (UPM_A) (32 kByte)
#define BR2_VAL (FPGA_CONFIG_START | 0x01881)
#define OR2_VAL 0xFFF80100
#define OR2_VAL 0xFFFF9100
// fpga register access range (UPM_B) (8 MByte)
#define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
#define OR3_VAL 0xFF800100
#define OR3_VAL 0xFF801100
// fpga fifo access range (UPM_B) (8 MByte)
#define BR4_VAL (FPGA_FIFO_START | 0x018A1)
#define OR4_VAL 0xFF800100
// fpga fifo access range (UPM_C) (8 MByte)
#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
#define OR4_VAL 0xFF801100
/*
* SDRAM registers

13
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
View File

@@ -199,7 +199,18 @@ start_code_in_rom:
#ifdef OR3_VAL
SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
#endif
#ifdef BR4_VAL
SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
#endif
#ifdef OR4_VAL
SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
#endif
#ifdef BR5_VAL
SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
#endif
#ifdef OR5_VAL
SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
#endif
/*
* ROM startup: init SDRAM access window
*/

2
c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c
View File

@@ -235,7 +235,7 @@ void cpu_init( void)
(uint32_t) bsp_rom_start,
(uint32_t) bsp_rom_size,
#endif /* HAS_UBOOT */
false,
true,
false,
false,
false,