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* rtems/powerpc/registers.h: Added Freescale Book E Implementation

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Standards (EIS) special purpose register definitions for MMU and L1
	cache.
This commit is contained in:
Thomas Doerfler
2009-02-27 11:06:21 +00:00
parent 06f8e558b7
commit cd4ed38422
2 changed files with 33 additions and 0 deletions
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6
cpukit/score/cpu/powerpc/ChangeLog
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@@ -1,3 +1,9 @@
2009-02-27 Sebastian Huber <sebastian.huber@embedded-brains.de>
* rtems/powerpc/registers.h: Added Freescale Book E Implementation
Standards (EIS) special purpose register definitions for MMU and L1
cache.
2009-02-11 Joel Sherrill <joel.sherrill@oarcorp.com>
* rtems/new-exceptions/cpu.h, rtems/score/cpu.h: Eliminate

27
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
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@@ -311,6 +311,33 @@ lidate */
#define BOOKE_TCR_FPEXT(x) (((x)&0xf)<<13)
#define BOOKE_TCR_FPEXT_MASK (0xf<<13)
#define BOOKE_PID 48
/* Freescale Book E Implementation Standards (EIS): MMU Control and Status */
#define FREESCALE_EIS_MAS0 624
#define FREESCALE_EIS_MAS1 625
#define FREESCALE_EIS_MAS2 626
#define FREESCALE_EIS_MAS3 627
#define FREESCALE_EIS_MAS4 628
#define FREESCALE_EIS_MAS5 629
#define FREESCALE_EIS_MAS6 630
#define FREESCALE_EIS_MAS7 944
#define FREESCALE_EIS_MMUCFG 1015
#define FREESCALE_EIS_MMUCSR0 1012
#define FREESCALE_EIS_PID0 48
#define FREESCALE_EIS_PID1 633
#define FREESCALE_EIS_PID2 634
#define FREESCALE_EIS_TLB0CFG 688
#define FREESCALE_EIS_TLB1CFG 689
/* Freescale Book E Implementation Standards (EIS): L1 Cache */
#define FREESCALE_EIS_L1CFG0 515
#define FREESCALE_EIS_L1CFG1 516
#define FREESCALE_EIS_L1CSR0 1010
#define FREESCALE_EIS_L1CSR1 1011
/**
* @brief Default value for the interrupt disable mask.
*