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sparc: Ensure interrupt service after ISR enable

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This commit is contained in:
Sebastian Huber
2015-03-25 11:40:08 +01:00
parent 10a699d3fc
commit cb4dd48e06
1 changed files with 8 additions and 1 deletions
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9
cpukit/score/cpu/sparc/rtems/score/sparc.h
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@@ -320,7 +320,14 @@ static inline uint32_t sparc_disable_interrupts(void)
static inline void sparc_enable_interrupts(uint32_t psr) static inline void sparc_enable_interrupts(uint32_t psr)
{ {
register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */ register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */
__asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
/*
* The trap instruction has a higher trap priority than the interrupts
* according to "The SPARC Architecture Manual: Version 8", Table 7-1
* "Exception and Interrupt Request Priority and tt Values". Add a nop to
* prevent a trap instruction right after the interrupt enable trap.
*/
__asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
} }
/** /**