forked from Imagelibrary/rtems
sparc: Ensure interrupt service after ISR enable
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@@ -320,7 +320,14 @@ static inline uint32_t sparc_disable_interrupts(void)
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static inline void sparc_enable_interrupts(uint32_t psr)
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{
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register uint32_t _psr __asm__("g1") = psr; /* input to trap handler */
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__asm__ volatile ( "ta %0\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
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/*
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* The trap instruction has a higher trap priority than the interrupts
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* according to "The SPARC Architecture Manual: Version 8", Table 7-1
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* "Exception and Interrupt Request Priority and tt Values". Add a nop to
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* prevent a trap instruction right after the interrupt enable trap.
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*/
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__asm__ volatile ( "ta %0\nnop\n" :: "i" (SPARC_SWTRAP_IRQEN), "r" (_psr));
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}
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/**
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