forked from Imagelibrary/rtems
arm/xilinx_zynq: Start the second core when an SMP build.
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@@ -14,8 +14,23 @@
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#include <rtems/score/smpimpl.h>
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extern void _start(void);
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bool _CPU_SMP_Start_processor(uint32_t cpu_index)
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{
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/*
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* Enable the second CPU.
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*/
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if (cpu_index != 0) {
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volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
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_ARM_Data_synchronization_barrier();
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_ARM_Instruction_synchronization_barrier();
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*kick_address = (uint32_t) _start;
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_ARM_Data_synchronization_barrier();
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_ARM_Instruction_synchronization_barrier();
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_ARM_Send_event();
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}
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/*
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* Wait for secondary processor to complete its basic initialization so that
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* we can enable the unified L2 cache.
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@@ -22,6 +22,13 @@
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BSP_START_DATA_SECTION static const arm_cp15_start_section_config
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zynq_mmu_config_table[] = {
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ARMV7_CP15_START_DEFAULT_SECTIONS,
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#if defined(RTEMS_SMP)
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{
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.begin = 0xffff0000U,
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.end = 0xffffffffU,
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.flags = ARMV7_MMU_DEVICE
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},
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#endif
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{
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.begin = 0xe0000000U,
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.end = 0xe0200000U,
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