2010-06-15 Joel Sherrill <joel.sherrill@oarcorp.com>

PR 1561/cpukit * .cvsignore, ChangeLog, Makefile.am, Makefile.in, README, context.S, cpu.c, preinstall.am, rtems/asm.h, rtems/score/cpu.h, rtems/score/sparc64.h, rtems/score/types.h: New files.
2010-06-15 22:43:56 +00:00
parent 591b76084c
commit c86da31cb9
12 changed files with 2766 additions and 0 deletions
--- a/cpukit/score/cpu/sparc64/.cvsignore
+++ b/cpukit/score/cpu/sparc64/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
--- a/cpukit/score/cpu/sparc64/ChangeLog
+++ b/cpukit/score/cpu/sparc64/ChangeLog
@@ -0,0 +1,31 @@
+2010-06-15	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1561/cpukit
+	* .cvsignore, ChangeLog, Makefile.am, Makefile.in, README, context.S,
+	cpu.c, preinstall.am, rtems/asm.h, rtems/score/cpu.h,
+	rtems/score/sparc64.h, rtems/score/types.h: New files.
+
+2010-05-10  Gedare Bloom <gedare@gwmail.gwu.edu>
+
+	* README: Explain separation of score between here and libcpu.
+
+2010-05-03  Gedare Bloom <gedare@gwmail.gwu.edu>
+
+	* rtems/score/cpu.h, context.S, cpu.c: Remove privileged
+	registers from context.
+
+2010-05-03  Gedare Bloom <gedare@gwmail.gwu.edu>
+
+	* cpu.c: Remove interrupt handling code.  Moved to libcpu.
+
+2010-05-03  Gedare Bloom <gedare@gwmail.gwu.edu>
+
+	* context.S: renamed cpu_asm.S to context.S
+
+2010-05-02  Gedare Bloom <gedare@gwmail.gwu.edu>
+
+	* cpu_asm.S: Remove interrupt handling code.  Moved to libcpu.
+
+2009-10-19	Eugen Leontie <eugen@gwu.edu>
+
+	Added sparc64 architecture
--- a/cpukit/score/cpu/sparc64/Makefile.am
+++ b/cpukit/score/cpu/sparc64/Makefile.am
@@ -0,0 +1,22 @@
+##
+## $Id$
+##
+
+include $(top_srcdir)/automake/compile.am
+
+include_rtemsdir = $(includedir)/rtems
+include_rtems_HEADERS = rtems/asm.h
+
+#include_rtems_sparc64dir = $(includedir)/rtems/sparc64
+#include_rtems_sparc64_HEADERS = 
+
+include_rtems_scoredir = $(includedir)/rtems/score
+include_rtems_score_HEADERS = rtems/score/sparc64.h rtems/score/cpu.h \
+    rtems/score/types.h
+
+noinst_LIBRARIES = libscorecpu.a
+libscorecpu_a_SOURCES = context.S cpu.c
+libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/automake/local.am
--- a/cpukit/score/cpu/sparc64/Makefile.in
+++ b/cpukit/score/cpu/sparc64/Makefile.in
@@ -0,0 +1,654 @@
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+
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+# 2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation,
+# Inc.
+# This Makefile.in is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
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+
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+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/libscorecpu_a-cpu.Tpo $(DEPDIR)/libscorecpu_a-cpu.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='cpu.c' object='libscorecpu_a-cpu.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libscorecpu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libscorecpu_a-cpu.o `test -f 'cpu.c' || echo '$(srcdir)/'`cpu.c
+
+libscorecpu_a-cpu.obj: cpu.c
+@am__fastdepCC_TRUE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libscorecpu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT libscorecpu_a-cpu.obj -MD -MP -MF $(DEPDIR)/libscorecpu_a-cpu.Tpo -c -o libscorecpu_a-cpu.obj `if test -f 'cpu.c'; then $(CYGPATH_W) 'cpu.c'; else $(CYGPATH_W) '$(srcdir)/cpu.c'; fi`
+@am__fastdepCC_TRUE@	$(am__mv) $(DEPDIR)/libscorecpu_a-cpu.Tpo $(DEPDIR)/libscorecpu_a-cpu.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='cpu.c' object='libscorecpu_a-cpu.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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+install-include_rtemsHEADERS: $(include_rtems_HEADERS)
+	@$(NORMAL_INSTALL)
+	test -z "$(include_rtemsdir)" || $(MKDIR_P) "$(DESTDIR)$(include_rtemsdir)"
+	@list='$(include_rtems_HEADERS)'; test -n "$(include_rtemsdir)" || list=; \
+	for p in $$list; do \
+	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+	  echo "$$d$$p"; \
+	done | $(am__base_list) | \
+	while read files; do \
+	  echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(include_rtemsdir)'"; \
+	  $(INSTALL_HEADER) $$files "$(DESTDIR)$(include_rtemsdir)" || exit $$?; \
+	done
+
+uninstall-include_rtemsHEADERS:
+	@$(NORMAL_UNINSTALL)
+	@list='$(include_rtems_HEADERS)'; test -n "$(include_rtemsdir)" || list=; \
+	files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+	test -n "$$files" || exit 0; \
+	echo " ( cd '$(DESTDIR)$(include_rtemsdir)' && rm -f" $$files ")"; \
+	cd "$(DESTDIR)$(include_rtemsdir)" && rm -f $$files
+install-include_rtems_scoreHEADERS: $(include_rtems_score_HEADERS)
+	@$(NORMAL_INSTALL)
+	test -z "$(include_rtems_scoredir)" || $(MKDIR_P) "$(DESTDIR)$(include_rtems_scoredir)"
+	@list='$(include_rtems_score_HEADERS)'; test -n "$(include_rtems_scoredir)" || list=; \
+	for p in $$list; do \
+	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
+	  echo "$$d$$p"; \
+	done | $(am__base_list) | \
+	while read files; do \
+	  echo " $(INSTALL_HEADER) $$files '$(DESTDIR)$(include_rtems_scoredir)'"; \
+	  $(INSTALL_HEADER) $$files "$(DESTDIR)$(include_rtems_scoredir)" || exit $$?; \
+	done
+
+uninstall-include_rtems_scoreHEADERS:
+	@$(NORMAL_UNINSTALL)
+	@list='$(include_rtems_score_HEADERS)'; test -n "$(include_rtems_scoredir)" || list=; \
+	files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
+	test -n "$$files" || exit 0; \
+	echo " ( cd '$(DESTDIR)$(include_rtems_scoredir)' && rm -f" $$files ")"; \
+	cd "$(DESTDIR)$(include_rtems_scoredir)" && rm -f $$files
+
+ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
+	list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+	      END { if (nonempty) { for (i in files) print i; }; }'`; \
+	mkid -fID $$unique
+tags: TAGS
+
+TAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+		$(TAGS_FILES) $(LISP)
+	set x; \
+	here=`pwd`; \
+	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+	      END { if (nonempty) { for (i in files) print i; }; }'`; \
+	shift; \
+	if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \
+	  test -n "$$unique" || unique=$$empty_fix; \
+	  if test $$# -gt 0; then \
+	    $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+	      "$$@" $$unique; \
+	  else \
+	    $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
+	      $$unique; \
+	  fi; \
+	fi
+ctags: CTAGS
+CTAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
+		$(TAGS_FILES) $(LISP)
+	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
+	unique=`for i in $$list; do \
+	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
+	  done | \
+	  $(AWK) '{ files[$$0] = 1; nonempty = 1; } \
+	      END { if (nonempty) { for (i in files) print i; }; }'`; \
+	test -z "$(CTAGS_ARGS)$$unique" \
+	  || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
+	     $$unique
+
+GTAGS:
+	here=`$(am__cd) $(top_builddir) && pwd` \
+	  && $(am__cd) $(top_srcdir) \
+	  && gtags -i $(GTAGS_ARGS) "$$here"
+
+distclean-tags:
+	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
+
+distdir: $(DISTFILES)
+	@srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
+	list='$(DISTFILES)'; \
+	  dist_files=`for file in $$list; do echo $$file; done | \
+	  sed -e "s|^$$srcdirstrip/||;t" \
+	      -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
+	case $$dist_files in \
+	  */*) $(MKDIR_P) `echo "$$dist_files" | \
+			   sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
+			   sort -u` ;; \
+	esac; \
+	for file in $$dist_files; do \
+	  if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
+	  if test -d $$d/$$file; then \
+	    dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
+	    if test -d "$(distdir)/$$file"; then \
+	      find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+	    fi; \
+	    if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
+	      cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \
+	      find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \
+	    fi; \
+	    cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \
+	  else \
+	    test -f "$(distdir)/$$file" \
+	    || cp -p $$d/$$file "$(distdir)/$$file" \
+	    || exit 1; \
+	  fi; \
+	done
+check-am: all-am
+check: check-am
+all-am: Makefile $(LIBRARIES) $(HEADERS)
+installdirs:
+	for dir in "$(DESTDIR)$(include_rtemsdir)" "$(DESTDIR)$(include_rtems_scoredir)"; do \
+	  test -z "$$dir" || $(MKDIR_P) "$$dir"; \
+	done
+install: install-am
+install-exec: install-exec-am
+install-data: install-data-am
+uninstall: uninstall-am
+
+install-am: all-am
+	@$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
+
+installcheck: installcheck-am
+install-strip:
+	$(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
+	  install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
+	  `test -z '$(STRIP)' || \
+	    echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
+mostlyclean-generic:
+
+clean-generic:
+	-test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
+
+distclean-generic:
+	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
+	-test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
+	-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
+
+maintainer-clean-generic:
+	@echo "This command is intended for maintainers to use"
+	@echo "it deletes files that may require special tools to rebuild."
+clean: clean-am
+
+clean-am: clean-generic clean-noinstLIBRARIES mostlyclean-am
+
+distclean: distclean-am
+	-rm -rf ./$(DEPDIR)
+	-rm -f Makefile
+distclean-am: clean-am distclean-compile distclean-generic \
+	distclean-tags
+
+dvi: dvi-am
+
+dvi-am:
+
+html: html-am
+
+html-am:
+
+info: info-am
+
+info-am:
+
+install-data-am: install-include_rtemsHEADERS \
+	install-include_rtems_scoreHEADERS
+
+install-dvi: install-dvi-am
+
+install-dvi-am:
+
+install-exec-am:
+
+install-html: install-html-am
+
+install-html-am:
+
+install-info: install-info-am
+
+install-info-am:
+
+install-man:
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+install-pdf: install-pdf-am
+
+install-pdf-am:
+
+install-ps: install-ps-am
+
+install-ps-am:
+
+installcheck-am:
+
+maintainer-clean: maintainer-clean-am
+	-rm -rf ./$(DEPDIR)
+	-rm -f Makefile
+maintainer-clean-am: distclean-am maintainer-clean-generic
+
+mostlyclean: mostlyclean-am
+
+mostlyclean-am: mostlyclean-compile mostlyclean-generic
+
+pdf: pdf-am
+
+pdf-am:
+
+ps: ps-am
+
+ps-am:
+
+uninstall-am: uninstall-include_rtemsHEADERS \
+	uninstall-include_rtems_scoreHEADERS
+
+.MAKE: install-am install-strip
+
+.PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \
+	clean-noinstLIBRARIES ctags distclean distclean-compile \
+	distclean-generic distclean-tags distdir dvi dvi-am html \
+	html-am info info-am install install-am install-data \
+	install-data-am install-dvi install-dvi-am install-exec \
+	install-exec-am install-html install-html-am \
+	install-include_rtemsHEADERS \
+	install-include_rtems_scoreHEADERS install-info \
+	install-info-am install-man install-pdf install-pdf-am \
+	install-ps install-ps-am install-strip installcheck \
+	installcheck-am installdirs maintainer-clean \
+	maintainer-clean-generic mostlyclean mostlyclean-compile \
+	mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \
+	uninstall-am uninstall-include_rtemsHEADERS \
+	uninstall-include_rtems_scoreHEADERS
+
+
+@AMPOLISH3_TRUE@$(srcdir)/preinstall.am: Makefile.am
+@AMPOLISH3_TRUE@	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+
+all-am: $(PREINSTALL_FILES)
+
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
+	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
+	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/sparc64.h: rtems/score/sparc64.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sparc64.h
+
+$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
+
+$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
+
+preinstall-am: $(PREINSTALL_FILES)
+preinstall: preinstall-am
+.PHONY: preinstall preinstall-am
+
+# Tell versions [3.59,3.63) of GNU make to not export all variables.
+# Otherwise a system limit (for SysV at least) may be exceeded.
+.NOEXPORT:
--- a/cpukit/score/cpu/sparc64/README
+++ b/cpukit/score/cpu/sparc64/README
@@ -0,0 +1,15 @@
+#
+#  $Id$
+#
+
+A lot of explanation needed, will do when known.
+
+The score/cpu/sparc64 contains only code that can execute without accessing 
+privileged registers or using privileged instructions. This was done because
+the privileged registers differ between the sun4u and sun4v models.
+
+The model specific and privileged code that would normally be found in 
+score/cpu/sparc64 resides in libcpu/sparc64/@RTEMS_CPU_MODEL@/score or in
+libcpu/sparc64/shared/score directory. This is primarily the interrupt 
+handling code.
+
--- a/cpukit/score/cpu/sparc64/context.S
+++ b/cpukit/score/cpu/sparc64/context.S
@@ -0,0 +1,322 @@
+/*  context.S
+ *
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language. 
+ *
+ *  COPYRIGHT (c) 1989-2007.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  Ported to ERC32 implementation of the SPARC by On-Line Applications
+ *  Research Corporation (OAR) under contract to the European Space 
+ *  Agency (ESA).
+ *
+ *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
+ *  European Space Agency.
+ *
+ *  Ported to UltraSPARC T1 Niagara implementation of the SPARC-v9.
+ *  Niagara modifications of respective RTEMS file: 
+ *    COPYRIGHT (c) 2010. Gedare Bloom.
+ *
+ *  $Id$
+ */
+
+#include <rtems/asm.h>
+
+
+/* 
+ *  The assembler needs to be told that we know what to do with 
+ *  the global registers.
+ */
+.register %g2, #scratch
+.register %g3, #scratch
+.register %g6, #scratch
+.register %g7, #scratch
+
+#if (SPARC_HAS_FPU == 1)
+
+/*
+ *  void _CPU_Context_save_fp(
+ *    void **fp_context_ptr
+ *  )
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ */
+
+  .align 4
+PUBLIC(_CPU_Context_save_fp)
+  SYM(_CPU_Context_save_fp):
+    save    %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+
+    /*
+     *  The following enables the floating point unit.
+     */
+
+    sparc64_enable_FPU(%l0)
+
+  /*
+   *  Although sun4v supports alternate register names for double-
+   *  and quad-word floating point, SPARC v9 only uses f[#]
+   *
+   *  Because quad-word fp is not supported by the hardware in 
+   *  many situations, we stick with double-word fp operations
+   */
+  ldx    [%i0], %l0     
+  std     %f0, [%l0]
+  std     %f2, [%l0 + F2_OFFSET]
+  std     %f4, [%l0 + F4_OFFSET]
+  std     %f6, [%l0 + F6_OFFSET]
+  std     %f8, [%l0 + F8_OFFSET]
+  std     %f10, [%l0 + F1O_OFFSET]
+  std     %f12, [%l0 + F12_OFFSET]
+  std     %f14, [%l0 + F14_OFFSET]
+  std     %f16, [%l0 + F16_OFFSET]
+  std     %f18, [%l0 + F18_OFFSET]
+  std     %f20, [%l0 + F2O_OFFSET]
+  std     %f22, [%l0 + F22_OFFSET]
+  std     %f24, [%l0 + F24_OFFSET]
+  std     %f26, [%l0 + F26_OFFSET]
+  std     %f28, [%l0 + F28_OFFSET]
+  std     %f30, [%l0 + F3O_OFFSET]
+  std     %f32, [%l0 + F32_OFFSET]
+  std     %f34, [%l0 + F34_OFFSET]
+  std     %f36, [%l0 + F36_OFFSET]
+  std     %f38, [%l0 + F38_OFFSET]
+  std     %f40, [%l0 + F4O_OFFSET]
+  std     %f42, [%l0 + F42_OFFSET]
+  std     %f44, [%l0 + F44_OFFSET]
+  std     %f46, [%l0 + F46_OFFSET]
+  std     %f48, [%l0 + F48_OFFSET]
+  std     %f50, [%l0 + F5O_OFFSET]
+  std     %f52, [%l0 + F52_OFFSET]
+  std     %f54, [%l0 + F54_OFFSET]
+  std     %f56, [%l0 + F56_OFFSET]
+  std     %f58, [%l0 + F58_OFFSET]
+  std     %f60, [%l0 + F6O_OFFSET]       
+  std     %f62, [%l0 + F62_OFFSET]
+  stx     %fsr, [%l0 + FSR_OFFSET]
+  ret
+  restore
+
+  /*
+   *  void _CPU_Context_restore_fp(
+   *    void **fp_context_ptr
+   *  )
+   *
+   *  This routine is responsible for restoring the FP context
+   *  at *fp_context_ptr.  If the point to load the FP context
+   *  from is changed then the pointer is modified by this routine.
+   *
+   */
+
+  .align 4
+PUBLIC(_CPU_Context_restore_fp)
+  SYM(_CPU_Context_restore_fp):
+    save    %sp, -CPU_MINIMUM_STACK_FRAME_SIZE , %sp
+
+    /*
+     *  The following enables the floating point unit.
+     */
+
+    sparc64_enable_FPU(%l0)
+
+  ldx     [%i0], %l0
+  ldd     [%l0 + FO_OFFSET], %f0
+  ldd     [%l0 + F2_OFFSET], %f2
+  ldd     [%l0 + F4_OFFSET], %f4
+  ldd     [%l0 + F6_OFFSET], %f6
+  ldd     [%l0 + F8_OFFSET], %f8
+  ldd     [%l0 + F1O_OFFSET], %f10
+  ldd     [%l0 + F12_OFFSET], %f12
+  ldd     [%l0 + F14_OFFSET], %f14
+  ldd     [%l0 + F16_OFFSET], %f16
+  ldd     [%l0 + F18_OFFSET], %f18
+  ldd     [%l0 + F2O_OFFSET], %f20
+  ldd     [%l0 + F22_OFFSET], %f22
+  ldd     [%l0 + F24_OFFSET], %f24
+  ldd     [%l0 + F26_OFFSET], %f26
+  ldd     [%l0 + F28_OFFSET], %f28
+  ldd     [%l0 + F3O_OFFSET], %f30
+  ldd     [%l0 + F32_OFFSET], %f32
+  ldd     [%l0 + F34_OFFSET], %f34
+  ldd     [%l0 + F36_OFFSET], %f36
+  ldd     [%l0 + F38_OFFSET], %f38
+  ldd     [%l0 + F4O_OFFSET], %f40
+  ldd     [%l0 + F42_OFFSET], %f42
+  ldd     [%l0 + F44_OFFSET], %f44
+  ldd     [%l0 + F46_OFFSET], %f46
+  ldd     [%l0 + F48_OFFSET], %f48
+  ldd     [%l0 + F5O_OFFSET], %f50
+  ldd     [%l0 + F52_OFFSET], %f52
+  ldd     [%l0 + F54_OFFSET], %f54
+  ldd     [%l0 + F56_OFFSET], %f56
+  ldd     [%l0 + F58_OFFSET], %f58
+  ldd     [%l0 + F6O_OFFSET], %f60
+  ldd     [%l0 + F62_OFFSET], %f62
+  ldx     [%l0 + FSR_OFFSET], %fsr
+  ret
+  restore
+
+#endif /* SPARC_HAS_FPU */
+
+  /*
+   *  void _CPU_Context_switch(
+   *    Context_Control  *run,
+   *    Context_Control  *heir
+   *  )
+   *
+   *  This routine performs a normal non-FP context switch.
+   */
+
+  .align 4
+PUBLIC(_CPU_Context_switch)
+  SYM(_CPU_Context_switch):
+    ! skip g0
+      stx     %g1, [%o0 + G1_OFFSET]       ! save the global registers
+      stx     %g2, [%o0 + G2_OFFSET]
+      stx     %g3, [%o0 + G3_OFFSET]       
+      stx     %g4, [%o0 + G4_OFFSET]
+      stx     %g5, [%o0 + G5_OFFSET]       
+      stx     %g6, [%o0 + G6_OFFSET]
+      stx     %g7, [%o0 + G7_OFFSET]
+
+      ! load the address of the ISR stack nesting prevention flag
+      setx  SYM(_CPU_ISR_Dispatch_disable), %g1, %g2
+      lduw  [%g2], %g2
+
+      ! save it a bit later so we do not waste a couple of cycles
+
+      stx     %l0, [%o0 + L0_OFFSET]       ! save the local registers
+      stx     %l1, [%o0 + L1_OFFSET]
+      stx     %l2, [%o0 + L2_OFFSET]
+      stx     %l3, [%o0 + L3_OFFSET]
+      stx     %l4, [%o0 + L4_OFFSET]
+      stx     %l5, [%o0 + L5_OFFSET]
+      stx     %l6, [%o0 + L6_OFFSET]
+      stx     %l7, [%o0 + L7_OFFSET]
+
+      ! Now actually save ISR stack nesting prevention flag
+      stuw     %g2, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
+
+      stx     %i0, [%o0 + I0_OFFSET]       ! save the input registers
+      stx     %i1, [%o0 + I1_OFFSET]
+      stx     %i2, [%o0 + I2_OFFSET]
+      stx     %i3, [%o0 + I3_OFFSET]
+      stx     %i4, [%o0 + I4_OFFSET]
+      stx     %i5, [%o0 + I5_OFFSET]
+      stx     %i6, [%o0 + I6_FP_OFFSET]
+      stx     %i7, [%o0 + I7_OFFSET]
+
+      stx     %o0, [%o0 + O0_OFFSET]       ! save the output registers
+      stx     %o1, [%o0 + O1_OFFSET]
+      stx     %o2, [%o0 + O2_OFFSET]
+      stx     %o3, [%o0 + O3_OFFSET]
+      stx     %o4, [%o0 + O4_OFFSET]
+      stx     %o5, [%o0 + O5_OFFSET]
+      stx     %o6, [%o0 + O6_SP_OFFSET]
+      stx     %o7, [%o0 + O7_OFFSET]       ! o7 is the PC
+
+!      rdpr    %pil, %o2
+!      stuw    %o2, [%o0 + PIL_OFFSET] ! save pil
+
+!      rdpr    %pstate, %o2
+!      stx     %o2, [%o0 + PSTATE_OFFSET]      ! save status register
+
+      /*
+       *  This is entered from _CPU_Context_restore with:
+       *    o1 = context to restore
+!       *    o2 = pstate
+       *
+       *  NOTE: Flushing the register windows is necessary, but it adds 
+       *  an unpredictable (but bounded) overhead to context switching.
+       */
+
+PUBLIC(_CPU_Context_restore_heir)
+  SYM(_CPU_Context_restore_heir):
+
+    flushw
+
+
+
+    ! skip g0
+    ldx     [%o1 + G1_OFFSET], %g1        ! restore the global registers
+    ldx     [%o1 + G2_OFFSET], %g2
+    ldx     [%o1 + G3_OFFSET], %g3
+    ldx     [%o1 + G4_OFFSET], %g4
+    ldx     [%o1 + G5_OFFSET], %g5
+    ldx     [%o1 + G6_OFFSET], %g6
+    ldx     [%o1 + G7_OFFSET], %g7
+
+    ! Load thread specific ISR dispatch prevention flag
+    ldx    [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
+    setx  SYM(_CPU_ISR_Dispatch_disable), %o5, %o3
+    ! Store it to memory later to use the cycles
+
+    ldx     [%o1 + L0_OFFSET], %l0        ! restore the local registers
+    ldx     [%o1 + L1_OFFSET], %l1
+    ldx     [%o1 + L2_OFFSET], %l2
+    ldx     [%o1 + L3_OFFSET], %l3
+    ldx     [%o1 + L4_OFFSET], %l4
+    ldx     [%o1 + L5_OFFSET], %l5
+    ldx     [%o1 + L6_OFFSET], %l6
+    ldx     [%o1 + L7_OFFSET], %l7
+
+    ! Now restore thread specific ISR dispatch prevention flag
+    stuw  %o2, [%o3]
+
+    ldx     [%o1 + I0_OFFSET], %i0        ! restore the input registers
+    ldx     [%o1 + I1_OFFSET], %i1
+    ldx     [%o1 + I2_OFFSET], %i2
+    ldx     [%o1 + I3_OFFSET], %i3
+    ldx     [%o1 + I4_OFFSET], %i4
+    ldx     [%o1 + I5_OFFSET], %i5
+    ldx     [%o1 + I6_FP_OFFSET], %i6
+    ldx     [%o1 + I7_OFFSET], %i7
+
+    ldx     [%o1 + O0_OFFSET], %o0
+    ldx     [%o1 + O2_OFFSET], %o2        ! restore the output registers
+    ldx     [%o1 + O3_OFFSET], %o3
+    ldx     [%o1 + O4_OFFSET], %o4
+    ldx     [%o1 + O5_OFFSET], %o5
+    ldx     [%o1 + O6_SP_OFFSET], %o6
+    ldx     [%o1 + O7_OFFSET], %o7       ! PC
+
+    ! on a hunch... we should be able to use some of the %o regs
+!    lduw    [%o1 + PIL_OFFSET], %o2
+!    wrpr    %g0, %o2, %pil
+
+!    ldx     [%o1 + PSTATE_OFFSET], %o2
+
+    ! do o1 last to avoid destroying heir context pointer
+    ldx     [%o1 + O1_OFFSET], %o1        ! overwrite heir pointer
+!    wrpr    %g0, %o2, %pstate
+
+    retl
+    nop
+
+    /*
+     *  void _CPU_Context_restore(
+     *    Context_Control *new_context
+     *  )
+     *
+     *  This routine is generally used only to perform restart self.
+     *
+     *  NOTE: It is unnecessary to reload some registers.
+     */
+    /* if _CPU_Context_restore_heir does not flushw, then do it here */
+  .align 4
+PUBLIC(_CPU_Context_restore)
+  SYM(_CPU_Context_restore):
+    save    %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
+!    rdpr    %pstate, %o2
+    ba      SYM(_CPU_Context_restore_heir)
+    mov     %i0, %o1                      ! in the delay slot
+
+/* end of file */
--- a/cpukit/score/cpu/sparc64/cpu.c
+++ b/cpukit/score/cpu/sparc64/cpu.c
@@ -0,0 +1,116 @@
+/*
+ *  SPARC-v9 Dependent Source
+ *
+ *  COPYRIGHT (c) 1989-2007.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  This file is based on the SPARC cpu.c file. Modifications are made to 
+ *  provide support for the SPARC-v9.
+ *    COPYRIGHT (c) 2010. Gedare Bloom.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/asm.h>
+#include <rtems/score/isr.h>
+#include <rtems/rtems/cache.h>
+
+/*PAGE
+ *
+ *  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS: NONE
+ *
+ *  Output Parameters: NONE
+ *
+ *  NOTE: There is no need to save the pointer to the thread dispatch routine.
+ *        The SPARC's assembly code can reference it directly with no problems.
+ */
+
+void _CPU_Initialize(void)
+{
+#if (SPARC_HAS_FPU == 1)
+  Context_Control_fp *pointer;
+
+  /*
+   *  This seems to be the most appropriate way to obtain an initial
+   *  FP context on the SPARC.  The NULL fp context is copied in to
+   *  the task's FP context during Context_Initialize_fp.
+   */
+
+  pointer = &_CPU_Null_fp_context;
+  _CPU_Context_save_fp( &pointer );
+
+#endif
+
+  /*
+   *  Since no tasks have been created yet and no interrupts have occurred,
+   *  there is no way that the currently executing thread can have an
+   *  _ISR_Dispatch stack frame on its stack.
+   */
+  _CPU_ISR_Dispatch_disable = 0;
+}
+
+/*PAGE
+ *
+ *  _CPU_Context_Initialize
+ *
+ *  This kernel routine initializes the basic non-FP context area associated
+ *  with each thread.
+ *
+ *  Input parameters:
+ *    the_context  - pointer to the context area
+ *    stack_base   - address of memory for the SPARC
+ *    size         - size in bytes of the stack area
+ *    new_level    - interrupt level for this context area
+ *    entry_point  - the starting execution point for this this context
+ *    is_fp        - TRUE if this context is associated with an FP thread
+ *
+ *  Output parameters: NONE
+ */
+
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  void         *stack_base,
+  uint32_t          size,
+  uint32_t          new_level,
+  void             *entry_point,
+  bool              is_fp
+)
+{
+    uint64_t     stack_high;  /* highest "stack aligned" address */
+    uint32_t     the_size;
+
+    /*
+     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
+     *  based on the stack_high address.
+     */
+
+    stack_high = ((uint64_t)(stack_base) + size);
+    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
+
+    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
+
+    /*
+     *  See the README in this directory for a diagram of the stack.
+     */
+
+    the_context->o7    = ((uint64_t) entry_point) - 8;
+    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE - STACK_BIAS;
+    the_context->i6_fp = 0;
+
+    /* PSTATE used to be built here, but is no longer included in context */
+
+  /*
+   *  Since THIS thread is being created, there is no way that THIS
+   *  thread can have an _ISR_Dispatch stack frame on its stack.
+   */
+    the_context->isr_dispatch_disable = 0;
+}
--- a/cpukit/score/cpu/sparc64/preinstall.am
+++ b/cpukit/score/cpu/sparc64/preinstall.am
@@ -0,0 +1,41 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES = $(PREINSTALL_FILES)
+
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
+	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
+	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/sparc64.h: rtems/score/sparc64.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/sparc64.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/sparc64.h
+
+$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
+
+$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
+
--- a/cpukit/score/cpu/sparc64/rtems/asm.h
+++ b/cpukit/score/cpu/sparc64/rtems/asm.h
@@ -0,0 +1,102 @@
+/**
+ * @file rtems/asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ */
+
+/*
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#ifndef __ASM__
+#define __ASM__
+#endif
+
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/cpu.h>
+
+/*
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ */
+
+/* XXX __USER_LABEL_PREFIX__ and __REGISTER_PREFIX__ do not work on gcc 2.7.0 */
+/* XXX The following ifdef magic fixes the problem but results in a warning   */
+/* XXX when compiling assembly code.                                          */
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/* Use the right prefix for global labels.  */
+
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/* Use the right prefix for registers.  */
+
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+#define BEGIN_CODE_DCL .text
+#define END_CODE_DCL
+#define BEGIN_DATA_DCL .data
+#define END_DATA_DCL
+#define BEGIN_CODE .text
+#define END_CODE
+#define BEGIN_DATA
+#define END_DATA
+#define BEGIN_BSS
+#define END_BSS
+#define END
+
+/*
+ *  Following must be tailor for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+
+#define PUBLIC(sym) .globl SYM (sym)
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
--- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
--- a/cpukit/score/cpu/sparc64/rtems/score/sparc64.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/sparc64.h
@@ -0,0 +1,341 @@
+/**
+ * @file rtems/score/sparc64.h
+ */
+
+/*
+ *  This include file contains information pertaining to the SPARC 
+ *  processor family.
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  This file is based on the SPARC sparc.h file. Modifications are made 
+ *  to support the SPARC64 processor.
+ *    COPYRIGHT (c) 2010. Gedare Bloom.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_SPARC_H
+#define _RTEMS_SCORE_SPARC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the "sparc" family.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
+ *
+ *  Currently recognized feature flags:
+ *
+ *    + SPARC_HAS_FPU 
+ *        0 - no HW FPU
+ *        1 - has HW FPU (assumed to be compatible w/90C602)
+ *
+ *    + SPARC_HAS_BITSCAN 
+ *        0 - does not have scan instructions
+ *        1 - has scan instruction  (not currently implemented)
+ * 
+ *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
+ *        8 is the most common number supported by SPARC implementations.
+ *        SPARC_PSR_CWP_MASK is derived from this value.
+ */
+ 
+/*
+ *  Some higher end SPARCs have a bitscan instructions. It would
+ *  be nice to take advantage of them.  Right now, there is no
+ *  port to a CPU model with this feature and no (untested) code
+ *  that is based on this feature flag.
+ */
+
+#define SPARC_HAS_BITSCAN                0
+
+/*
+ *  This should be OK until a port to a higher end SPARC processor
+ *  is made that has more than 8 register windows.  If this cannot
+ *  be determined based on multilib settings (v7/v8/v9), then the
+ *  cpu_asm.S code that depends on this will have to move to libcpu.
+ *
+ *  SPARC v9 supports from 3 to 32 register windows.
+ *  N_REG_WINDOWS = 8 on UltraSPARC T1 (impl. dep. #2-V8).
+ */
+
+#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
+ 
+/*
+ *  This should be determined based on some soft float derived 
+ *  cpp predefine but gcc does not currently give us that information.
+ */
+
+
+#if defined(_SOFT_FLOAT)
+#define SPARC_HAS_FPU 0
+#else
+#define SPARC_HAS_FPU 1
+#endif
+
+#if SPARC_HAS_FPU
+#define CPU_MODEL_NAME "w/FPU"
+#else
+#define CPU_MODEL_NAME "w/soft-float"
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "SPARC"
+
+/*
+ *  Miscellaneous constants
+ */
+
+/* 
+ * The PSR is deprecated and deleted.
+ *
+ * The following registers represent fields of the PSR:
+ * 	PIL - Processor Interrupt Level register
+ * 	CWP - Current Window Pointer register
+ * 	VER - Version register
+ * 	CCR - Condition Codes Register
+ * 	PSTATE - Processor State register
+ */
+
+/*
+ *  PSTATE masks and starting bit positions
+ *
+ *  NOTE: Reserved bits are ignored.
+ */
+
+#define SPARC_PSTATE_AG_MASK   0x00000001   /* bit  0 */
+#define SPARC_PSTATE_IE_MASK   0x00000002   /* bit  1 */
+#define SPARC_PSTATE_PRIV_MASK 0x00000004   /* bit  2 */
+#define SPARC_PSTATE_AM_MASK   0x00000008   /* bit  3 */
+#define SPARC_PSTATE_PEF_MASK  0x00000010   /* bit  4 */
+#define SPARC_PSTATE_MM_MASK   0x00000040   /* bit  6 */
+#define SPARC_PSTATE_TLE_MASK  0x00000100   /* bit  8 */
+#define SPARC_PSTATE_CLE_MASK  0x00000200   /* bit  9 */
+
+#define SPARC_PSTATE_AG_BIT_POSITION   0   /* bit  0 */
+#define SPARC_PSTATE_IE_BIT_POSITION   1   /* bit  1 */
+#define SPARC_PSTATE_PRIV_BIT_POSITION 2   /* bit  2 */
+#define SPARC_PSTATE_AM_BIT_POSITION   3   /* bit  3 */
+#define SPARC_PSTATE_PEF_BIT_POSITION  4   /* bit  4 */
+#define SPARC_PSTATE_MM_BIT_POSITION   6   /* bit  6 */
+#define SPARC_PSTATE_TLE_BIT_POSITION  8   /* bit  8 */
+#define SPARC_PSTATE_CLE_BIT_POSITION  9   /* bit  9 */
+
+#define SPARC_FPRS_FEF_MASK     0x0100 /* bit 2 */
+#define SPARC_FPRS_FEF_BIT_POSITION 2      /* bit 2 */
+
+#define SPARC_TSTATE_IE_MASK  0x00000200  /* bit 9 */
+
+#define SPARC_SOFTINT_TM_MASK 0x00000001    /* bit 0 */
+#define SPARC_SOFTINT_SM_MASK 0x00010000    /* bit 16 */
+#define SPARC_SOFTINT_TM_BIT_POSITION    1       /* bit 0 */
+#define SPARC_SOFTINT_SM_BIT_POSITION    17      /* bit 16 */
+
+#define STACK_BIAS (2047)
+
+#ifdef ASM
+
+/* 
+ * To enable the FPU we need to set both PSTATE.pef and FPRS.fef
+ */
+
+#define sparc64_enable_FPU(rtmp1) \
+	rdpr %pstate, rtmp1; \
+	or rtmp1, SPARC_PSTATE_PEF_MASK, rtmp1; \
+	wrpr %g0, rtmp1, %pstate; \
+	rd %fprs, rtmp1; \
+	or rtmp1, SPARC_FPRS_FEF_MASK, rtmp1; \
+	wr %g0, rtmp1, %fprs
+
+
+#endif
+
+#ifndef ASM
+
+/*
+ *  Standard nop
+ */
+
+#define nop() \
+  do { \
+    asm volatile ( "nop" ); \
+  } while ( 0 )
+
+/*
+ *  Get and set the pstate
+ */
+
+#define sparc64_get_pstate( _pstate ) \
+  do { \
+     (_pstate) = 0; \
+     asm volatile( "rdpr %%pstate, %0" :  "=r" (_pstate) : "0" (_pstate) ); \
+  } while ( 0 )
+
+#define sparc64_set_pstate( _pstate ) \
+  do { \
+    asm volatile ( \
+      "wrpr  %g0, %0, %%pstate " : "=r" ((_pstate)) : "0" ((_pstate)) ); \
+  } while ( 0 )
+
+/*
+ * Get and set the PIL
+ */
+
+#define sparc64_get_pil( _pil ) \
+  do { \
+     (_pil) = 0; \
+     asm volatile( "rdpr %%pil, %0" :  "=r" (_pil) : "0" (_pil) ); \
+  } while ( 0 )
+
+#define sparc64_set_pil( _pil ) \
+  do { \
+    asm volatile ( "wrpr  %g0, %0, %%pil " : "=r" ((_pil)) : "0" ((_pil)) ); \
+  } while ( 0 )
+
+
+/*
+ *  Get and set the TBA
+ */
+
+#define sparc64_get_tba( _tba ) \
+  do { \
+     (_tba) = 0; /* to avoid unitialized warnings */ \
+     asm volatile( "rdpr %%tba, %0" :  "=r" (_tba) : "0" (_tba) ); \
+  } while ( 0 )
+
+#define sparc64_set_tba( _tba ) \
+  do { \
+     asm volatile( "wrpr %%g0, %0, %%tba" :  "=r" (_tba) : "0" (_tba) ); \
+  } while ( 0 )
+
+/*
+ *  Get and set the TL (trap level)
+ */
+
+#define sparc64_get_tl( _tl ) \
+  do { \
+     (_tl) = 0; /* to avoid unitialized warnings */ \
+     asm volatile( "rdpr %%tl, %0" :  "=r" (_tl) : "0" (_tl) ); \
+  } while ( 0 )
+
+#define sparc64_set_tl( _tl ) \
+  do { \
+     asm volatile( "wrpr %%g0, %0, %%tl" :  "=r" (_tl) : "0" (_tl) ); \
+  } while ( 0 )
+
+
+/*
+ * read the stick register
+ *
+ * Note: 
+ * stick asr=24, mnemonic=stick
+ * Note: stick does not appear to be a valid ASR for US3, although it is 
+ * implemented in US3i.
+ */
+#define sparc64_read_stick( _stick ) \
+  do { \
+    (_stick) = 0; \
+    asm volatile( "rd %%stick, %0" : "=r" (_stick) : "0" (_stick) );  \
+  } while ( 0 )
+
+/*
+ * write the stick_cmpr register 
+ *
+ * Note: 
+ * stick_cmpr asr=25, mnemonic=stick_cmpr
+ * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is 
+ * implemented in US3i.
+ */
+#define sparc64_write_stick_cmpr( _stick_cmpr ) \
+  do { \
+    asm volatile( "wr %%g0, %0, %%stick_cmpr" :  "=r" (_stick_cmpr)  \
+                                              :  "0" (_stick_cmpr) ); \
+  } while ( 0 )
+
+/*
+ * read the Tick register
+ */
+#define sparc64_read_tick( _tick ) \
+  do { \
+    (_tick) = 0; \
+    asm volatile( "rd %%tick, %0" : "=r" (_tick) : "0" (_tick) ); \
+  } while ( 0 )
+
+/*
+ * write the tick_cmpr register
+ */
+#define sparc64_write_tick_cmpr( _tick_cmpr ) \
+  do { \
+    asm volatile( "wr %%g0, %0, %%tick_cmpr" :  "=r" (_tick_cmpr)  \
+                                             :  "0" (_tick_cmpr) ); \
+  } while ( 0 )
+
+/* 
+ * Clear the softint register.
+ *
+ * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint
+ */
+#define sparc64_clear_interrupt_bits( _bit_mask ) \
+  do { \
+  asm volatile( "wr %%g0, %0, %%clear_softint" : "=r" (_bit_mask) \
+                                               : "0" (_bit_mask)); \
+  } while ( 0 )
+
+/************* DEPRECATED ****************/
+/* Note: Although the y register is deprecated, gcc still uses it */
+/*
+ *  Get and set the Y
+ */
+ 
+#define sparc_get_y( _y ) \
+  do { \
+    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
+  } while ( 0 )
+ 
+#define sparc_set_y( _y ) \
+  do { \
+    asm volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
+  } while ( 0 )
+
+/************* /DEPRECATED ****************/
+
+/*
+ *  Manipulate the interrupt level in the pstate 
+ */
+
+uint32_t sparc_disable_interrupts(void);
+void sparc_enable_interrupts(uint32_t);
+  
+#define sparc_flash_interrupts( _level ) \
+  do { \
+    register uint32_t   _ignored = 0; \
+    \
+    sparc_enable_interrupts( (_level) ); \
+    _ignored = sparc_disable_interrupts(); \
+  } while ( 0 )
+
+#define sparc64_get_interrupt_level( _level ) \
+  do { \
+    _level = 0; \
+    sparc64_get_pil( _level ); \
+  } while ( 0 )
+
+#endif /* !ASM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_SCORE_SPARC_H */
--- a/cpukit/score/cpu/sparc64/rtems/score/types.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/types.h
@@ -0,0 +1,51 @@
+/**
+ * @file rtems/score/types.h
+ */
+
+/*
+ *  This include file contains type definitions pertaining to the 
+ *  SPARC-v9 processor family.
+ *
+ *  COPYRIGHT (c) 1989-1999.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_TYPES_H
+#define _RTEMS_SCORE_TYPES_H
+
+#ifndef ASM
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+typedef uint16_t         Priority_Bit_map_control;
+typedef void sparc_isr;
+typedef void ( *sparc_isr_entry )( void );
+
+#ifdef RTEMS_DEPRECATED_TYPES
+typedef bool	boolean;              /* Boolean value   */
+typedef float	single_precision;     /* single precision float */
+typedef double	double_precision;     /* double precision float */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif