forked from Imagelibrary/rtems
Whitespace removal.
This commit is contained in:
Ralf Corsepius
@@ -159,7 +159,7 @@ typedef volatile uint32 vuint32 __attribute__((__may_alias__)); /* 32 bits */
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/*
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* Functions provided by mcf5xxx.s
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*/
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int asm_set_ipl (uint32);
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void mcf5xxx_wr_cacr (uint32);
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void mcf5xxx_wr_acr0 (uint32);
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@@ -447,11 +447,11 @@ extern uint8 __IPSBAR[];
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*********************************************************************/
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/* Read/Write access macros for general use */
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#define MCF5282_DMA0_SAR (*(vuint32 *)(&__IPSBAR[0x0100]))
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#define MCF5282_DMA0_DAR (*(vuint32 *)(&__IPSBAR[0x0104]))
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#define MCF5282_DMA0_DCR (*(vuint32 *)(&__IPSBAR[0x0108]))
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#define MCF5282_DMA0_BCR (*(vuint32 *)(&__IPSBAR[0x010C]))
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#define MCF5282_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x0110]))
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#define MCF5282_DMA0_SAR (*(vuint32 *)(&__IPSBAR[0x0100]))
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#define MCF5282_DMA0_DAR (*(vuint32 *)(&__IPSBAR[0x0104]))
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#define MCF5282_DMA0_DCR (*(vuint32 *)(&__IPSBAR[0x0108]))
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#define MCF5282_DMA0_BCR (*(vuint32 *)(&__IPSBAR[0x010C]))
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#define MCF5282_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x0110]))
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#define MCF5282_DMA1_SAR (*(vuint32 *)(&__IPSBAR[0x0140]))
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#define MCF5282_DMA1_DAR (*(vuint32 *)(&__IPSBAR[0x0144]))
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@@ -471,11 +471,11 @@ extern uint8 __IPSBAR[];
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#define MCF5282_DMA3_BCR (*(vuint32 *)(&__IPSBAR[0x01CC]))
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#define MCF5282_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x01D0]))
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#define MCF5282_DMA_SAR(x) (*(vuint32 *)(&__IPSBAR[0x0100+((x)*0x40)]))
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#define MCF5282_DMA_DAR(x) (*(vuint32 *)(&__IPSBAR[0x0104+((x)*0x40)]))
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#define MCF5282_DMA_DCR(x) (*(vuint32 *)(&__IPSBAR[0x0108+((x)*0x40)]))
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#define MCF5282_DMA_BCR(x) (*(vuint32 *)(&__IPSBAR[0x010C+((x)*0x40)]))
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#define MCF5282_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x0110+((x)*0x40)]))
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#define MCF5282_DMA_SAR(x) (*(vuint32 *)(&__IPSBAR[0x0100+((x)*0x40)]))
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#define MCF5282_DMA_DAR(x) (*(vuint32 *)(&__IPSBAR[0x0104+((x)*0x40)]))
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#define MCF5282_DMA_DCR(x) (*(vuint32 *)(&__IPSBAR[0x0108+((x)*0x40)]))
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#define MCF5282_DMA_BCR(x) (*(vuint32 *)(&__IPSBAR[0x010C+((x)*0x40)]))
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#define MCF5282_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x0110+((x)*0x40)]))
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/* Bit level definitions and macros */
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#define MCF5282_DMA_DCR_INT (0x80000000)
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@@ -502,12 +502,12 @@ extern uint8 __IPSBAR[];
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#define MCF5282_DMA_DCR_START (0x00010000)
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#define MCF5282_DMA_DCR_AT (0x00008000)
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#define MCF5282_DMA_DSR_CE (0x40)
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#define MCF5282_DMA_DSR_BES (0x20)
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#define MCF5282_DMA_DSR_BED (0x10)
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#define MCF5282_DMA_DSR_REQ (0x04)
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#define MCF5282_DMA_DSR_BSY (0x02)
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#define MCF5282_DMA_DSR_DONE (0x01)
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#define MCF5282_DMA_DSR_CE (0x40)
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#define MCF5282_DMA_DSR_BES (0x20)
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#define MCF5282_DMA_DSR_BED (0x10)
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#define MCF5282_DMA_DSR_REQ (0x04)
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#define MCF5282_DMA_DSR_BSY (0x02)
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#define MCF5282_DMA_DSR_DONE (0x01)
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/*********************************************************************
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*
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@@ -722,19 +722,19 @@ extern uint8 __IPSBAR[];
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#define MCF5282_QSPI_QMR_CPOL (0x0200)
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#define MCF5282_QSPI_QMR_CPHA (0x0100)
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#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QDLYR_SPE (0x8000)
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#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
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#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QWR_HALT (0x8000)
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#define MCF5282_QSPI_QWR_HALT (0x8000)
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#define MCF5282_QSPI_QWR_WREN (0x4000)
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#define MCF5282_QSPI_QWR_WRTO (0x2000)
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#define MCF5282_QSPI_QWR_CSIV (0x1000)
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#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
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#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
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#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
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#define MCF5282_QSPI_QIR_WCEFB (0x8000)
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#define MCF5282_QSPI_QIR_ABRTB (0x4000)
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#define MCF5282_QSPI_QIR_ABRTL (0x1000)
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@@ -764,35 +764,35 @@ extern uint8 __IPSBAR[];
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/* Read/Write access macros for general use */
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#define MCF5282_TIMER0_DTMR (*(vuint16 *)(&__IPSBAR[0x0400]))
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#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(&__IPSBAR[0x0402]))
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#define MCF5282_TIMER0_DTXMR (*(vuint8 *)(&__IPSBAR[0x0402]))
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#define MCF5282_TIMER0_DTER (*(vuint8 *)(&__IPSBAR[0x0403]))
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#define MCF5282_TIMER0_DTRR (*(vuint32 *)(&__IPSBAR[0x0404]))
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#define MCF5282_TIMER0_DTCR (*(vuint32 *)(&__IPSBAR[0x0408]))
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#define MCF5282_TIMER0_DTCN (*(vuint32 *)(&__IPSBAR[0x040C]))
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#define MCF5282_TIMER1_DTMR (*(vuint16 *)(&__IPSBAR[0x0440]))
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#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(&__IPSBAR[0x0442]))
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#define MCF5282_TIMER1_DTXMR (*(vuint8 *)(&__IPSBAR[0x0442]))
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#define MCF5282_TIMER1_DTER (*(vuint8 *)(&__IPSBAR[0x0443]))
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#define MCF5282_TIMER1_DTRR (*(vuint32 *)(&__IPSBAR[0x0444]))
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#define MCF5282_TIMER1_DTCR (*(vuint32 *)(&__IPSBAR[0x0448]))
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#define MCF5282_TIMER1_DTCN (*(vuint32 *)(&__IPSBAR[0x044C]))
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#define MCF5282_TIMER2_DTMR (*(vuint16 *)(&__IPSBAR[0x0480]))
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#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(&__IPSBAR[0x0482]))
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#define MCF5282_TIMER2_DTXMR (*(vuint8 *)(&__IPSBAR[0x0482]))
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#define MCF5282_TIMER2_DTER (*(vuint8 *)(&__IPSBAR[0x0483]))
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#define MCF5282_TIMER2_DTRR (*(vuint32 *)(&__IPSBAR[0x0484]))
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#define MCF5282_TIMER2_DTCR (*(vuint32 *)(&__IPSBAR[0x0488]))
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#define MCF5282_TIMER2_DTCN (*(vuint32 *)(&__IPSBAR[0x048C]))
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#define MCF5282_TIMER3_DTMR (*(vuint16 *)(&__IPSBAR[0x04C0]))
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#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(&__IPSBAR[0x04C2]))
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#define MCF5282_TIMER3_DTXMR (*(vuint8 *)(&__IPSBAR[0x04C2]))
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#define MCF5282_TIMER3_DTER (*(vuint8 *)(&__IPSBAR[0x04C3]))
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#define MCF5282_TIMER3_DTRR (*(vuint32 *)(&__IPSBAR[0x04C4]))
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#define MCF5282_TIMER3_DTCR (*(vuint32 *)(&__IPSBAR[0x04C8]))
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#define MCF5282_TIMER3_DTCN (*(vuint32 *)(&__IPSBAR[0x04CC]))
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#define MCF5282_TIMER_DTMR(x) (*(vuint16 *)(&__IPSBAR[0x0400+((x)*0x40)]))
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#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x0402+((x)*0x40)]))
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#define MCF5282_TIMER_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x0402+((x)*0x40)]))
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#define MCF5282_TIMER_DTER(x) (*(vuint8 *)(&__IPSBAR[0x0403+((x)*0x40)]))
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#define MCF5282_TIMER_DTRR(x) (*(vuint32 *)(&__IPSBAR[0x0404+((x)*0x40)]))
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#define MCF5282_TIMER_DTCR(x) (*(vuint32 *)(&__IPSBAR[0x0408+((x)*0x40)]))
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@@ -1541,7 +1541,7 @@ extern uint8 __IPSBAR[];
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#define MCF5282_GPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
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#define MCF5282_GPIO_PEPAR_PEPA0(x) (((x)&0x3))
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#define MCF5282_GPIO_PFPAR_PFPA7 (0x80)
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#define MCF5282_GPIO_PFPAR_PFPA7 (0x80)
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#define MCF5282_GPIO_PFPAR_PFPA6 (0x40)
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#define MCF5282_GPIO_PFPAR_PFPA5 (0x20)
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@@ -1787,7 +1787,7 @@ extern uint8 __IPSBAR[];
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#define MCF5282_WTM_WSR (*(vuint16 *)(&__IPSBAR[0x140006]))
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/* Bit level definitions and macros */
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#define MCF5282_WTM_WCR_WAIT (0x0008)
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#define MCF5282_WTM_WCR_WAIT (0x0008)
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#define MCF5282_WTM_WCR_DOZE (0x0004)
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#define MCF5282_WTM_WCR_HALTED (0x0002)
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#define MCF5282_WTM_WCR_EN (0x0001)
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@@ -1805,7 +1805,7 @@ extern uint8 __IPSBAR[];
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#define MCF5282_PIT0_PCSR (*(vuint16 *)(&__IPSBAR[0x150000]))
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#define MCF5282_PIT0_PMR (*(vuint16 *)(&__IPSBAR[0x150002]))
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#define MCF5282_PIT0_PCNTR (*(vuint16 *)(&__IPSBAR[0x150004]))
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#define MCF5282_PIT1_PCSR (*(vuint16 *)(&__IPSBAR[0x160000]))
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#define MCF5282_PIT1_PMR (*(vuint16 *)(&__IPSBAR[0x160002]))
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#define MCF5282_PIT1_PCNTR (*(vuint16 *)(&__IPSBAR[0x160004]))
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@@ -1910,9 +1910,9 @@ extern uint8 __IPSBAR[];
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#define MCF5282_QADC_QASR0_PF1 (0x4000)
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#define MCF5282_QADC_QASR0_CF2 (0x2000)
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#define MCF5282_QADC_QASR0_PF2 (0x1000)
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#define MCF5282_QADC_QASR0_TOR1 (0x0800)
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#define MCF5282_QADC_QASR0_TOR1 (0x0800)
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#define MCF5282_QADC_QASR0_TOR2 (0x0400)
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#define MCF5282_QADC_CCW_P (0x0200)
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#define MCF5282_QADC_CCW_BYP (0x0100)
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#define MCF5282_QADC_CCW_IST(x) (((x)&0x0003)<<14)
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8
c/src/lib/libcpu/m68k/shared/cache/cache.c
vendored
8
c/src/lib/libcpu/m68k/shared/cache/cache.c
vendored
@@ -7,12 +7,12 @@
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#include <rtems.h>
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#include "cache_.h"
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/*
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/*
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* Since the cacr is common to all mc680x0, provide macros
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* for masking values in that register.
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*/
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/*
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/*
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* Used to clear bits in the cacr.
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*/
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#define _CPU_CACR_AND(mask) \
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@@ -26,7 +26,7 @@
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}
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/*
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/*
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* Used to set bits in the cacr.
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*/
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#define _CPU_CACR_OR(mask) \
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@@ -39,7 +39,7 @@
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: "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \
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}
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/*
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* CACHE MANAGER: The following functions are CPU-specific.
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* They provide the basic implementation for the rtems_* cache
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