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riscv: Add LADDR assembler define

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An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.
This commit is contained in:
Sebastian Huber
2018-07-06 11:07:20 +02:00
parent dd32e2b2d0
commit bca36d986b
3 changed files with 20 additions and 10 deletions
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16
bsps/riscv/riscv/start/start.S
View File

@@ -50,12 +50,12 @@ SYM(_start):
/* Load global pointer */ /* Load global pointer */
.option push .option push
.option norelax .option norelax
la gp, __global_pointer$ LADDR gp, __global_pointer$
.option pop .option pop
#ifdef RTEMS_SMP #ifdef RTEMS_SMP
csrr s0, mhartid csrr s0, mhartid
la t0, _Per_CPU_Information LADDR t0, _Per_CPU_Information
slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2 slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2
add t0, t0, t1 add t0, t0, t1
csrw mscratch, t0 csrw mscratch, t0
@@ -63,25 +63,25 @@ SYM(_start):
#endif #endif
/* load stack and frame pointers */ /* load stack and frame pointers */
la sp, _Configuration_Interrupt_stack_area_end LADDR sp, _Configuration_Interrupt_stack_area_end
#ifdef BSP_START_COPY_FDT_FROM_U_BOOT #ifdef BSP_START_COPY_FDT_FROM_U_BOOT
mv a0, a1 mv a0, a1
call bsp_fdt_copy call bsp_fdt_copy
#endif #endif
la t0, ISR_Handler LADDR t0, ISR_Handler
csrw mtvec, t0 csrw mtvec, t0
/* Clear .bss */ /* Clear .bss */
la a0, bsp_section_bss_begin LADDR a0, bsp_section_bss_begin
li a1, 0 li a1, 0
la a2, bsp_section_bss_size LADDR a2, bsp_section_bss_size
call memset call memset
#ifdef RTEMS_SMP #ifdef RTEMS_SMP
/* Give go to secondary processors */ /* Give go to secondary processors */
la t0, .Lsecondary_processor_go LADDR t0, .Lsecondary_processor_go
fence iorw,ow fence iorw,ow
amoswap.w zero, zero, 0(t0) amoswap.w zero, zero, 0(t0)
#endif #endif
@@ -95,7 +95,7 @@ SYM(_start):
#ifdef RTEMS_SMP #ifdef RTEMS_SMP
/* Wait for go issued by the boot processor (mhartid == 0) */ /* Wait for go issued by the boot processor (mhartid == 0) */
.Lwait_for_go: .Lwait_for_go:
la t0, .Lsecondary_processor_go LADDR t0, .Lsecondary_processor_go
.Lwait_for_go_again: .Lwait_for_go_again:
lw t1, 0(t0) lw t1, 0(t0)
fence iorw, iorw fence iorw, iorw

12
cpukit/score/cpu/riscv/include/rtems/asm.h
View File

@@ -131,6 +131,16 @@
#endif /* __riscv_xlen */ #endif /* __riscv_xlen */
#ifdef __riscv_cmodel_medany
#define LADDR lla
#else /* !__riscv_cmodel_medany */
#define LADDR la
#endif /* __riscv_cmodel_medany */
#if __riscv_flen == 32 #if __riscv_flen == 32
#define FLREG flw #define FLREG flw
@@ -167,7 +177,7 @@
#ifdef RTEMS_SMP #ifdef RTEMS_SMP
csrr \REG, mscratch csrr \REG, mscratch
#else #else
la \REG, _Per_CPU_Information LADDR \REG, _Per_CPU_Information
#endif #endif
.endm .endm

2
cpukit/score/cpu/riscv/riscv-exception-handler.S
View File

@@ -128,7 +128,7 @@ SYM(ISR_Handler):
mv a1, sp mv a1, sp
/* calculate the offset */ /* calculate the offset */
la t5, bsp_start_vector_table_begin LADDR t5, bsp_start_vector_table_begin
#if __riscv_xlen == 32 #if __riscv_xlen == 32
slli t6, a0, 2 slli t6, a0, 2
#else /* xlen = 64 */ #else /* xlen = 64 */