forked from Imagelibrary/rtems
bca36d986b
An address must be loaded to a register according to the code model. Add LADDR define for use in assembler code. Update #3433.
252 lines
7.6 KiB
ArmAsm
252 lines
7.6 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup ScoreCPU
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*
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* @brief RISC-V exception support implementation.
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*/
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/*
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* Copyright (c) 2018 embedded brains GmbH
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* Copyright (c) 2015 University of York.
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* Hesham Almatary <hesham@alumni.york.ac.uk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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EXTERN(bsp_start_vector_table_begin)
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EXTERN(_Thread_Dispatch)
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PUBLIC(ISR_Handler)
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.section .text, "ax", @progbits
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.align 2
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TYPE_FUNC(ISR_Handler)
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SYM(ISR_Handler):
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addi sp, sp, -CPU_INTERRUPT_FRAME_SIZE
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/* Save */
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SREG a0, RISCV_INTERRUPT_FRAME_A0(sp)
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SREG a1, RISCV_INTERRUPT_FRAME_A1(sp)
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SREG a2, RISCV_INTERRUPT_FRAME_A2(sp)
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SREG s0, RISCV_INTERRUPT_FRAME_S0(sp)
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csrr a0, mcause
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csrr a1, mstatus
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csrr a2, mepc
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GET_SELF_CPU_CONTROL s0
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SREG s1, RISCV_INTERRUPT_FRAME_S1(sp)
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#if __riscv_flen > 0
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frcsr s1
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#endif
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SREG ra, RISCV_INTERRUPT_FRAME_RA(sp)
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SREG a3, RISCV_INTERRUPT_FRAME_A3(sp)
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SREG a4, RISCV_INTERRUPT_FRAME_A4(sp)
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SREG a5, RISCV_INTERRUPT_FRAME_A5(sp)
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SREG a6, RISCV_INTERRUPT_FRAME_A6(sp)
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SREG a7, RISCV_INTERRUPT_FRAME_A7(sp)
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SREG t0, RISCV_INTERRUPT_FRAME_T0(sp)
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SREG t1, RISCV_INTERRUPT_FRAME_T1(sp)
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SREG t2, RISCV_INTERRUPT_FRAME_T2(sp)
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SREG t3, RISCV_INTERRUPT_FRAME_T3(sp)
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SREG t4, RISCV_INTERRUPT_FRAME_T4(sp)
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SREG t5, RISCV_INTERRUPT_FRAME_T5(sp)
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SREG t6, RISCV_INTERRUPT_FRAME_T6(sp)
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SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
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SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp)
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#if __riscv_flen > 0
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sw s1, RISCV_INTERRUPT_FRAME_FCSR(sp)
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FSREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp)
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FSREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp)
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FSREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp)
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FSREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp)
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FSREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp)
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FSREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp)
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FSREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp)
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FSREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp)
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FSREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp)
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FSREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp)
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FSREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp)
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FSREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp)
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FSREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp)
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FSREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp)
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FSREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp)
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FSREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp)
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FSREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp)
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FSREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp)
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FSREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp)
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FSREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp)
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#endif
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/* FIXME Only handle interrupts for now (MSB = 1) */
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andi a0, a0, 0xf
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/* Increment interrupt nest and thread dispatch disable level */
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lw t0, PER_CPU_ISR_NEST_LEVEL(s0)
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lw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
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addi t2, t0, 1
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addi t1, t1, 1
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sw t2, PER_CPU_ISR_NEST_LEVEL(s0)
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sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
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CLEAR_RESERVATIONS s0
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/* Keep sp (Exception frame address) in s1 */
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mv s1, sp
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/* Call the exception handler from vector table */
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/* First function arg for C handler is vector number,
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* and the second is a pointer to exception frame.
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* a0/mcause/vector number is already loaded above */
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mv a1, sp
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/* calculate the offset */
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LADDR t5, bsp_start_vector_table_begin
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#if __riscv_xlen == 32
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slli t6, a0, 2
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#else /* xlen = 64 */
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slli t6, a0, 3
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#endif
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add t5, t5, t6
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LREG t5, (t5)
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/* Switch to interrupt stack if necessary */
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bnez t0, .Linterrupt_stack_switch_done
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LREG sp, PER_CPU_INTERRUPT_STACK_HIGH(s0)
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.Linterrupt_stack_switch_done:
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jalr t5
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/* Load some per-CPU variables */
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lw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
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lbu t1, PER_CPU_DISPATCH_NEEDED(s0)
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lw t2, PER_CPU_ISR_DISPATCH_DISABLE(s0)
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lw t3, PER_CPU_ISR_NEST_LEVEL(s0)
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/* Restore stack pointer */
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mv sp, s1
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/* Decrement levels and determine thread dispatch state */
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xor t1, t1, t0
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addi t0, t0, -1
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or t1, t1, t0
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or t1, t1, t2
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addi t3, t3, -1
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/* Store thread dispatch disable and ISR nest levels */
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sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
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sw t3, PER_CPU_ISR_NEST_LEVEL(s0)
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/*
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* Check thread dispatch necessary, ISR dispatch disable and thread
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* dispatch disable level.
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*/
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bnez t1, .Lthread_dispatch_done
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.Ldo_thread_dispatch:
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/* Set ISR dispatch disable and thread dispatch disable level to one */
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li t0, 1
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sw t0, PER_CPU_ISR_DISPATCH_DISABLE(s0)
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sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
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/* Call _Thread_Do_dispatch(), this function will enable interrupts */
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mv a0, s0
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li a1, RISCV_MSTATUS_MIE
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call _Thread_Do_dispatch
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/* Disable interrupts */
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csrrc zero, mstatus, RISCV_MSTATUS_MIE
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#ifdef RTEMS_SMP
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GET_SELF_CPU_CONTROL s0
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#endif
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/* Check if we have to do the thread dispatch again */
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lbu t0, PER_CPU_DISPATCH_NEEDED(s0)
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bnez t0, .Ldo_thread_dispatch
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/* We are done with thread dispatching */
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sw zero, PER_CPU_ISR_DISPATCH_DISABLE(s0)
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.Lthread_dispatch_done:
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/* Restore */
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LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
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LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp)
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LREG a2, RISCV_INTERRUPT_FRAME_A2(sp)
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LREG s0, RISCV_INTERRUPT_FRAME_S0(sp)
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LREG s1, RISCV_INTERRUPT_FRAME_S1(sp)
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LREG ra, RISCV_INTERRUPT_FRAME_RA(sp)
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LREG a3, RISCV_INTERRUPT_FRAME_A3(sp)
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LREG a4, RISCV_INTERRUPT_FRAME_A4(sp)
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LREG a5, RISCV_INTERRUPT_FRAME_A5(sp)
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LREG a6, RISCV_INTERRUPT_FRAME_A6(sp)
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LREG a7, RISCV_INTERRUPT_FRAME_A7(sp)
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LREG t0, RISCV_INTERRUPT_FRAME_T0(sp)
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LREG t1, RISCV_INTERRUPT_FRAME_T1(sp)
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LREG t2, RISCV_INTERRUPT_FRAME_T2(sp)
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LREG t3, RISCV_INTERRUPT_FRAME_T3(sp)
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LREG t4, RISCV_INTERRUPT_FRAME_T4(sp)
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LREG t5, RISCV_INTERRUPT_FRAME_T5(sp)
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LREG t6, RISCV_INTERRUPT_FRAME_T6(sp)
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csrw mstatus, a0
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csrw mepc, a1
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#if __riscv_flen > 0
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lw a0, RISCV_INTERRUPT_FRAME_FCSR(sp)
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FLREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp)
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FLREG ft1, RISCV_INTERRUPT_FRAME_FT1(sp)
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FLREG ft2, RISCV_INTERRUPT_FRAME_FT2(sp)
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FLREG ft3, RISCV_INTERRUPT_FRAME_FT3(sp)
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FLREG ft4, RISCV_INTERRUPT_FRAME_FT4(sp)
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FLREG ft5, RISCV_INTERRUPT_FRAME_FT5(sp)
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FLREG ft6, RISCV_INTERRUPT_FRAME_FT6(sp)
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FLREG ft7, RISCV_INTERRUPT_FRAME_FT7(sp)
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FLREG ft8, RISCV_INTERRUPT_FRAME_FT8(sp)
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FLREG ft9, RISCV_INTERRUPT_FRAME_FT9(sp)
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FLREG ft10, RISCV_INTERRUPT_FRAME_FT10(sp)
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FLREG ft11, RISCV_INTERRUPT_FRAME_FT11(sp)
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FLREG fa0, RISCV_INTERRUPT_FRAME_FA0(sp)
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FLREG fa1, RISCV_INTERRUPT_FRAME_FA1(sp)
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FLREG fa2, RISCV_INTERRUPT_FRAME_FA2(sp)
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FLREG fa3, RISCV_INTERRUPT_FRAME_FA3(sp)
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FLREG fa4, RISCV_INTERRUPT_FRAME_FA4(sp)
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FLREG fa5, RISCV_INTERRUPT_FRAME_FA5(sp)
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FLREG fa6, RISCV_INTERRUPT_FRAME_FA6(sp)
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FLREG fa7, RISCV_INTERRUPT_FRAME_FA7(sp)
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fscsr a0
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#endif
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LREG a0, RISCV_INTERRUPT_FRAME_A0(sp)
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LREG a1, RISCV_INTERRUPT_FRAME_A1(sp)
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addi sp, sp, CPU_INTERRUPT_FRAME_SIZE
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mret
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