2009-05-05 Michael Walle <michael@walle.cc>

* cpu_asm.S, irq.c, rtems/score/cpu.h: Add lm32 gdb stub support.

cpukit/score/cpu/lm32/ChangeLog

@@ -1,3 +1,7 @@
+2009-05-05	Michael Walle <michael@walle.cc>
+
+	* cpu_asm.S, irq.c, rtems/score/cpu.h: Add lm32 gdb stub support.
+
 2009-04-14	Michael Walle <michael@walle.cc>
 
 	* cpu.h: corrected the registers in Context_Control and

cpukit/score/cpu/lm32/cpu_asm.S

@@ -54,6 +54,21 @@ _CPU_Context_switch:
     sw      (r1+72), ra
     rcsr    r3, IE
     sw      (r1+76), r3
+    .extern _exception_stack_frame
+    mvhi    r3, hi(_exception_stack_frame)
+    ori     r3, r3, lo(_exception_stack_frame)
+    lw      r4, (r3+0)
+    be      r4, r0, 2f
+1:
+    lw      r5, (r4+44)
+    sw      (r3+0), r0
+    bi      3f
+2:
+    mvhi    r5, hi(_Thread_Dispatch)
+    ori     r5, r5, lo(_Thread_Dispatch)
+3:
+    sw      (r1+80), r5
+
 _CPU_Context_switch_restore:
     lw      r11, (r2+0)   /* r2 is the second argument */
     lw      r12, (r2+4)

cpukit/score/cpu/lm32/irq.c

@@ -28,11 +28,14 @@
   unsigned long    *_old_stack_ptr;
 #endif
 
+unsigned long *_exception_stack_frame;
+
 register unsigned long  *stack_ptr asm("sp");
 
 void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
 {
   register uint32_t   level;
+  _exception_stack_frame = NULL;
 
   /* Interrupts are disabled upon entry to this Handler */
 
@@ -77,7 +80,15 @@ void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
 
   if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
     _ISR_Signals_to_thread_executing = FALSE;
+
+    /* save off our stack frame so the context switcher can get to it */
+    _exception_stack_frame = ifr;
+
     _Thread_Dispatch();
+
+    /* and make sure its clear in case we didn't dispatch. if we did, its
+     * already cleared */
+    _exception_stack_frame = NULL;
   }
 }
 

cpukit/score/cpu/lm32/rtems/score/cpu.h

@@ -482,6 +482,7 @@ typedef struct {
   uint32_t sp;
   uint32_t ra;
   uint32_t ie;
+  uint32_t epc;
 } Context_Control;
 
 /**