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added support for COBRA5475 board

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This commit is contained in:
Thomas Doerfler
2009-10-16 12:53:50 +00:00
parent 5380482008
commit a9d0c6ecd8
12 changed files with 347 additions and 18 deletions
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9
c/src/lib/libbsp/m68k/genmcf548x/ChangeLog
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@@ -1,3 +1,12 @@
2009-10-16 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* Makefile.am, README, configure.ac,
* console/console.c, start/start.S startup/init548x.c,
* startup/linkcmds, startup/linkcmds.m5484FireEngine.flash,
* make/custom/COBRA5475.cfg, startup/linkcmds.COBRA5475:
Added support for COBRA5475 board
2009-10-15 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
* network/network.c: add PHY control support

2
c/src/lib/libbsp/m68k/genmcf548x/Makefile.am
View File

@@ -24,7 +24,7 @@ noinst_LIBRARIES = libbspstart.a
libbspstart_a_SOURCES = start/start.S
project_lib_DATA = start.$(OBJEXT)
dist_project_lib_DATA += startup/linkcmds
dist_project_lib_DATA += startup/linkcmds startup/linkcmds.m5484FireEngine.flash startup/linkcmds.COBRA5475
noinst_LIBRARIES += libbsp.a
libbsp_a_SOURCES =

65
c/src/lib/libbsp/m68k/genmcf548x/README
View File

@@ -45,7 +45,12 @@
Description: Generic mcf548x BSP
============
The genmcf548x supports several boards based on the Freescale MCF547x/8x
ColdFire microcontrollers
Supported Hardware: mcf5484FireEngine
=============================
CPU: MCF548x, 200MHz
XLB: 100 MHz, which is the main clock for all onchip peripherals
RAM: 64M (m5484FireEngine)
@@ -53,9 +58,18 @@ Boot-Flash: 2M (m5484FireEngine)
Code-Flash: 16M (m5484FireEngine)
Core-SRAM: 8K
Core-SysRAM: 32K
Boot-Monitor:None
Supported Hardware: COBRA5475
=============================
CPU: MCF5475, 266MHz
XLB: 132 MHz, which is the main clock for all onchip peripherals
RAM: 128M
Boot-Flash: 32M
Core-SRAM: 8K
Core-SysRAM: 32K
Boot-Monitor:DBug
The genmcf548x supports the Fresscale m5484FireEngine EVB.
ACKNOWLEDGEMENTS:
=================
@@ -74,9 +88,9 @@ and the work of
BSP INFO:
=========
BSP NAME: genmcf548x
BOARD: m5484FireEngine (freescale),
BOARD: various MCF547x/8x based boards
CPU FAMILY: ColdFire 548x
CPU: MCF5484
CPU: MCF5475/MCF5484
FPU: MCF548x FPU, context switch supported by RTEMS multitasking
EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
@@ -85,7 +99,7 @@ PERIPHERALS
TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
RESOLUTION: System tick 10 millieconds (via SLT0)
SERIAL PORTS: Internal PSC 0-3
NETWORKING: Internal 10/100MHz FEC (not supported yet)
NETWORKING: Internal 10/100MHz FEC on two channels
DRIVER INFORMATION
==================
@@ -104,9 +118,9 @@ STOP BITS: 1
MODES: Interrupt driven (polled mode alternatively)
Memory map as set up by BSP initialization
----------------------------------------------------------------------
m5484FireEngine:
Memory map of m5484FireEngine as set up by BSP initialization:
+--------------------------------------------------+
0000 0000 | 64 MByte SDRAM (external) | 03FF FFFF
@@ -148,6 +162,41 @@ FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
| | FFFF FFFF
+--------------------------------------------------+
----------------------------------------------------------------------
Memory map for COBRA5475 as set up by DBug:
+--------------------------------------------------+
F000 0000 | 128 MByte SDRAM (external) |
. .
. (first 256KByte reserved for DBug) .
. . F03F FFFF
F040 0000 | |
. .
. .
. .
| | F7FF FFFF
+--------------------------------------------------+
FC00 0000 | 32M code flash (external) |
. .
. .
. .
| | FDFF FFFF
+--------------------------------------------------+
FE00 0000 | internal per. registers via MBAR |
. .
. .
. .
| | FE03 FFFF
+--------------------------------------------------+
FF00 0000 | 8K core SRAM (internal) |
. .
. .
. .
| | FF00 1FFF
+--------------------------------------------------+
============================================================================
Interrupt map
@@ -167,7 +216,7 @@ FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 3 | PSC 0 | PSC 1 | PSC 2 | PSC 3 | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 2 | | | | | | | | |
| 2 | | | | | FEC0/1 | MCDMA | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+

17
c/src/lib/libbsp/m68k/genmcf548x/configure.ac
View File

@@ -19,15 +19,30 @@ RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET([BSP_CPU_CLOCK_SPEED],[COBRA5475],[132000000])
RTEMS_BSPOPTS_SET([BSP_CPU_CLOCK_SPEED],[m5484FireEngine],[100000000])
RTEMS_BSPOPTS_SET([BSP_CPU_CLOCK_SPEED],[*],[100000000])
RTEMS_BSPOPTS_HELP([BSP_CPU_CLOCK_SPEED],
[Use a clock speed of 100000000 for the m5484FireEngine board])
[The bus clock to be used inside the mcf54xx])
RTEMS_BSPOPTS_SET([M5484FIREENGINE],[m5484FireEngine],[1])
RTEMS_BSPOPTS_HELP([M5484FIREENGINE],
[If defined, use custom settings for the m5484FireEngine BSP.])
RTEMS_BSPOPTS_SET([BSP_CONSOLE_BAUD],[COBRA5475],[19200])
RTEMS_BSPOPTS_SET([BSP_CONSOLE_BAUD],[*],[9600])
RTEMS_BSPOPTS_HELP([BSP_CONSOLE_BAUD],[initial baudrate for UARTs])
RTEMS_BSPOPTS_SET([HAS_DBUG],[COBRA5475],[1])
RTEMS_BSPOPTS_SET([HAS_DBUG],[*],[0])
RTEMS_BSPOPTS_HELP([HAS_DBUG],
[If defined, we will not boot from RESET, but from Freescale DBug monitor.])
RTEMS_BSPOPTS_SET([HAS_LOW_LEVEL_INIT],[m5484FireEngine],[1])
RTEMS_BSPOPTS_SET([HAS_LOW_LEVEL_INIT],[*],[0])
RTEMS_BSPOPTS_HELP([HAS_DBUG],
[If defined, we will do all the low level init of the chip (like bus/memory...).])
RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
# Explicitly list all Makefiles here

4
c/src/lib/libbsp/m68k/genmcf548x/console/console.c
View File

@@ -111,7 +111,7 @@ struct IntUartInfoStruct IntUartInfo[MAX_UART_INFO];
static int GetBaud( int baudHandle )
{
int baud = 9600;
int baud = BSP_CONSOLE_BAUD;
switch(baudHandle)
{
case B0:
@@ -291,7 +291,7 @@ static int
IntUartSetAttributes(int minor, const struct termios *t)
{
/* set default index values */
int baud = (int)9600;
int baud = (int)BSP_CONSOLE_BAUD;
int databits = (int)MCF548X_PSC_MR_BC_8;
int parity = (int)MCF548X_PSC_MR_PM_NONE;
int stopbits = (int)MCF548X_PSC_MR_SB_STOP_BITS_1;

14
c/src/lib/libbsp/m68k/genmcf548x/make/custom/COBRA5475.cfg Normal file
View File

@@ -0,0 +1,14 @@
#
# Config file for COBRA5475 module
#
# $Id$
#
#
# All genmcf548x configurations share the same base file, only a few
# parameters differ.
#
RTEMS_LINKCMDS=linkcmds.COBRA5475
include $(RTEMS_ROOT)/make/custom/genmcf548x.cfg

8
c/src/lib/libbsp/m68k/genmcf548x/preinstall.am
View File

@@ -65,3 +65,11 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
$(PROJECT_LIB)/linkcmds.m5484FireEngine.flash: startup/linkcmds.m5484FireEngine.flash $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.m5484FireEngine.flash
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.m5484FireEngine.flash
$(PROJECT_LIB)/linkcmds.COBRA5475: startup/linkcmds.COBRA5475 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.COBRA5475
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.COBRA5475

3
c/src/lib/libbsp/m68k/genmcf548x/start/start.S
View File

@@ -58,7 +58,6 @@
.extern mcf548x_init
.extern boot_card
.extern _SpInit
.extern _InitPc
/*===============================================================*\
| Global symbols |
@@ -77,7 +76,7 @@
PUBLIC (InterruptVectorTable)
SYM(InterruptVectorTable):
INITSP: .long _SpInit /* Initial SP */
INITPC: .long _InitPc /* Initial PC */
INITPC: .long start /* Initial PC */
vector002: .long asm_default_interrupt /* Access Error */
vector003: .long asm_default_interrupt /* Address Error */
vector004: .long asm_default_interrupt /* Illegal Instruction */

11
c/src/lib/libbsp/m68k/genmcf548x/startup/init548x.c
View File

@@ -46,6 +46,7 @@
#include <rtems.h>
#include <bsp.h>
#if defined(HAS_LOW_LEVEL_INIT)
#define SYSTEM_PERIOD 10 /* system bus period in ns */
/* SDRAM Timing Parameters */
@@ -55,6 +56,7 @@
#define SDRAM_TRP 20 /* in ns */
#define SDRAM_TRFC 75 /* in ns */
#define SDRAM_TREFI 7800 /* in ns */
#endif /* defined(HAS_LOW_LEVEL_INIT) */
extern uint8_t _DataRom[];
extern uint8_t _DataRam[];
@@ -78,8 +80,7 @@ void mcf548x_init(void)
uint32_t n;
uint8_t *dp, *sp;
/* set XLB arbiter timeouts */
#ifdef M5484FIREENGINE
#if defined(HAS_LOW_LEVEL_INIT)
/* set XLB arbiter timeouts */
MCF548X_XLB_ADRTO = 0x00000100;
MCF548X_XLB_DATTO = 0x00000100;
@@ -87,8 +88,10 @@ void mcf548x_init(void)
#endif
gpio_init();
#if defined(HAS_LOW_LEVEL_INIT)
fbcs_init();
sdramc_init();
#endif /* defined(HAS_LOW_LEVEL_INIT) */
/* Copy the vector table to RAM */
if (_VectorRam != InterruptVectorTable)
@@ -122,6 +125,7 @@ void mcf548x_init(void)
}
/********************************************************************/
#if defined(HAS_LOW_LEVEL_INIT)
void
fbcs_init (void)
{
@@ -184,8 +188,10 @@ if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))
#endif
}
#endif defined(HAS_LOW_LEVEL_INIT)
/********************************************************************/
#if defined(HAS_LOW_LEVEL_INIT)
void
sdramc_init (void)
{
@@ -287,6 +293,7 @@ sdramc_init (void)
}
}
#endif /* defined(HAS_LOW_LEVEL_INIT) */
/********************************************************************/
void

1
c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds
View File

@@ -70,7 +70,6 @@ _DataEnd = DEFINED(_DataEnd) ? _DataEnd : _data_dest_end;
_BssStart = DEFINED(_BssStart) ? _BssStart : _clear_start;
_BssEnd = DEFINED(_BssEnd) ? _BssEnd : _clear_end;
_SpInit = DEFINED(_SpInit) ? _SpInit : _EndInitStackSpace;
_InitPc = DEFINED(_InitPc) ? _InitPc : _SdramBase + 0x400;
_InitStackSize = DEFINED(StackSize) ? StackSize : 0x800; /* 2 kB */
_TopRamReserved = DEFINED(_TopRamReserved) ? _TopRamReserved : 0;

230
c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.COBRA5475 Normal file
View File

@@ -0,0 +1,230 @@
/*===============================================================*\
| Project: RTEMS generic mcf548x BSP |
+-----------------------------------------------------------------+
| File: linkcmds.COBRA5475 |
+-----------------------------------------------------------------+
| The file contains the linker directives for the generic MCF548x |
| BSP to be used with an COBRA5475 board to load and execute |
| code in the RAM. |
+-----------------------------------------------------------------+
| Copyright (c) 2007 |
| Embedded Brains GmbH |
| Obere Lagerstr. 30 |
| D-82178 Puchheim |
| Germany |
| rtems@embedded-brains.de |
+-----------------------------------------------------------------+
| |
| Parts of the code has been derived from the "dBUG source code" |
| package Freescale is providing for M548X EVBs. The usage of |
| the modified or unmodified code and it's integration into the |
| generic mcf548x BSP has been done according to the Freescale |
| license terms. |
| |
| The Freescale license terms can be reviewed in the file |
| |
| Freescale_license.txt |
| |
+-----------------------------------------------------------------+
| |
| The generic mcf548x BSP has been developed on the basic |
| structures and modules of the av5282 BSP. |
| |
+-----------------------------------------------------------------+
| |
| The license and distribution terms for this file may be |
| found in the file LICENSE in this distribution or at |
| |
| http://www.rtems.com/license/LICENSE. |
| |
+-----------------------------------------------------------------+
| |
| date history ID |
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 12.11.07 1.0 ras |
| 15.10.09 1.1, adapted to COBRA5475 doe |
| |
\*===============================================================*/
/*
* Location and size of on-chip devices
*/
_SdramBase = DEFINED(_SdramBase) ? _SdramBase : 0xf0000000;
_SdramSize = DEFINED(_SdramSize) ? _SdramSize : (128 * 1024*1024);
_SysSramBase = DEFINED(_SysSramBase) ? _SysSramBase : __MBAR + 0x00010000;
_SysSramSize = DEFINED(_SysSramSize) ? _SysSramSize : (32 * 1024);
_McdapiBase = DEFINED(_McdapiBase) ? _McdapiBase : _SysSramBase;
_McdapiSize = DEFINED(_McdapiSize) ? _McdapiSize : (12 * 1024);
_CoreSramBase0 = DEFINED(_CoreSramBase0) ? _CoreSramBase0 : 0xFF000000;
_CoreSramBase1 = DEFINED(_CoreSramBase1) ? _CoreSramBase1 : 0xFF001000;
_CoreSramSize0 = DEFINED(_CoreSramSize0) ? _CoreSramSize0 : (4 * 1024);
_CoreSramSize1 = DEFINED(_CoreSramSize1) ? _CoreSramSize1 : (4 * 1024);
_BootFlashBase = DEFINED(_BootFlashBase) ? _BootFlashBase : 0xFC000000;
_BootFlashSize = DEFINED(_BootFlashSize) ? _BootFlashSize : (32 * 1024*1024);
_VectorRam = DEFINED(_VectorRam) ? _VectorRam : _SdramBase;
_DataRam = DEFINED(_DataRam) ? _DataRam : _data_dest_start;
_DataRom = DEFINED(_DataRom) ? _DataRom : _data_src_start;
_DataEnd = DEFINED(_DataEnd) ? _DataEnd : _data_dest_end;
_BssStart = DEFINED(_BssStart) ? _BssStart : _clear_start;
_BssEnd = DEFINED(_BssEnd) ? _BssEnd : _clear_end;
_SpInit = DEFINED(_SpInit) ? _SpInit : _EndInitStackSpace;
_InitStackSize = DEFINED(StackSize) ? StackSize : 0x800; /* 2 kB */
_TopRamReserved = DEFINED(_TopRamReserved) ? _TopRamReserved : 0;
RamBase = DEFINED(_SdramBase) ? _SdramBase : _SdramBase;
RamSize = DEFINED(_SdramSize) ? _SdramSize : _SdramSize;
HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0;
_VBR = DEFINED(_VBR) ? _VBR : RamBase;
__MBAR = DEFINED(__MBAR) ? __MBAR : 0xFE000000;
ENTRY(start)
MEMORY
{
sdram : ORIGIN = 0xF0040000, LENGTH = 128M - 256K
boot_flash : ORIGIN = 0xFC000000, LENGTH = 32M
}
SECTIONS
{
_header_offset = 0;
/*
* Text, data and bss segments .vectors
*/
.vectors : {
*(.vectors*)
} >sdram
.text : {
*(.text*)
*(.ram_code)
/*
* C++ constructors/destructors
*/
*(.gnu.linkonce.t.*)
/*
* Initialization and finalization code.
*
* Various files can provide initialization and finalization
* functions. crtbegin.o and crtend.o are two instances. The
* body of these functions are in .init and .fini sections. We
* accumulate the bodies here, and prepend function prologues
* from crti.o and function epilogues from crtn.o. crti.o must
* be linked first; crtn.o must be linked last. Because these
* are wildcards, it doesn't matter if the user does not
* actually link against crti.o and crtn.o; the linker won't
* look for a file to match a wildcard. The wildcard also
* means that it doesn't matter which directory crti.o and
* crtn.o are in.
*/
PROVIDE (_init = .);
*crti.o(.init)
*(.init)
*crtn.o(.init)
PROVIDE (_fini = .);
*crti.o(.fini)
*(.fini)
*crtn.o(.fini)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/*
* C++ constructors/destructors
*
* gcc uses crtbegin.o to find the start of the constructors
* and destructors so we make sure it is first. Because this
* is a wildcard, it doesn't matter if the user does not
* actually link against crtbegin.o; the linker won't look for
* a file to match a wildcard. The wildcard also means that
* it doesn't matter which directory crtbegin.o is in. The
* constructor and destructor list are terminated in
* crtend.o. The same comments apply to it.
*/
. = ALIGN (16);
*crtbegin.o(.ctors)
*(.ctors)
*crtend.o(.ctors)
*crtbegin.o(.dtors)
*(.dtors)
*crtend.o(.dtors)
/*
* Exception frame info
*/
. = ALIGN (16);
*(.eh_frame)
/*
* Read-only data
*/
. = ALIGN (16);
_rodata_start = . ;
*(.rodata*)
*(.gnu.linkonce.r*)
. = ALIGN (16);
*(.console_gdb_xfer)
*(.bootstrap_data)
. = ALIGN(16);
_estuff = .;
PROVIDE (_etext = .);
} >sdram
.data : {
/*.data : {*/
PROVIDE( _data_dest_start = . );
PROVIDE( _copy_start = .);
*(.data*)
*(.gnu.linkonce.d*)
*(.gcc_except_table*)
*(.jcr)
. = ALIGN (16);
PROVIDE (_edata = .);
PROVIDE (_copy_end = .);
PROVIDE (_data_dest_end = . );
} >sdram
_data_src_start = _etext; /*LOADADDR(.data);*/
_data_src_end = _data_src_start + SIZEOF(.data);
.bss : {
PROVIDE (_clear_start = .);
*(.bss*)
*(COMMON)
. = ALIGN (16);
PROVIDE (end = .);
PROVIDE (_clear_end = .);
. = ALIGN (4);
PROVIDE (_StartInitStackSpace = .);
/*. = _StartInitStackSpace + _InitStackSize;*/
. += _InitStackSize;
PROVIDE (_EndInitStackSpace = .);
PROVIDE (WorkAreaBase = .);
} >sdram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
PROVIDE (end_of_all = .);
}

1
c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.m5484FireEngine.flash
View File

@@ -70,7 +70,6 @@ _DataEnd = DEFINED(_DataEnd) ? _DataEnd : _data_dest_end;
_BssStart = DEFINED(_BssStart) ? _BssStart : _clear_start;
_BssEnd = DEFINED(_BssEnd) ? _BssEnd : _clear_end;
_SpInit = DEFINED(_SpInit) ? _SpInit : _EndInitStackSpace;
_InitPc = DEFINED(_InitPc) ? _InitPc : _SdramBase + 0x400;
_InitStackSize = DEFINED(StackSize) ? StackSize : 0x2000; /* 8 kB */
_TopRamReserved= DEFINED(_TopRamReserved) ? _TopRamReserved : 0;