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2011-08-31 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
	* include/mpc55xx-config.h, make/custom/mpc5674fevb.cfg,
	startup/early-init.c, startup/ebi-cal-cs-config.c,
	startup/ebi-cs-config.c, startup/exc-vector-base.S,
	startup/fmpll-syncr-vals.c, startup/linkcmds.mpc5674fevb,
	startup/mmu-config.c, startup/siu-pcr-config.c: New files.
	* Makefile.am, preinstall.am: Reflect changes above.
	* startup/linkcmds.gwlcfm, startup/linkcmds.mpc5566evb,
	startup/linkcmds.phycore_mpc5554: Use linker command base file.
	* configure.ac: Support MPC5674F.  Changed eSCI options.
	* clock/clock-config.c: Support MPC5674F.
	* i2c/i2c_init.c, network/smsc9218i.c, startup/sd-card-init.c: Update
	due to API changes.
	* include/bsp.h: Define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN.
	* network/if_smc.c: Use HAS_SMC91111.
	* startup/start.S, startup/bspstart.c: Moved low-level initialization
	into new files.  Overall cleanup.
This commit is contained in:
Sebastian Huber
2011-08-31 16:03:10 +00:00
parent f23c9ed63d
commit 9e7758b277
27 changed files with 1352 additions and 1184 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
c/src/lib/libbsp/powerpc/mpc55xxevb/ChangeLog
View File

@@ -1,3 +1,23 @@
2011-08-31 Sebastian Huber <sebastian.huber@embedded-brains.de>
* startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
* include/mpc55xx-config.h, make/custom/mpc5674fevb.cfg,
startup/early-init.c, startup/ebi-cal-cs-config.c,
startup/ebi-cs-config.c, startup/exc-vector-base.S,
startup/fmpll-syncr-vals.c, startup/linkcmds.mpc5674fevb,
startup/mmu-config.c, startup/siu-pcr-config.c: New files.
* Makefile.am, preinstall.am: Reflect changes above.
* startup/linkcmds.gwlcfm, startup/linkcmds.mpc5566evb,
startup/linkcmds.phycore_mpc5554: Use linker command base file.
* configure.ac: Support MPC5674F. Changed eSCI options.
* clock/clock-config.c: Support MPC5674F.
* i2c/i2c_init.c, network/smsc9218i.c, startup/sd-card-init.c: Update
due to API changes.
* include/bsp.h: Define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN.
* network/if_smc.c: Use HAS_SMC91111.
* startup/start.S, startup/bspstart.c: Moved low-level initialization
into new files. Overall cleanup.
2011-08-30 Peter Dufault <dufault@hda.com>
* make/custom/phycore_mpc5554.cfg, startup/linkcmds.phycore_mpc5554,

40
c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am
View File

@@ -24,11 +24,11 @@ project_lib_DATA += rtems_crti.$(OBJEXT)
# Link commands
project_lib_DATA += startup/linkcmds
dist_project_lib_DATA += \
startup/linkcmds.gwlcfm \
startup/linkcmds.phycore_mpc5554 \
startup/linkcmds.mpc5566evb \
startup/linkcmds.base
dist_project_lib_DATA += ../shared/startup/linkcmds.base
dist_project_lib_DATA += startup/linkcmds.gwlcfm
dist_project_lib_DATA += startup/linkcmds.mpc5566evb
dist_project_lib_DATA += startup/linkcmds.mpc5674fevb
dist_project_lib_DATA += startup/linkcmds.phycore_mpc5554
noinst_LIBRARIES += libbsp.a
libbsp_a_SOURCES =
@@ -41,20 +41,35 @@ nodist_include_HEADERS = include/bspopts.h ../../shared/tod.h \
../../shared/include/coverhd.h
include_bsp_HEADERS = include/mpc55xxevb.h \
include/smsc9218i.h \
include/mpc55xx-config.h \
../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h \
../../shared/include/irq-generic.h \
../../shared/include/irq-info.h \
../../shared/include/utility.h \
../shared/include/linker-symbols.h \
../shared/include/start.h \
../shared/include/tictac.h
# startup
libbsp_a_SOURCES += ../../shared/bsplibc.c ../../shared/bsppost.c \
../../shared/bootcard.c ../shared/src/tictac.c ../../shared/bspclean.c \
../shared/startup/bspidle.c startup/bspstart.c startup/bspgetworkarea.c \
../../shared/bsppretaskinghook.c \
../shared/src/memcpy.c \
../shared/src/bsp-start-zero.S
libbsp_a_SOURCES += ../../shared/bootcard.c
libbsp_a_SOURCES += ../../shared/bspclean.c
libbsp_a_SOURCES += ../../shared/bsplibc.c
libbsp_a_SOURCES += ../../shared/bsppost.c
libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
libbsp_a_SOURCES += ../../shared/bspgetworkarea.c
libbsp_a_SOURCES += ../shared/src/bsp-start-zero.S
libbsp_a_SOURCES += ../shared/src/memcpy.c
libbsp_a_SOURCES += ../shared/src/tictac.c
libbsp_a_SOURCES += ../shared/startup/bspidle.c
libbsp_a_SOURCES += startup/bspstart.c
libbsp_a_SOURCES += startup/fmpll-syncr-vals.c
libbsp_a_SOURCES += startup/exc-vector-base.S
libbsp_a_SOURCES += startup/ebi-cs-config.c
libbsp_a_SOURCES += startup/ebi-cal-cs-config.c
libbsp_a_SOURCES += startup/mmu-config.c
libbsp_a_SOURCES += startup/siu-pcr-config.c
libbsp_a_SOURCES += startup/early-init.c
# clock
libbsp_a_SOURCES += clock/clock-config.c
@@ -74,7 +89,8 @@ libbsp_a_SOURCES += i2c/i2c_init.c \
# Network
if HAS_NETWORKING
libbsp_a_SOURCES += network/smsc9218i.c network/if_smc.c
libbsp_a_SOURCES += network/smsc9218i.c
libbsp_a_SOURCES += network/if_smc.c
endif
# BSP library

25
c/src/lib/libbsp/powerpc/mpc55xxevb/clock/clock-config.c
View File

@@ -49,7 +49,7 @@ static void mpc55xx_clock_handler_install( rtems_isr_entry isr,
rtems_status_code sc = RTEMS_SUCCESSFUL;
sc = mpc55xx_interrupt_handler_install(
MPC55XX_IRQ_EMIOS_GET_REQUEST( MPC55XX_CLOCK_EMIOS_CHANNEL),
MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
"clock",
RTEMS_INTERRUPT_UNIQUE,
MPC55XX_INTC_MIN_PRIORITY,
@@ -96,26 +96,17 @@ static void mpc55xx_clock_initialize( void)
csr.B.FLAG = 1;
regs->CSR.R = csr.R;
/* Set internal counter start value */
regs->CCNTR.R = 1;
/* Set timer period */
regs->CADR.R = (uint32_t) interval - 1;
/* Set unused registers */
regs->CBDR.R = 0;
regs->CCNTR.R = 0;
#if MPC55XX_CHIP_TYPE != 5554
/* This is reserved on the MPC5554.
*/
regs->ALTCADR.R = 0;
#endif
/* Set control register */
/* The mode change, made by Thomas for GW_LCFM support, breaks interrupts
* on the MPC5554.
*/
#if MPC55XX_CHIP_TYPE == 5554
ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
#else
#if MPC55XX_CHIP_TYPE / 10 == 551
ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK;
#else
ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK;
#endif
ccr.B.UCPREN = 1;
ccr.B.FEN = 1;
@@ -135,7 +126,7 @@ static void mpc55xx_clock_cleanup( void)
/* Remove interrupt handler */
sc = rtems_interrupt_handler_remove(
MPC55XX_IRQ_EMIOS_GET_REQUEST( MPC55XX_CLOCK_EMIOS_CHANNEL),
MPC55XX_IRQ_EMIOS( MPC55XX_CLOCK_EMIOS_CHANNEL),
(rtems_interrupt_handler) Clock_isr,
NULL
);

53
c/src/lib/libbsp/powerpc/mpc55xxevb/configure.ac
View File

@@ -25,56 +25,45 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([gwlcfm],[])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5566evb],[1])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([mpc5674fevb],[1])
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([gwlcfm],[])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5566evb],[1])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([mpc5674fevb],[1])
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[1])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
RTEMS_BSPOPTS_SET([UARTS_USE_TERMIOS],[*],[])
RTEMS_BSPOPTS_HELP([UARTS_USE_TERMIOS],
[Define to 1 if you want termios support for every port.
Termios support is independent of the choice of UART I/O mode.])
RTEMS_BSPOPTS_SET([MPC55XX_ESCI_CONSOLE_MINOR],[*],[0])
RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_CONSOLE_MINOR],
[determines which eSCI device will be registered as /dev/console])
RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[gwlcfm],[MPC55XX_ESCI_A_MINOR])
RTEMS_BSPOPTS_SET([CONSOLE_MINOR],[*] ,[MPC55XX_ESCI_A_MINOR])
RTEMS_BSPOPTS_HELP([CONSOLE_MINOR],
[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR. Determines which
device will be registered as /dev/console.])
RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[gwlcfm],[1])
RTEMS_BSPOPTS_SET([UARTS_IO_MODE],[*] ,[])
RTEMS_BSPOPTS_HELP([UARTS_IO_MODE],
[Define to 1 if you want interrupt-driven I/O for the SCI ports.])
RTEMS_BSPOPTS_SET([PRINTK_MINOR],[gwlcfm],[MPC55XX_ESCI_A_MINOR])
RTEMS_BSPOPTS_SET([PRINTK_MINOR],[phytec_mpc5554],[MPC55XX_ESCI_A_MINOR])
RTEMS_BSPOPTS_SET([PRINTK_MINOR],[*] ,[MPC55XX_ESCI_B_MINOR])
RTEMS_BSPOPTS_HELP([PRINTK_MINOR],
[Must be defined to be one of MPC55XX_ESCI_A_MINOR or MPC55XX_ESCI_B_MINOR. Determines which
device is used for output by printk(). The printk port always uses polled
I/O. Don't open the printk port from RTEMS unless also using polled I/O
for the SCI ports.])
RTEMS_BSPOPTS_SET([MPC55XX_ESCI_USE_INTERRUPTS],[*],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_ESCI_USE_INTERRUPTS],
[define to zero or one to disable or enable interrupts for the eSCI devices])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[gwlcfm],[40000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[mpc5674fevb],[40000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_REF_CLOCK],[*] ,[8000000])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_REF_CLOCK],
[Must be defined to be the external reference clock (in Hz)
for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[gwlcfm],[66000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[mpc5674fevb],[264000000])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_CLK_OUT],[*] ,[128000000])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_CLK_OUT],
[Must be defined to be the PLL output clock (in Hz) for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[gwlcfm],[10])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[mpc5674fevb],[5])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_PREDIV],[*] ,[1])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_PREDIV],
[Must be defined to be the PLL predivider factor for clock generation])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[gwlcfm],[99])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[mpc5674fevb],[66])
RTEMS_BSPOPTS_SET([MPC55XX_FMPLL_MFD],[*] ,[12])
RTEMS_BSPOPTS_HELP([MPC55XX_FMPLL_MFD],
[Must be defined to be the PLL multiplication factor for clock generation])
@@ -97,18 +86,28 @@ RTEMS_BSPOPTS_HELP([MPC55XX_CLOCK_EMIOS_CHANNEL],
[Define to the eMIOS channel to use for the BSP clock.
The default is the last channel.])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5674fevb],[5674])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[mpc5566evb],[5566])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[gwlcfm] ,[5516])
RTEMS_BSPOPTS_SET([MPC55XX_CHIP_TYPE],[*] ,[5554])
RTEMS_BSPOPTS_HELP([MPC55XX_CHIP_TYPE],
[specifies the chip type in use (e.g. 5554 for MPC5554)])
RTEMS_BSPOPTS_SET([MPC55XX_BOOTFLAGS],[*],[])
RTEMS_BSPOPTS_HELP([MPC55XX_BOOTFLAGS],
[If defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
[if defined, builds in bootflags above the RCHW for setup in a debugger to avoid startup MMU setup])
RTEMS_BSPOPTS_SET([BOARD_GWLCFM],[gwlcfm],[1])
RTEMS_BSPOPTS_HELP([BOARD_GWLCFM],
[If defined, use custom settings of for the GW_LCFM board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5674FEVB],[mpc5674fevb],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5674FEVB],[if defined, use custom settings for MPC5674FEVB board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_MPC5566EVB],[mpc5566evb],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_MPC5566EVB],[if defined, use custom settings for MPC5566EVB board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_GWLCFM],[gwlcfm],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_GWLCFM],[if defined, use custom settings for GWLCFM board])
RTEMS_BSPOPTS_SET([MPC55XX_BOARD_PHYCORE_MPC5554],[phycore_mpc5554],[1])
RTEMS_BSPOPTS_HELP([MPC55XX_BOARD_PHYCORE_MPC5554],[if defined, use custom settings for phyCORE MPC5554 board])
RTEMS_BSPOPTS_SET([RTEMS_BSP_I2C_EEPROM_DEVICE_NAME],[gwlcfm],['"eeprom"'])
RTEMS_BSPOPTS_HELP([RTEMS_BSP_I2C_EEPROM_DEVICE_NAME],[EEPROM name for LibI2C])

10
c/src/lib/libbsp/powerpc/mpc55xxevb/i2c/i2c_init.c
View File

@@ -23,7 +23,7 @@
#include <bsp/irq.h>
#include <bsp/mpc83xx_i2cdrv.h>
#ifdef MPC55XX_IRQ_I2C
#if MPC55XX_CHIP_TYPE / 10 == 551
static mpc83xx_i2c_desc_t mpc55xx_i2c_bus = {
.bus_desc = {
.ops = &mpc83xx_i2c_ops,
@@ -32,7 +32,7 @@
.softc = {
.reg_ptr = (m83xxI2CRegisters_t *) 0xfff88000,
.initialized = FALSE,
.irq_number = MPC55XX_IRQ_I2C,
.irq_number = MPC55XX_IRQ_I2C(0),
.base_frq = 0
}
};
@@ -41,9 +41,9 @@
{
int rv = 0;
int busno = 0;
rtems_libi2c_initialize ();
mpc55xx_i2c_bus.softc.base_frq = bsp_clock_speed;
busno = rtems_libi2c_register_bus(
"/dev/i2c1",
@@ -64,7 +64,7 @@
return RTEMS_IO_ERROR;
}
#endif
return RTEMS_SUCCESSFUL;
}
#endif

22
c/src/lib/libbsp/powerpc/mpc55xxevb/include/bsp.h
View File

@@ -7,15 +7,19 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef LIBBSP_POWERPC_MPC55XXEVB_BSP_H
@@ -37,6 +41,8 @@ extern "C" {
#define BSP_SMALL_MEMORY 1
#define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN
#define BSP_FEATURE_IRQ_EXTENSION
#ifndef ASM

65
c/src/lib/libbsp/powerpc/mpc55xxevb/include/mpc55xx-config.h Normal file
View File

@@ -0,0 +1,65 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief MPC55XX low-level configuration.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#ifndef LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H
#define LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H
#include <stddef.h>
#include <mpc55xx/regs.h>
#include <mpc55xx/regs-mmu.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
typedef struct {
uint16_t index;
uint16_t count;
union SIU_PCR_tag pcr;
} mpc55xx_siu_pcr_config_entry;
extern const mpc55xx_siu_pcr_config_entry mpc55xx_siu_pcr_config [];
extern const size_t mpc55xx_siu_pcr_config_count [];
extern const struct MMU_tag mpc55xx_mmu_config [];
extern const size_t mpc55xx_mmu_config_count [];
extern const struct EBI_CS_tag mpc55xx_ebi_cs_config [];
extern const size_t mpc55xx_ebi_cs_config_count [];
extern const struct EBI_CAL_CS_tag mpc55xx_ebi_cal_cs_config [];
extern const size_t mpc55xx_ebi_cal_cs_config_count [];
void mpc55xx_early_init(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* LIBBSP_POWERPC_MPC55XXEVB_MPC55XX_CONFIG_H */

11
c/src/lib/libbsp/powerpc/mpc55xxevb/make/custom/mpc5674fevb.cfg Normal file
View File

@@ -0,0 +1,11 @@
##
#
# @file
#
# @ingroup mpc55xx_config
#
# @brief Configuration file for MPC567XEVBFXMB evaluation board equipped with
# an MPC5674F core from Freescale and Axiom.
#
include $(RTEMS_ROOT)/make/custom/mpc55xx.inc

8
c/src/lib/libbsp/powerpc/mpc55xxevb/network/if_smc.c
View File

@@ -2,13 +2,15 @@
* $Id$
*/
#include <bsp.h>
#ifdef HAS_SMC91111M
#include <mpc55xx/mpc55xx.h>
#include <mpc55xx/regs.h>
#include <rtems.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <rtems/bspIo.h>
#include <libcpu/powerpc-utility.h>
@@ -165,3 +167,5 @@ int rtems_smc91111_driver_attach_mpc5554(struct rtems_bsdnet_ifconfig *config)
return _rtems_smc91111_driver_attach(config,&mpc5554_scmv91111_configuration);
};
#endif /* HAS_SMC91111M */

18
c/src/lib/libbsp/powerpc/mpc55xxevb/network/smsc9218i.c
View File

@@ -790,7 +790,10 @@ static void smsc9218i_init_receive_jobs(
/* Obtain receive eDMA channel */
e->edma_receive.id = e->receive_task;
sc = mpc55xx_edma_obtain_channel(&e->edma_receive);
sc = mpc55xx_edma_obtain_channel(
&e->edma_receive,
MPC55XX_INTC_DEFAULT_PRIORITY
);
ASSERT_SC(sc);
for (i = 0; i < SMSC9218I_RX_JOBS; ++i) {
@@ -1341,7 +1344,10 @@ static void smsc9218i_transmit_task(void *arg)
/* Obtain transmit eDMA channel */
e->edma_transmit.id = e->transmit_task;
sc = mpc55xx_edma_obtain_channel(&e->edma_transmit);
sc = mpc55xx_edma_obtain_channel(
&e->edma_transmit,
MPC55XX_INTC_DEFAULT_PRIORITY
);
ASSERT_SC(sc);
/* Setup transmit eDMA descriptors */
@@ -1410,8 +1416,6 @@ static void smsc9218i_transmit_task(void *arg)
SMSC9218I_PRINTF("tx: done\n");
}
cleanup:
/* Release network semaphore */
rtems_bsdnet_semaphore_release();
@@ -1523,7 +1527,9 @@ static void smsc9218i_interrupt_init(
pcr.B.PA = 2;
pcr.B.OBE = 0;
pcr.B.IBE = 1;
#if MPC55XX_CHIP_TYPE / 10 != 551
pcr.B.DSC = 0;
#endif
pcr.B.ODE = 0;
pcr.B.HYS = 0;
pcr.B.SRC = 3;
@@ -1534,7 +1540,9 @@ static void smsc9218i_interrupt_init(
/* DMA/Interrupt Request Select */
rtems_interrupt_disable(level);
dirsr.R = SIU.DIRSR.R;
#if MPC55XX_CHIP_TYPE / 10 != 551
dirsr.B.DIRS0 = 0;
#endif
SIU.DIRSR.R = dirsr.R;
rtems_interrupt_enable(level);
@@ -1607,7 +1615,9 @@ static void smsc9218i_reset_signal_init(void)
pcr.B.PA = 0;
pcr.B.OBE = 1;
pcr.B.IBE = 0;
#if MPC55XX_CHIP_TYPE / 10 != 551
pcr.B.DSC = 0;
#endif
pcr.B.ODE = 0;
pcr.B.HYS = 0;
pcr.B.SRC = 3;

26
c/src/lib/libbsp/powerpc/mpc55xxevb/preinstall.am
View File

@@ -53,21 +53,25 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds
$(PROJECT_LIB)/linkcmds.base: ../shared/startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
$(PROJECT_LIB)/linkcmds.gwlcfm: startup/linkcmds.gwlcfm $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.gwlcfm
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.gwlcfm
$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
$(PROJECT_LIB)/linkcmds.mpc5566evb: startup/linkcmds.mpc5566evb $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5566evb
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5566evb
$(PROJECT_LIB)/linkcmds.base: startup/linkcmds.base $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
$(PROJECT_LIB)/linkcmds.mpc5674fevb: startup/linkcmds.mpc5674fevb $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc5674fevb
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc5674fevb
$(PROJECT_LIB)/linkcmds.phycore_mpc5554: startup/linkcmds.phycore_mpc5554 $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.phycore_mpc5554
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.phycore_mpc5554
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
@@ -97,6 +101,10 @@ $(PROJECT_INCLUDE)/bsp/smsc9218i.h: include/smsc9218i.h $(PROJECT_INCLUDE)/bsp/$
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/smsc9218i.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/smsc9218i.h
$(PROJECT_INCLUDE)/bsp/mpc55xx-config.h: include/mpc55xx-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc55xx-config.h
$(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h: ../../../libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mpc83xx_i2cdrv.h
@@ -113,6 +121,10 @@ $(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLU
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h
$(PROJECT_INCLUDE)/bsp/linker-symbols.h: ../shared/include/linker-symbols.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/linker-symbols.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/linker-symbols.h
$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h

46
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspgetworkarea.c
View File

@@ -1,46 +0,0 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief BSP Get Work Area of Memory.
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/bootcard.h>
#include <libcpu/powerpc-utility.h>
#define MPC55XX_INTERRUPT_STACK_SIZE 0x1000
/* Symbols defined in linker command file */
LINKER_SYMBOL(bsp_workspace_start);
LINKER_SYMBOL(bsp_workspace_end);
LINKER_SYMBOL(bsp_external_ram_end);
void bsp_get_work_area(
void **work_area_start,
uintptr_t *work_area_size,
void **heap_start,
uintptr_t *heap_size
)
{
size_t free_ram_size;
*work_area_start = bsp_workspace_start;
free_ram_size = (uint8_t *)bsp_external_ram_end - (uint8_t *)*work_area_start;
*work_area_size = (free_ram_size / 2);
*heap_start = (void *)((uint8_t *)*work_area_start + *work_area_size);
*heap_size = (free_ram_size / 2);
}

564
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c
View File

@@ -7,24 +7,30 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <mpc55xx/mpc55xx.h>
#include <mpc55xx/regs.h>
#include <mpc55xx/edma.h>
#include <mpc55xx/emios.h>
#include <mpc55xx/siu.h>
#include <string.h>
#include <rtems.h>
#include <rtems/config.h>
#include <libcpu/powerpc-utility.h>
#include <bsp/vectors.h>
@@ -33,21 +39,16 @@
#include <bsp/bootcard.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#define RTEMS_STATUS_CHECKS_USE_PRINTK
#include <rtems/status-checks.h>
#define DEBUG_DONE() RTEMS_DEBUG_PRINT( "Done\n")
#define MPC55XX_INTERRUPT_STACK_SIZE 0x1000
#include <bsp/linker-symbols.h>
#include <bsp/start.h>
#include <bsp/mpc55xx-config.h>
/* Symbols defined in linker command file */
LINKER_SYMBOL(bsp_ram_start);
LINKER_SYMBOL(bsp_ram_end);
LINKER_SYMBOL(bsp_external_ram_start);
LINKER_SYMBOL(bsp_external_ram_size);
LINKER_SYMBOL(bsp_section_bss_end);
LINKER_SYMBOL(mpc55xx_exc_vector_base);
unsigned int bsp_clock_speed = 0;
@@ -79,515 +80,37 @@ void _BSP_Fatal_error( unsigned n)
}
}
void bsp_predriver_hook()
static void null_pointer_protection(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
#if defined(MPC55XX_BOARD_MPC5674FEVB) || defined(MPC55XX_BOARD_MPC5566EVB)
struct MMU_tag mmu = { .MAS0 = { .B = { .TLBSEL = 1, .ESEL = 1 } } };
RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n");
sc = mpc55xx_edma_init();
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic( "Cannot initialize eDMA");
} else {
DEBUG_DONE();
}
}
#if ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517))
/*
* define init values for FMPLL ESYNCRx
* (used in start.S/fmpll.S)
*/
#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
#define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
#define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
#define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
const struct fmpll_syncr_vals_t {
union ESYNCR2_tag esyncr2_temp;
union ESYNCR2_tag esyncr2_final;
union ESYNCR1_tag esyncr1_final;
} fmpll_syncr_vals =
{
{ /* esyncr2_temp */
.B.LOCEN=0,
.B.LOLRE=0,
.B.LOCRE=0,
.B.LOLIRQ=0,
.B.LOCIRQ=0,
.B.ERATE=0,
.B.DEPTH=0,
.B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
},
{ /* esyncr2_final */
.B.LOCEN=0,
.B.LOLRE=0,
.B.LOCRE=0,
.B.LOLIRQ=0,
.B.LOCIRQ=0,
.B.ERATE=0,
.B.DEPTH=0,
.B.ERFD=ERFD_VAL /* nominal output clock after init */
},
{ /* esyncr1_final */
.B.CLKCFG=7,
.B.EPREDIV=EPREDIV_VAL,
.B.EMFD=EMFD_VAL
}
};
#else /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
const struct fmpll_syncr_vals_t {
union SYNCR_tag syncr_temp;
union SYNCR_tag syncr_final;
} fmpll_syncr_vals =
{
{ /* syncr_temp */
.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
.B.MFD=MPC55XX_FMPLL_MFD,
.B.RFD=2,
.B.LOCEN=1
},
{ /* syncr_final */
.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
.B.MFD=MPC55XX_FMPLL_MFD,
.B.RFD=0,
.B.LOCEN=1
}
};
#endif /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
#if defined(BOARD_GWLCFM)
static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
{ 0,16,{.B.PA = 1, .B.WPE = 0}}, /* PA[ 0..15] analog input */
{ 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
{ 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/
{ 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7 ] FR_A_EN out */
{ 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */
{ 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */
{ 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */
{ 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */
{ 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */
{ 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */
{ 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */
{ 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */
{ 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10 ] FR_B_EN out */
{ 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11 ] FOR_STATUS in */
{ 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12 ] FR_B_ERRN in */
{ 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13 ] HS_CAN_STBN out */
{ 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14 ] HS_CAN_ERR in */
{ 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15 ] HS_CAN_EN out */
{ 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0 ] HS_CAN_TX out */
{ 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1 ] HS_CAN_RX in */
{ 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */
{ 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4 ] LS_CAN_TX out */
{ 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5 ] LS_CAN_RX in */
{ 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6 ] HS_CAN_TX out */
{ 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7 ] HS_CAN_RX in */
{ 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 8 ] I2C_SCL in/out */
{ 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 9 ] I2C_SDA in/out */
{ 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN out*/
{ 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
/* PD[11..13] PWO1_OC, MOCO_INT in */
{ 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B in */
{ 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5. out*/
{ 70, 1,{.B.PA = 1,.B.SRC = 3,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT out*/
{ 80, 1,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR out*/
{ 81, 1,{.B.PA = 0,.B.SRC = 0,.B.WPE = 0}}, /* PF[ 1.. 1] (nc) in */
{ 82, 8,{.B.PA = 2,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] ADDR[8..15] out*/
{ 90, 2,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] CS[0..1] out*/
{ 92, 1,{.B.PA = 3,.B.SRC = 3,.B.WPE = 0}}, /* PF[ 12] ALE out*/
{ 93, 3,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[13..15] OE/WE out*/
{ 96,16,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PG[ 0..15] AD16..31 in/out*/
{113, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 1.. 1] RES_MOSTComp out*/
{114, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 2.. 2] CS3_MOSTComp out*/
{115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH out*/
{116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM out*/
{118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx out*/
{119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx in */
{120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 8..11] LIN_SLP,RST out*/
{0,0}
};
#elif defined(BOARD_PHYCORE_MPC5554)
static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
{ 0, 4,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0:3] */
{ 4,24,{.B.PA = 1, .B.DSC = 1 }}, /* ADDR [8 : 31] */
{ 28,32,{.B.PA = 1, .B.DSC = 1 }}, /* DATA [0 : 31] */
{ 60, 4,{.B.PA = 1, .B.DSC = 1, }}, /* TSIZ[0:1], RD_!WR, BDIP */
{ 64, 6,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, !WE, !OE, !TS */
{ 89, 4,{.B.PA = 1 }}, /* ESCI_A and ESCI_B */
{229, 4,{ .B.OBE= 1,.B.DSC = 1 }}, /* CLKOUT */
{0,0}
};
#else /* MPC55xxEVB */
static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
{ 0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0] */
{ 3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [3] */
{ 4,24,{.B.PA = 1,.B.DSC = 1 }}, /* ADDR [8 : 31] */
{ 28,16,{.B.PA = 1,.B.DSC = 1 }}, /* DATA [0 : 15] */
{ 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
!WE, !OE, !TS */
{ 89, 2,{.B.PA = 1 }}, /* ESCI_B */
{0,0}
};
#endif /* BOARD_GWLCFM */
/*
* Arrays for setting up the chip selects.
* You can define up to four, and those with the valid bit
* set will be loaded into the matching chip select.
*/
static const struct EBI_CS_tag cs_setup[] = {
#if defined(BOARD_GWLCFM)
/* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
{
{
.B.BA = 0x20000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
},
/* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 3,
.B.BSCY = 0
}
},
/* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22800000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
},
{ /* CS3: MOST Companion. */
{
.B.BA = 0x23000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
}
#elif defined(BOARD_PHYCORE_MPC5554)
/* CS0: External flash. */
{
{ .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */
{ .R = 0xff000050 }
},
/* CS1: External synchronous burst mode SRAM. */
{
{ .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */
{ .R = 0xff000000 } /* No wait states. */
},
/* CS2: External LAN91C111 */
{
{ .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */
{ .R = 0xff000010 }
},
/* CS3: External FPGA */
{
{ .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */
{ .R = 0xff000020 }
}
#else /* default, MPC55xxEVB */
/* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
{
{
.B.BA = 0,
.B.PS = 1,
.B.BL = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1, /* TODO: Enable burst */
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 0,
.B.BSCY = 0
}
},
{ { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */
{ { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */
{ /* CS3: ethernet? */
{
.B.BA = 0x7fff,
.B.PS = 1,
.B.BL = 0,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
}
#endif /* Chip select setup */
};
/*
* Arrays for setting up the MAS registers.
* You can set as many as you want,we determine the size using sizeof.
*/
static const struct MMU_tag mmu_setup[] = {
#if defined(BOARD_GWLCFM)
{
/* External Ethernet Controller (3 wait states, 64kB) */
{
.B.TLBSEL = 1, /* MAS0 */
.B.ESEL = 5
},
{
.B.VALID = 1, /* MAS1 */
.B.IPROT = 1,
.B.TSIZ = 1
},
{
.B.EPN = 0x3fff8, /* MAS2 */
.B.I = 1,
.B.G = 1
},
{
.B.RPN = 0x3fff8, /* MAS3 */
.B.UW = 1,
.B.SW = 1,
.B.UR = 1,
.B.SR = 1
}
}
#elif defined(BOARD_PHYCORE_MPC5554)
/* XXX I'm not using TLB1 entry 2 the same way as
* in the BAM.
*/
/* Set up MMU TLB1 entry 2 for external ram. */
/* Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */
/* Real Base address = 0x2100_0000 XXX NOT LIKE BAM */
/* Page Size 6 = 4MB XXX Not like BAM */
/* Not Guarded, Cache Enable, All Access (0, 3F) */
{
{ .R = 0x10020000}, /* MAS0 */
{ .R = 0xC0000600}, /* MAS1 */
{ .R = 0x21000000}, /* MAS2 */
{ .R = 0x2100003F} /* MAS3 */
},
/* Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */
/* Effective Base address = 0x2140_0000 */
/* Real Base address = 0x2140_0000 */
/* Page Size 6 = 4MB */
/* Not Guarded, Cache Enable, All Access (0, 3F) */
{
{ .R = 0x10050000 }, /* MAS0 */
{ .R = 0xC0000600 }, /* MAS1 */
{ .R = 0x21400000 }, /* MAS2 */
{ .R = 0x2140003F } /* MAS3 */
},
/* Set up MMU TLB1 entry 6 for External LAN91C111 */
/* Effective Base address = 0x2200_0000 */
/* Real Base address = 0x2200_0000 */
/* Page Size 7 = 16MB */
/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
{
{ .R = 0x10060000}, /* MAS0 */
{ .R = 0xC0000700}, /* MAS1 */
{ .R = 0x2200000E}, /* MAS2 */
{ .R = 0x2200003F} /* MAS3 */
},
/* Set up MMU TLB1 entry 7 for External FPGA */
/* Effective Base address = 0x2300_0000 */
/* Real Base address = 0x2300_0000 */
/* Page Size 7 = 16MB */
/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
{
{ .R = 0x10070000}, /* MAS0 */
{ .R = 0xC0000700}, /* MAS1 */
{ .R = 0x2300000E}, /* MAS2 */
{ .R = 0x2300003F}, /* MAS3 */
},
/* Should also set up maps for the debug RAM and the
* external flash.
*/
#else /* default, MPC55xxEVB */
{
/* External Ethernet Controller (3 wait states, 64kB) */
.MAS0 = { .R = 0x10050000 },
.MAS1 = { .R = 0xc0000100 },
.MAS2 = { .R = 0x3fff800a },
.MAS3 = { .R = 0x3fff800f }
}
#endif /* MMU setup */
};
#ifdef MPC55XX_BOOTFLAGS
/* mpc55xx_bootflag_0 is defined in start.S using PUBLIC_VAR(). I go through this
* indirection to avoid a linker issue - if I try to reference
* mpc55xx_bootflag_0 as an "extern uint32_t" I get a linker error.
* Maybe if I declare it as an "extern const uint32_t"? Anyway, this works.
*/
extern void *mpc55xx_bootflag_0(void);
uint32_t *p_mpc55xx_bootflag_0 = (uint32_t *)mpc55xx_bootflag_0;
PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, mmu.MAS0.R);
__asm__ volatile ("tlbre");
mmu.MAS1.R = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1);
mmu.MAS1.B.VALID = 0;
PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, mmu.MAS1.R);
__asm__ volatile ("tlbwe");
#endif
static void mpc55xx_ebi_init(void)
{
int i;
#if defined(BOARD_GWLCFM)
SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
#endif /* defined(BOARD_GWLCFM) */
/*
* init I/O pins to proper state
*/
mpc55xx_siu_pcr_init(&SIU,
siu_pcr_list);
/* Set up chip selects. */
for (i = 0; i < sizeof(cs_setup) / sizeof(cs_setup[0]); i++) {
if (cs_setup[i].BR.B.V) {
EBI.CS [i] = cs_setup[i];
}
}
#ifdef MPC55XX_BOOTFLAGS
/* If the low bit of bootflag 0 is clear don't change the MMU.
*/
if (((*p_mpc55xx_bootflag_0) & 1))
#endif
{
/* Set up MMU. */
for (i = 0; i < sizeof(mmu_setup) / sizeof(mmu_setup[0]); i++) {
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, mmu_setup[i].MAS0.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, mmu_setup[i].MAS1.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, mmu_setup[i].MAS2.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, mmu_setup[i].MAS3.R);
__asm__ volatile ("tlbwe");
}
}
#if defined(BOARD_GWLCFM)
/*
* init EBI for Muxed AD bus
*/
EBI.MCR.B.DBM = 1;
EBI.MCR.B.ADMUX = 1; /* use multiplexed bus */
EBI.MCR.B.D16_32 = 1; /* use lower AD bus */
SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
#endif /* defined(BOARD_GWLCFM) */
}
/**
* @brief Start BSP.
*/
LINKER_SYMBOL(bsp_section_bss_start);
LINKER_SYMBOL(bsp_section_bss_end);
LINKER_SYMBOL(bsp_section_sbss_start);
LINKER_SYMBOL(bsp_section_sbss_end);
LINKER_SYMBOL(bsp_section_vector_start);
void bsp_start(void)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
#if defined(MPC55XX_BOARD_MPC5674FEVB)
unsigned system_clock_divider = 2;
#else
unsigned system_clock_divider = 1;
#endif
uintptr_t interrupt_stack_start = (uintptr_t)bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE;
/* Initialize External Bus Interface */
mpc55xx_ebi_init();
null_pointer_protection();
/*
* make sure BSS/SBSS is cleared
*/
memset(bsp_section_bss_start,0,
bsp_section_bss_end-bsp_section_bss_start);
memset(bsp_section_sbss_start,0,
bsp_section_sbss_end-bsp_section_sbss_start);
ppc_exc_vector_base = (uint32_t) bsp_section_vector_start;
RTEMS_DEBUG_PRINT( "BSP start ...\n");
RTEMS_DEBUG_PRINT( "System clock : %i\n", mpc55xx_get_system_clock());
RTEMS_DEBUG_PRINT( "Memory start : 0x%08x\n", bsp_ram_start);
RTEMS_DEBUG_PRINT( "Memory end : 0x%08x\n", bsp_ram_end);
RTEMS_DEBUG_PRINT( "Memory size : 0x%08x\n", bsp_ram_end - bsp_ram_start);
RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start);
RTEMS_DEBUG_PRINT( "Interrupt stack end : 0x%08x\n", interrupt_stack_start + interrupt_stack_size);
RTEMS_DEBUG_PRINT( "Interrupt stack size : 0x%08x\n", interrupt_stack_size);
memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size);
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
@@ -600,34 +123,29 @@ void bsp_start(void)
/*
* determine clock speed
*/
bsp_clock_speed = mpc55xx_get_system_clock();
bsp_clock_speed = mpc55xx_get_system_clock() / system_clock_divider;
/* Time reference value */
bsp_clicks_per_usec = bsp_clock_speed / 1000000;
/* Initialize exceptions */
RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n");
ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base;
sc = ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
interrupt_stack_start,
interrupt_stack_size
(uintptr_t) bsp_section_work_begin,
Configuration.interrupt_stack_size
);
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic( "Cannot initialize exceptions");
} else {
DEBUG_DONE();
}
ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
/* Initialize interrupts */
RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n");
sc = bsp_interrupt_initialize();
if (sc != RTEMS_SUCCESSFUL) {
BSP_panic( "Cannot initialize interrupts");
} else {
DEBUG_DONE();
}
/* Initialize eMIOS */
mpc55xx_emios_initialize( MPC55XX_EMIOS_PRESCALER);
mpc55xx_edma_init();
mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
}

157
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/early-init.c Normal file
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@@ -0,0 +1,157 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief BSP early initialization code.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/linker-symbols.h>
#include <bsp/start.h>
#include <bsp.h>
#include <mpc55xx/mpc55xx.h>
#include <string.h>
#ifdef MPC55XX_BOOTFLAGS
extern uint32_t mpc55xx_bootflag_0 [];
#endif
static void mpc55xx_siu_init(void)
{
size_t i = 0;
#if defined(MPC55XX_BOARD_GWLCFM)
SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
#endif
for (i = 0; i < mpc55xx_siu_pcr_config_count [0]; ++i) {
const mpc55xx_siu_pcr_config_entry *e = &mpc55xx_siu_pcr_config [i];
int j = e->index;
int n = j + e->count;
uint32_t pcr = e->pcr.R;
while (j < n) {
SIU.PCR [j].R = pcr;
++j;
}
}
}
static void BSP_START_TEXT_SECTION mpc55xx_ebi_chip_select_init(void)
{
size_t i = 0;
for (i = 0; i < mpc55xx_ebi_cs_config_count [0]; ++i) {
EBI.CS [i] = mpc55xx_ebi_cs_config [i];
}
for (i = 0; i < mpc55xx_ebi_cal_cs_config_count [0]; ++i) {
EBI.CAL_CS [i] = mpc55xx_ebi_cal_cs_config [i];
}
}
static void BSP_START_TEXT_SECTION mpc55xx_ebi_init(void)
{
#if defined(MPC55XX_BOARD_GWLCFM)
/*
* init EBI for Muxed AD bus
*/
EBI.MCR.B.DBM = 1;
EBI.MCR.B.AD_MUX = 1; /* use multiplexed bus */
EBI.MCR.B.D16_31 = 1; /* use lower AD bus */
SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
#elif defined(MPC55XX_BOARD_MPC5674FEVB)
struct EBI_tag ebi = {
.MCR = {
.B = {
.ACGE = 0,
.MDIS = 0,
.D16_31 = 0,
.AD_MUX = 0,
.DBM = 0
}
}
};
EBI.MCR.R = ebi.MCR.R;
#endif
}
static void BSP_START_TEXT_SECTION mpc55xx_mmu_init(void)
{
#ifdef MPC55XX_BOOTFLAGS
/* If the low bit of bootflag 0 is clear don't change the MMU. */
bool do_mmu_init = (mpc55xx_bootflag_0 [0] & 1) != 0;
#else
bool do_mmu_init = true;
#endif
if (do_mmu_init) {
size_t i = 0;
for (i = 0; i < mpc55xx_mmu_config_count [0]; ++i) {
const struct MMU_tag *tag = &mpc55xx_mmu_config [i];
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, tag->MAS0.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, tag->MAS1.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, tag->MAS2.R);
PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, tag->MAS3.R);
__asm__ volatile ("tlbwe");
}
}
}
static void BSP_START_TEXT_SECTION mpc55xx_load_section(
void *dst,
const void *src,
size_t n
)
{
if (dst != src) {
memcpy(dst, src, n);
}
}
void BSP_START_TEXT_SECTION mpc55xx_early_init(void)
{
mpc55xx_load_section(
&bsp_section_fast_text_begin [0],
&bsp_section_fast_text_load_begin [0],
(size_t) bsp_section_fast_text_size
);
mpc55xx_load_section(
&bsp_section_fast_data_begin [0],
&bsp_section_fast_data_load_begin [0],
(size_t) bsp_section_fast_data_size
);
mpc55xx_load_section(
&bsp_section_data_begin [0],
&bsp_section_data_load_begin [0],
(size_t) bsp_section_data_size
);
mpc55xx_siu_init();
mpc55xx_ebi_chip_select_init();
mpc55xx_ebi_init();
mpc55xx_mmu_init();
}

59
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cal-cs-config.c Normal file
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@@ -0,0 +1,59 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief MPC55XX EBI calibration chip-select configuration.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
const BSP_START_TEXT_SECTION struct EBI_CAL_CS_tag
mpc55xx_ebi_cal_cs_config [] = {
#if defined(MPC55XX_BOARD_MPC5674FEVB)
{
.BR = {
.B = {
.BA = 0x20000000 >> 15,
.PS = 0,
.AD_MUX = 1,
.BL = 1,
.WEBS = 0,
.TBDIP = 1,
.SETA = 0,
.BI = 0,
.V = 1
}
},
.OR = {
.B = {
.AM = 0xfff80000 >> 15,
.SCY = 0,
.BSCY = 0
}
}
}
#endif
};
const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cal_cs_config_count [] = {
sizeof(mpc55xx_ebi_cal_cs_config) / sizeof(mpc55xx_ebi_cal_cs_config [0])
};

165
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cs-config.c Normal file
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@@ -0,0 +1,165 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief MPC55XX EBI chip-select configuration.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
const BSP_START_TEXT_SECTION struct EBI_CS_tag
mpc55xx_ebi_cs_config [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
/* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
{
{
.B.BA = 0x20000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
},
/* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 3,
.B.BSCY = 0
}
},
/* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
{
{
.B.BA = 0x22800000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 1,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
},
{ /* CS3: MOST Companion. */
{
.B.BA = 0x23000000>>15,
.B.PS = 1,
.B.AD_MUX = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 1,
.B.BSCY = 0
}
}
#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
/* CS0: External flash. */
{
{ .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */
{ .R = 0xff000050 }
},
/* CS1: External synchronous burst mode SRAM. */
{
{ .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */
{ .R = 0xff000000 } /* No wait states. */
},
/* CS2: External LAN91C111 */
{
{ .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */
{ .R = 0xff000010 }
},
/* CS3: External FPGA */
{
{ .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */
{ .R = 0xff000020 }
}
#elif defined(MPC55XX_BOARD_MPC5566EVB)
/* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
{
{
.B.BA = 0,
.B.PS = 1,
.B.BL = 1,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1, /* TODO: Enable burst */
.B.V = 1
},
{
.B.AM = 0x1fff0,
.B.SCY = 0,
.B.BSCY = 0
}
},
{ { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */
{ { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */
{ /* CS3: ethernet? */
{
.B.BA = 0x7fff,
.B.PS = 1,
.B.BL = 0,
.B.WEBS = 0,
.B.TBDIP = 0,
.B.BI = 1,
.B.V = 1
},
{
.B.AM = 0x1ffff,
.B.SCY = 1,
.B.BSCY = 0
}
}
#endif
};
const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cs_config_count [] = {
sizeof(mpc55xx_ebi_cs_config) / sizeof(mpc55xx_ebi_cs_config [0])
};

126
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/exc-vector-base.S Normal file
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@@ -0,0 +1,126 @@
/**
* @file
*
* @ingroup mpc55xx_asm
*
* @brief Exception minimum prologues.
*/
/*
* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
/**
* @defgroup mpc55xx_asm Assembler files
*
* @ingroup mpc55xx
*/
#include <bspopts.h>
#include <bsp/vectors.h>
.globl mpc55xx_exc_vector_base
.section ".bsp_start_data", "ax"
#if 5510 <= MPC55XX_CHIP_TYPE && MPC55XX_CHIP_TYPE <= 5517
.align 12
#else
.align 16
#endif
mpc55xx_exc_vector_base:
stw r1, ppc_exc_lock_crit@sdarel(r13)
stw r4, ppc_exc_vector_register_crit@sdarel(r13)
li r4, -32767
b ppc_exc_wrap_bookE_crit
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 2
b ppc_exc_wrap_nopush_bookE_crit
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 3
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 4
b ppc_exc_wrap_nopush_std
stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
li r4, -32763
b ppc_exc_wrap_async_normal
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 6
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 7
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 8
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 12
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 24
b ppc_exc_wrap_nopush_std
stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
li r4, -32752
b ppc_exc_wrap_async_normal
stwu r1, -PPC_EXC_MINIMAL_FRAME_SIZE(r1)
stw r4, PPC_EXC_VECTOR_PROLOGUE_OFFSET(r1)
li r4, -32749
b ppc_exc_wrap_async_normal
stw r1, ppc_exc_lock_crit@sdarel(r13)
stw r4, ppc_exc_vector_register_crit@sdarel(r13)
li r4, -32748
b ppc_exc_wrap_bookE_crit
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 18
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 17
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 13
b ppc_exc_wrap_nopush_bookE_crit
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 10
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 25
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 26
b ppc_exc_wrap_nopush_std
stwu r1, -EXC_GENERIC_SIZE(r1)
stw r4, GPR4_OFFSET(r1)
li r4, 15
b ppc_exc_wrap_nopush_std

92
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/fmpll-syncr-vals.c Normal file
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@@ -0,0 +1,92 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief BSP startup code.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <mpc55xx/regs.h>
#if MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567
/*
* define init values for FMPLL ESYNCRx
* (used in start.S/fmpll.S)
*/
#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
#define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
#define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
#define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
const struct fmpll_syncr_vals_t {
union FMPLL_ESYNCR2_tag esyncr2_temp;
union FMPLL_ESYNCR2_tag esyncr2_final;
union FMPLL_ESYNCR1_tag esyncr1_final;
} mpc55xx_fmpll_config =
{
{ /* esyncr2_temp */
.B.LOCEN=0,
.B.LOLRE=0,
.B.LOCRE=0,
.B.LOLIRQ=0,
.B.LOCIRQ=0,
.B.ERATE=0,
.B.EDEPTH=0,
.B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
},
{ /* esyncr2_final */
.B.LOCEN=0,
.B.LOLRE=0,
.B.LOCRE=0,
.B.LOLIRQ=0,
.B.LOCIRQ=0,
.B.ERATE=0,
#if MPC55XX_CHIP_TYPE / 10 == 567
.B.CLKCFG_DIS=1,
#endif
.B.EDEPTH=0,
.B.ERFD=ERFD_VAL /* nominal output clock after init */
},
{ /* esyncr1_final */
.B.CLKCFG=7,
.B.EPREDIV=EPREDIV_VAL,
.B.EMFD=EMFD_VAL
}
};
#else /* !(MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567) */
const struct fmpll_syncr_vals_t {
union FMPLL_SYNCR_tag syncr_temp;
union FMPLL_SYNCR_tag syncr_final;
} mpc55xx_fmpll_config =
{
{ /* syncr_temp */
.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
.B.MFD=MPC55XX_FMPLL_MFD,
.B.RFD=2,
.B.LOCEN=1
},
{ /* syncr_final */
.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
.B.MFD=MPC55XX_FMPLL_MFD,
.B.RFD=0,
.B.LOCEN=1
}
};
#endif /* !(MPC55XX_CHIP_TYPE / 10 == 551 || MPC55XX_CHIP_TYPE / 10 == 567) */

285
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.base
View File

@@ -1,285 +0,0 @@
/**
* @file
*
* Derived from internal linker script of GNU ld (GNU Binutils) 2.18 for elf32ppc emulation.
*/
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")
OUTPUT_ARCH(powerpc)
ENTRY(start)
SECTIONS
{
.text : {
/*
* BSP: Start of text section
*/
bsp_section_text_start = .;
/*
* BSP: System startup entry
*/
KEEP (*(.bsp_start_text))
KEEP (*(.bsp_start_data))
/*
* BSP: Moved into .text from .init
*/
KEEP (*(.init))
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.glink)
/*
* BSP: Special FreeBSD sysctl sections
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/*
* BSP: Moved into .text from .*
*/
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
*(.interp)
*(.note.gnu.build-id)
*(.hash)
*(.gnu.hash)
*(.dynsym)
*(.dynstr)
*(.gnu.version)
*(.gnu.version_d)
*(.gnu.version_r)
*(.eh_frame_hdr)
/*
* BSP: Magic PPC stuff
*/
*(.PPC.*)
/*
* BSP: Required by cpukit/score/src/threadhandler.c
*/
PROVIDE (_fini = .);
/*
* BSP: Moved into .text from .fini
*/
KEEP (*(.fini))
. = ALIGN (bsp_section_align);
PROVIDE (__etext = .);
PROVIDE (_etext = .);
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PROVIDE (_SDA2_BASE_ = 32768);
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
. = ALIGN (bsp_section_align);
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.vectors : {
. = ALIGN (bsp_section_align);
bsp_section_vector_start = .;
/*
* BSP: Reserve space for exception handler
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. = ALIGN (bsp_section_align);
} > REGION_VECTORS
.data : AT (bsp_section_text_end) {
/*
* BSP: Start of data section
*/
bsp_section_data_start = .;
/*
* BSP: Moved into .data from .ctors
*/
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
/*
* BSP: Moved into .data from .dtors
*/
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/*
* BSP: Moved into .data from .*
*/
*(.tdata .tdata.* .gnu.linkonce.td.*)
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
*(.data1)
KEEP (*(.eh_frame))
*(.gcc_except_table .gcc_except_table.*)
KEEP (*(.jcr))
*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*)
*(.fixup)
*(.got1)
*(.got2)
*(.dynamic)
*(.got)
*(.plt)
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
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.sdata : {
PROVIDE (_SDA_BASE_ = 32768);
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN (bsp_section_align);
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PROVIDE (edata = .);
/*
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} > REGION_DATA
.sbss : {
/*
* BSP: Start of bss section
*/
bsp_section_sbss_start = .;
__bss_start = .;
PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);
*(.scommon)
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);
. = ALIGN (bsp_section_align);
bsp_section_sbss_end = .;
} > REGION_DATA
.sbss2 : {
bsp_section_bss_start = .;
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
. = ALIGN (bsp_section_align);
} > REGION_BSS
.bss : {
*(COMMON)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN (bsp_section_align);
__end = .;
_end = .;
PROVIDE (end = .);
/*
* BSP: End of bss section
*/
bsp_section_bss_end = .;
} > REGION_BSS
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
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.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
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/* DWARF 1.1 and DWARF 2 */
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/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
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/* DWARF 3 */
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : {
*(.note.GNU-stack) *(.gnu_debuglink)
}
/*
* BSP: Catch all unknown sections
*/
.nirvana : {
*(*)
} > NIRVANA
}

26
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.gwlcfm
View File

@@ -1,6 +1,6 @@
MEMORY
{
ROM (RX) : ORIGIN = 0x0, LENGTH = 1536M
ROM (RX) : ORIGIN = 0x0, LENGTH = 1536K
RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 80K
RAM_EXT : ORIGIN = 0x20000000, LENGTH = 512K
NIRVANA : ORIGIN = 0x0, LENGTH = 0
@@ -18,14 +18,20 @@ bsp_external_ram_start = ORIGIN (RAM_EXT);
bsp_external_ram_end = ORIGIN (RAM_EXT) + LENGTH (RAM_EXT);
bsp_external_ram_size = LENGTH (RAM_EXT);
bsp_section_align = 32;
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_VECTORS", RAM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_START", ROM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_RODATA", ROM);
REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
REGION_ALIAS ("REGION_WORK", RAM_EXT);
REGION_ALIAS ("REGION_STACK", RAM_EXT);
INCLUDE linkcmds.base
bsp_workspace_start = bsp_section_bss_end;

24
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5566evb
View File

@@ -18,14 +18,20 @@ bsp_external_ram_start = ORIGIN (RAM_EXT);
bsp_external_ram_end = ORIGIN (RAM_EXT) + LENGTH (RAM_EXT);
bsp_external_ram_size = LENGTH (RAM_EXT);
bsp_section_align = 32;
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_VECTORS", RAM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_START", ROM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_RODATA", ROM);
REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
REGION_ALIAS ("REGION_WORK", RAM_EXT);
REGION_ALIAS ("REGION_STACK", RAM_EXT);
INCLUDE linkcmds.base
bsp_workspace_start = bsp_section_bss_end;

37
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.mpc5674fevb Normal file
View File

@@ -0,0 +1,37 @@
MEMORY
{
ROM (RX) : ORIGIN = 0x0, LENGTH = 4M
RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 256K
RAM_EXT : ORIGIN = 0x20000000, LENGTH = 512K
NIRVANA : ORIGIN = 0x0, LENGTH = 0
}
bsp_ram_start = ORIGIN (RAM);
bsp_ram_end = ORIGIN (RAM) + LENGTH (RAM);
bsp_ram_size = LENGTH (RAM);
bsp_rom_start = ORIGIN (ROM);
bsp_rom_end = ORIGIN (ROM) + LENGTH (ROM);
bsp_rom_size = LENGTH (ROM);
bsp_external_ram_start = ORIGIN (RAM_EXT);
bsp_external_ram_end = ORIGIN (RAM_EXT) + LENGTH (RAM_EXT);
bsp_external_ram_size = LENGTH (RAM_EXT);
REGION_ALIAS ("REGION_START", ROM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_RODATA", ROM);
REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_BSS", RAM);
REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
REGION_ALIAS ("REGION_WORK", RAM_EXT);
REGION_ALIAS ("REGION_STACK", RAM_EXT);
INCLUDE linkcmds.base

25
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/linkcmds.phycore_mpc5554
View File

@@ -5,7 +5,7 @@
MEMORY
{
ROM (RX) : ORIGIN = 0x00000000, LENGTH = 2M
RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 64K
RAM (AIW) : ORIGIN = 0x40000000, LENGTH = 64K
RAM_EXT (AIW) : ORIGIN = 0x21000000, LENGTH = 4M
DEBUG_RAM (AIW): ORIGIN = 0x21400000, LENGTH = 4M
NIRVANA : ORIGIN = 0x00000000, LENGTH = 0
@@ -27,13 +27,20 @@ bsp_debug_ram_start = ORIGIN (DEBUG_RAM);
bsp_debug_ram_end = ORIGIN (DEBUG_RAM) + LENGTH (DEBUG_RAM);
bsp_debug_ram_size = LENGTH (DEBUG_RAM);
bsp_section_align = 32;
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_VECTORS", RAM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_START", ROM);
REGION_ALIAS ("REGION_FAST_TEXT", RAM);
REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_TEXT", ROM);
REGION_ALIAS ("REGION_TEXT_LOAD", ROM);
REGION_ALIAS ("REGION_RODATA", ROM);
REGION_ALIAS ("REGION_RODATA_LOAD", ROM);
REGION_ALIAS ("REGION_FAST_DATA", RAM);
REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_DATA", RAM);
REGION_ALIAS ("REGION_DATA_LOAD", ROM);
REGION_ALIAS ("REGION_BSS", RAM_EXT);
REGION_ALIAS ("REGION_RWEXTRA", RAM_EXT);
REGION_ALIAS ("REGION_WORK", RAM_EXT);
REGION_ALIAS ("REGION_STACK", RAM_EXT);
INCLUDE linkcmds.base
bsp_workspace_start = bsp_section_bss_end;

125
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/mmu-config.c Normal file
View File

@@ -0,0 +1,125 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief MPC55XX MMU configuration.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
const BSP_START_TEXT_SECTION struct MMU_tag
mpc55xx_mmu_config [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
/* External Ethernet Controller 64k */
MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, 6, 0, 1, 1, 1)
#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
/* XXX I'm not using TLB1 entry 2 the same way as
* in the BAM.
*/
/* Set up MMU TLB1 entry 2 for external ram. */
/* Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */
/* Real Base address = 0x2100_0000 XXX NOT LIKE BAM */
/* Page Size 6 = 4MB XXX Not like BAM */
/* Not Guarded, Cache Enable, All Access (0, 3F) */
{
{ .R = 0x10020000}, /* MAS0 */
{ .R = 0xC0000600}, /* MAS1 */
{ .R = 0x21000000}, /* MAS2 */
{ .R = 0x2100003F} /* MAS3 */
},
/* Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */
/* Effective Base address = 0x2140_0000 */
/* Real Base address = 0x2140_0000 */
/* Page Size 6 = 4MB */
/* Not Guarded, Cache Enable, All Access (0, 3F) */
{
{ .R = 0x10050000 }, /* MAS0 */
{ .R = 0xC0000600 }, /* MAS1 */
{ .R = 0x21400000 }, /* MAS2 */
{ .R = 0x2140003F } /* MAS3 */
},
/* Set up MMU TLB1 entry 6 for External LAN91C111 */
/* Effective Base address = 0x2200_0000 */
/* Real Base address = 0x2200_0000 */
/* Page Size 7 = 16MB */
/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
{
{ .R = 0x10060000}, /* MAS0 */
{ .R = 0xC0000700}, /* MAS1 */
{ .R = 0x2200000E}, /* MAS2 */
{ .R = 0x2200003F} /* MAS3 */
},
/* Set up MMU TLB1 entry 7 for External FPGA */
/* Effective Base address = 0x2300_0000 */
/* Real Base address = 0x2300_0000 */
/* Page Size 7 = 16MB */
/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
{
{ .R = 0x10070000}, /* MAS0 */
{ .R = 0xC0000700}, /* MAS1 */
{ .R = 0x2300000E}, /* MAS2 */
{ .R = 0x2300003F}, /* MAS3 */
},
/* Should also set up maps for the debug RAM and the
* external flash.
*/
#elif defined(MPC55XX_BOARD_MPC5566EVB)
/* Internal flash 3M */
MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, 8, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, 8, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, 8, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, 10, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, 10, 1, 0, 1, 0),
/* External SRAM 512k */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 8, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, 8, 0, 1, 1, 0),
/* Internal SRAM 128k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, 6, 0, 1, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, 6, 0, 1, 1, 0),
/* External Ethernet Controller 64k */
MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, 6, 0, 1, 1, 1)
#elif defined(MPC55XX_BOARD_MPC5674FEVB)
/* Internal flash 4M */
MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 7, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, 8, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, 9, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, 10, 1, 0, 1, 0),
MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, 11, 1, 0, 1, 0),
/* External SRAM 512k */
MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 9, 0, 1, 1, 0),
/* Internal SRAM 256k */
MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, 8, 0, 1, 1, 0)
#endif
};
const BSP_START_TEXT_SECTION size_t mpc55xx_mmu_config_count [] = {
sizeof(mpc55xx_mmu_config) / sizeof(mpc55xx_mmu_config [0])
};

2
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/sd-card-init.c
View File

@@ -38,8 +38,10 @@ static rtems_status_code mpc55xx_dspi_init(void)
rv = rtems_libi2c_initialize();
RTEMS_CHECK_RV_SC( rv, "rtems_libi2c_initialize");
#if MPC55XX_CHIP_TYPE / 10 != 551
/* DSPI D inputs are taken from DSPI C */
SIU.DISR.R = 0x000000FC;
#endif
/* DSPI A signals */
pcr.B.PA = 1;

119
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/siu-pcr-config.c Normal file
View File

@@ -0,0 +1,119 @@
/**
* @file
*
* @ingroup mpc55xx
*
* @brief MPC55XX SIU PCR configuration.
*/
/*
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp/mpc55xx-config.h>
#include <bsp/start.h>
#include <bsp.h>
const BSP_START_TEXT_SECTION mpc55xx_siu_pcr_config_entry
mpc55xx_siu_pcr_config [] = {
#if defined(MPC55XX_BOARD_GWLCFM)
{ 0,16,{.B.PA = 1, .B.WPE = 0}}, /* PA[ 0..15] analog input */
{ 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
{ 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/
{ 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7 ] FR_A_EN out */
{ 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */
{ 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */
{ 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */
{ 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */
{ 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */
{ 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */
{ 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */
{ 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */
{ 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10 ] FR_B_EN out */
{ 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11 ] FOR_STATUS in */
{ 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12 ] FR_B_ERRN in */
{ 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13 ] HS_CAN_STBN out */
{ 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14 ] HS_CAN_ERR in */
{ 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15 ] HS_CAN_EN out */
{ 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0 ] HS_CAN_TX out */
{ 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1 ] HS_CAN_RX in */
{ 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */
{ 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4 ] LS_CAN_TX out */
{ 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5 ] LS_CAN_RX in */
{ 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6 ] HS_CAN_TX out */
{ 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7 ] HS_CAN_RX in */
{ 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 8 ] I2C_SCL in/out */
{ 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
/* PD[ 9 ] I2C_SDA in/out */
{ 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN out*/
{ 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
/* PD[11..13] PWO1_OC, MOCO_INT in */
{ 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B in */
{ 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5. out*/
{ 70, 1,{.B.PA = 1,.B.SRC = 3,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT out*/
{ 80, 1,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR out*/
{ 81, 1,{.B.PA = 0,.B.SRC = 0,.B.WPE = 0}}, /* PF[ 1.. 1] (nc) in */
{ 82, 8,{.B.PA = 2,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] ADDR[8..15] out*/
{ 90, 2,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] CS[0..1] out*/
{ 92, 1,{.B.PA = 3,.B.SRC = 3,.B.WPE = 0}}, /* PF[ 12] ALE out*/
{ 93, 3,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[13..15] OE/WE out*/
{ 96,16,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PG[ 0..15] AD16..31 in/out*/
{113, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 1.. 1] RES_MOSTComp out*/
{114, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 2.. 2] CS3_MOSTComp out*/
{115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH out*/
{116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM out*/
{118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx out*/
{119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx in */
{120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}} /* PH[ 8..11] LIN_SLP,RST out*/
#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
{ 0, 4,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0:3] */
{ 4,24,{.B.PA = 1, .B.DSC = 1 }}, /* ADDR [8 : 31] */
{ 28,32,{.B.PA = 1, .B.DSC = 1 }}, /* DATA [0 : 31] */
{ 60, 4,{.B.PA = 1, .B.DSC = 1, }}, /* TSIZ[0:1], RD_!WR, BDIP */
{ 64, 6,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, !WE, !OE, !TS */
{ 89, 4,{.B.PA = 1 }}, /* ESCI_A and ESCI_B */
{229, 4,{ .B.OBE= 1,.B.DSC = 1 }} /* CLKOUT */
#elif defined(MPC55XX_BOARD_MPC5566EVB)
{ 0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0] */
{ 3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [3] */
{ 4,24,{.B.PA = 1,.B.DSC = 1 }}, /* ADDR [8 : 31] */
{ 28,16,{.B.PA = 1,.B.DSC = 1 }}, /* DATA [0 : 15] */
{ 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
!WE, !OE, !TS */
{ 89, 2,{.B.PA = 1 }} /* ESCI_B */
#elif defined(MPC55XX_BOARD_MPC5674FEVB)
{ 89, 2, { .B = { .PA = 1 } } }, /* ESCI_A */
{ 256, 1, { .B = { .PA = 1, .DSC = 1 } } }, /* D_CS0 */
{ 257, 1, { .B = { .PA = 2, .DSC = 1 } } }, /* D_ADD_DAT31 */
{ 259, 4, { .B = { .PA = 1, .DSC = 1 } } }, /* D_ADD12 .. D_ADD15 */
{ 263, 15, { .B = { .PA = 2, .DSC = 1 } } }, /* D_ADD_DAT16 .. D_ADD_DAT30 */
{ 278, 16, { .B = { .PA = 1, .DSC = 1 } } }, /* D_ADD_DAT0 .. D_ADD_DAT15 */
{ 294, 6, { .B = { .PA = 1, .DSC = 1 } } }, /* D_RD_WR, D_WE0, D_WE1, D_OE, D_TS, D_ALE */
{ 302, 6, { .B = { .PA = 1, .DSC = 1 } } } /* D_BDIP, D_WE2, D_WE3, D_ADD9 .. D_ADD11 */
#endif
};
const BSP_START_TEXT_SECTION size_t mpc55xx_siu_pcr_config_count [] = {
sizeof(mpc55xx_siu_pcr_config) / sizeof(mpc55xx_siu_pcr_config [0])
};

386
c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start.S
View File

@@ -7,15 +7,19 @@
*/
/*
* Copyright (c) 2008
* Embedded Brains GmbH
* Obere Lagerstr. 30
* D-82178 Puchheim
* Germany
* rtems@embedded-brains.de
* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
* The license and distribution terms for this file may be found in the file
* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
* embedded brains GmbH
* Obere Lagerstr. 30
* 82178 Puchheim
* Germany
* <rtems@embedded-brains.de>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
/**
@@ -24,267 +28,209 @@
* @ingroup mpc55xx
*/
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
#include <bspopts.h>
#include <libcpu/powerpc-utility.h>
#include <mpc55xx/reg-defs.h>
#include <bsp/vectors.h>
#define HAS_CACHE (BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED)
.extern mpc55xx_fmpll_config
.extern mpc55xx_fmpll_init
.extern mpc55xx_flash_init
.extern mpc55xx_early_init
.extern bsp_start_zero
.extern bsp_ram_start
.extern bsp_ram_size
.extern bsp_ram_end
.extern __eabi
.extern boot_card
.globl _start
.section ".bsp_start_text", "ax"
#ifdef MPC55XX_BOOTFLAGS
PUBLIC_VAR (mpc55xx_bootflag_0)
PUBLIC_VAR (mpc55xx_bootflag_1)
.globl mpc55xx_bootflag_0
.globl mpc55xx_bootflag_1
#endif
PUBLIC_VAR (start)
.globl fmpll_syncr_vals
bam_rchw:
/*
* BAM
*/
.section ".bsp_start_text", "ax"
/* BAM: RCHW */
.int 0x005a0000
/* BAM: Address of start instruction */
.int _start
#ifdef MPC55XX_BOOTFLAGS
/* BAM: Address of start instruction
* We skip over the next two boot flag words to the next
* 64-bit aligned start address. It is 64-bit aligned
* to play well with FLASH programming.
* These boot flags can be set by debuggers and emulators to
* customize boot.
* Currently bit0 of bootflag_0 means to "skip setting up the MMU",
* allowing external MMU setup in a debugger before branching
* to 0x10. This can be used e.g., to map FLASH into RAM.
*/
.int 0x00000010 /* Start address is 0x10. */
/*
* We skip over the next two boot flag words to the next 64-bit
* aligned start address. It is 64-bit aligned to play well with
* FLASH programming. These boot flags can be set by debuggers
* and emulators to customize boot. Currently bit0 of
* bootflag_0 means to "skip setting up the MMU", allowing
* external MMU setup in a debugger before branching to 0x10.
* This can be used e.g., to map FLASH into RAM.
*/
mpc55xx_bootflag_0:
.int 0xffffffff
.int 0xffffffff
mpc55xx_bootflag_1:
.int 0xffffffff
#else
.int 0x00000008 /* Start address is 0x08. */
.int 0xffffffff
#endif
/*
* Enable time base
*/
start:
li r0, 0
mtspr TBWU, r0
mtspr TBWL, r0
mfspr r2, HID0
ori r2, r2, 0x4000
mtspr HID0, r2
_start:
/*
* System clock
*/
/* Enable time base */
li r0, 0
mtspr TBWU, r0
mtspr TBWL, r0
mfspr r2, HID0
ori r2, r2, 0x4000
mtspr HID0, r2
LWI r3,fmpll_syncr_vals
bl SYM (mpc55xx_fmpll_reset_config)
/* FMPLL setup */
LWI r3, mpc55xx_fmpll_config
bl mpc55xx_fmpll_init
/*
* Enable branch prediction
*/
/* Enable branch prediction */
LWI r2, BUCSR_BBFI | BUCSR_BPEN
mtspr BUCSR, r2
LWI r2, BUCSR_BBFI | BUCSR_BPEN
mtspr BUCSR, r2
/*
* Basics
*/
/* Set stack start to end of ram */
LA r1, bsp_ram_end
addi r1, r1, -8
/* Set intermediate stack start to end of internal SRAM */
LA r1, bsp_ram_end
subi r1, r1, 16
/* Enable SPE */
mfmsr r2
oris r2, r2, 0x200
mtmsr r2
mfmsr r2
oris r2, r2, 0x200
mtmsr r2
/* Config internal flash */
bl SYM (mpc55xx_flash_config)
bl mpc55xx_flash_init
#if BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED
/* FIXME: Config cache */
#if HAS_CACHE
bl config_cache
#endif /* BSP_DATA_CACHE_ENABLED || BSP_INSTRUCTION_CACHE_ENABLED */
/*
* TODO, FIXME: Enable cache in the MMU for the SRAM
*/
.equ MAS0, 624
.equ MAS1, 625
.equ MAS2, 626
.equ MAS3, 627
/* Read back MMU TLB1 entry 3 (internal SRAM) and enable the cache.
*/
LWI r3, 0x10030000
mtspr MAS0, r3
/* Enable cache in the MMU for the internal SRAM */
LWI r3, 0x10030000
mtspr FSL_EIS_MAS0, r3
tlbre
LWI r4, ~0x00000008
mfspr r3, MAS2
and r3, r3, r4
mtspr MAS2, r3
LWI r4, ~0x00000008
mfspr r3, FSL_EIS_MAS2
and r3, r3, r4
mtspr FSL_EIS_MAS2, r3
tlbwe
#endif
/*
* TODO, FIXME: Set MMU for the external SRAM
*/
/* Zero internal SRAM (needed to get proper ECC) */
LA r3, bsp_ram_start
LA r4, bsp_ram_size
bl bsp_start_zero
/* Read back MMU TLB1 entry 2 (external SRAM) and set the
* logical address to the external RAM start.
*/
LWI r3, 0x10020000
mtspr MAS0, r3
tlbre
LWI r4, 0xfff
mfspr r3, MAS3
and r3, r3, r4
LA r4, bsp_external_ram_start
or r3, r3, r4
mtspr MAS3, r3
tlbwe
/* Initialize intermediate start stack */
li r0, 0
stw r0, 0(r1)
stw r0, 4(r1)
/* Read back MMU TLB1 entry 1 (internal flash) and disable
* write access.
*/
LWI r3, 0x10010000
mtspr MAS0, r3
tlbre
LWI r4, ~0x0000000C
mfspr r3, MAS3
and r3, r3, r4
mtspr MAS3, r3
tlbwe
/* Do early initialization */
bl mpc55xx_early_init
/*
* Zero RAM (needed to get proper ECC)
*/
/* Set up EABI and SYSV environment */
bl __eabi
/* Addresses */
LA r3, bsp_ram_start
LA r4, bsp_ram_size
/* Zero */
bl SYM (bsp_start_zero)
/*
* Copy data
*/
/* Addresses */
LA r3, bsp_section_text_end
LA r4, bsp_section_data_start
LA r5, bsp_section_data_end
/* Assert: Proper alignment of source start */
andi. r6, r3, 0x7
bne twiddle
/* Assert: Proper alignment of destination start */
andi. r6, r4, 0x7
bne twiddle
/* Assert: Proper alignment of destination end */
andi. r6, r5, 0x7
bne twiddle
/* Data size = destination end - destination start */
subf r5, r4, r5
/* Copy */
bl SYM (mpc55xx_copy_8)
/* Save time and get time delta */
mftb r26
subf r25, r25, r26
/*
* Prepare high level initialization
*/
/* Create NULL */
li r0, 0
/* Return address */
stw r0, 4(r1)
/* Back chain */
stw r0, 0(r1)
/* Read-only small data */
LA r2, _SDA2_BASE_
/* Read-write small data */
LA r13, _SDA_BASE_
/*
* Start RTEMS
*/
/* Initialize start stack */
LWI r1, start_stack_end
subi r1, r1, 16
li r0, 0
stw r0, 0(r1)
/* Clear command line */
xor r3, r3, r3
li r3, 0
/* Start RTEMS */
bl SYM (boot_card)
bl boot_card
/* Spin around */
b twiddle
twiddle:
b twiddle
.equ L1CSR0, 1010
.equ L1CSR0_CINV, 0x2
.equ L1CSR0_CABT, 0x4
/* FIXME: CORG??? .equ L1CSR0_SETTINGS, 0x00180011 */
.equ L1CSR0_SETTINGS, 0x00100001
/*
* Configure cache
*/
#if HAS_CACHE
config_cache:
/* Start cache invalidation */
LWI r5, L1CSR0_CINV
mtspr L1CSR0, r5
/* Bit masks to test and clear invalidation abortion (CABT) */
LWI r6, L1CSR0_CABT
not r7, r6
/* Load zero, CINV, and CABT) */
li r0, 0
li r3, 0x2
li r4, 0x4
/* Wait for cache invalidation to complete */
check_cache_invalidation:
mfspr r9, L1CSR0
#if MPC55XX_CHIP_TYPE / 10 == 567
start_instruction_cache_invalidation:
/* Check if the invalidate was aborted */
and. r10, r9, r6
beq no_chache_invalidation_abort
/* Clear instruction cache invalidation abort */
mtspr FSL_EIS_L1CSR1, r0
/* Clear CABT bit */
and r10, r9, r7
mtspr L1CSR0, r10
/* Start instruction cache invalidation */
mtspr FSL_EIS_L1CSR1, r3
/* Retry invalidation */
b config_cache
get_instruction_cache_invalidation_status:
no_chache_invalidation_abort:
/* Check CINV bit */
and. r10, r5, r9
/* Get instruction cache invalidation status */
mfspr r5, FSL_EIS_L1CSR1
/* Wait? */
bne check_cache_invalidation
/* Check CABT */
and. r6, r5, r4
bne start_instruction_cache_invalidation
/* Enable cache */
LWI r6, L1CSR0_SETTINGS
mfspr r5, L1CSR0
or r5, r5, r6
msync
/* Check CINV */
and. r6, r5, r3
bne get_instruction_cache_invalidation_status
/* Save instruction cache settings */
LWI r6, 0x00010001
isync
mtspr L1CSR0, r5
msync
mtspr FSL_EIS_L1CSR1, r6
#endif /* MPC55XX_CHIP_TYPE / 10 == 567 */
start_data_cache_invalidation:
/* Clear data cache invalidation abort */
mtspr FSL_EIS_L1CSR0, r0
/* Start data cache invalidation */
mtspr FSL_EIS_L1CSR0, r3
get_data_cache_invalidation_status:
/* Get data cache invalidation status */
mfspr r5, FSL_EIS_L1CSR0
/* Check CABT */
and. r6, r5, r4
bne start_data_cache_invalidation
/* Check CINV */
and. r6, r5, r3
bne get_data_cache_invalidation_status
/* Save data cache settings */
#if MPC55XX_CHIP_TYPE / 10 != 567
/* FIXME: CORG??? 0x00180011 */
LWI r6, 0x00100001
#else
LWI r6, 0x00190001
#endif
isync
msync
mtspr FSL_EIS_L1CSR0, r6
/* Return */
blr
#endif /* HAS_CACHE */
twiddle:
b twiddle
/* Start stack area */
.section ".bsp_rwextra", "aw", @nobits
.align 4
.space 4096
start_stack_end: