RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

powerpc/score603e: Remove (obselete).

Browse Source 
Updates #2458.
This commit is contained in:
Ralph Holmes
2015-12-08 23:10:24 +00:00
committed by Gedare Bloom
parent 9ae2d98866
commit 999529516a
33 changed files with 0 additions and 4920 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
c/src/lib/libbsp/powerpc/acinclude.m4
View File

@@ -30,8 +30,6 @@ AC_DEFUN([RTEMS_CHECK_BSPDIR],
AC_CONFIG_SUBDIRS([qemuppc]);;
qoriq )
AC_CONFIG_SUBDIRS([qoriq]);;
score603e )
AC_CONFIG_SUBDIRS([score603e]);;
ss555 )
AC_CONFIG_SUBDIRS([ss555]);;
t32mppc )

77
c/src/lib/libbsp/powerpc/score603e/Makefile.am
View File

@@ -1,77 +0,0 @@
ACLOCAL_AMFLAGS = -I ../../../../aclocal
include $(top_srcdir)/../../../../automake/compile.am
include $(top_srcdir)/../../bsp.am
include_bspdir = $(includedir)/bsp
dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
nodist_include_HEADERS = include/bspopts.h
nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h
DISTCLEANFILES = include/bspopts.h
include_HEADERS += ../../shared/include/coverhd.h include/gen2.h
###
dist_project_lib_DATA += startup/linkcmds
startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
startup/bspstart.c ../../powerpc/shared/startup/bspgetworkarea.c \
../../shared/bsppost.c \
../../shared/bootcard.c ../../shared/bsppretaskinghook.c \
startup/Hwr_init.c \
../../powerpc/shared/startup/sbrk.c ../../shared/gnatinstallhandler.c \
../../powerpc/shared/showbats.c
pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
console_SOURCES = console/85c30.c console/85c30.h console/console.c \
console/tbl85c30.c console/consolebsp.h
include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
PCI_bus/PCI.h \
../../powerpc/shared/residual/residual.h \
../../powerpc/shared/residual/pnp.h \
../../powerpc/shared/console/consoleIo.h
pci_SOURCES = PCI_bus/flash.c ../../powerpc/shared/pci/pci.c \
../../powerpc/shared/pci/pcifinddevice.c PCI_bus/PCI.c PCI_bus/universe.c
include_bsp_HEADERS += irq/irq.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
irq_SOURCES = irq/no_pic.c irq/irq_init.c \
irq/FPGA.c
vectors_SOURCES =
EXTRA_DIST = start/start.S
start.$(OBJEXT): start/start.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA = start.$(OBJEXT)
EXTRA_DIST += ../../powerpc/shared/start/rtems_crti.S
rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
$(CPPASCOMPILE) -o $@ -c $<
project_lib_DATA += rtems_crti.$(OBJEXT)
noinst_LIBRARIES = libbsp.a
libbsp_a_SOURCES = $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
$(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES)
libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
include $(srcdir)/preinstall.am
include $(top_srcdir)/../../../../automake/local.am

102
c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c
View File

@@ -1,102 +0,0 @@
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <assert.h>
#include <stdio.h>
#include <bsp.h>
/*
* Forced delay to get around timing problems with the UNIVERSE chip. The
* two nops are used so that the delay works for varying clock frequencies,
* up to 66 Mhz, with margin. Each nop averages about 1 1/2 clock ticks,
* and since there are 2 nops, this routine takes about 3 clock ticks,
* which on a worst case 66 Mhz board, is 45 nanosecond. This time period
* is sufficient to guarantee a work-around to the UNIVERSE chip timing
* problem. The problem is that when there are two successive accesses to
* an UNIVERSE register, without sufficient delay, the second access will
* not work correctly.
*/
static void PCI_bus_delay (void)
{
__asm__ volatile ("nop");
__asm__ volatile ("nop");
}
/*
* PCI_bus_write
*/
void PCI_bus_write(
volatile uint32_t * _addr, /* IN */
uint32_t _data /* IN */
)
{
_data = Convert_Endian_32( _data );
*_addr = _data;
}
uint32_t PCI_bus_read(
volatile uint32_t * _addr /* IN */
)
{
uint32_t data;
data = *_addr;
data = Convert_Endian_32( data );
return data;
}
/*
* PCI Configuration Cycle Read/Write Access which is used to access all of
* devices registers on the PCI bus. i.e.: Universe, Ethernet & PMC.
*/
uint32_t Read_pci_device_register(
uint32_t address
)
{
uint32_t data;
/*
* Write the PCI configuration address
*/
PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
/*
* Delay needed when running out of DRAM
*/
PCI_bus_delay ();
/*
* read data
*/
data = PCI_bus_read( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA );
return data;
}
void Write_pci_device_register(
uint32_t address,
uint32_t data
)
{
/*
* Write the PCI configuration address
*/
PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_ADDR, address );
/*
* Delay needed when running out of DRAM
*/
PCI_bus_delay ();
/*
* write data
*/
PCI_bus_write( (volatile uint32_t*)SCORE603E_PCI_IO_CFG_DATA, data );
}

42
c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h
View File

@@ -1,42 +0,0 @@
/**
* @file
*
* This include file contains prototypes for chips attached to the
* PCI bus.
*/
/*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __PCI_h
#define __PCI_h
/*
* PCI.c
*/
void PCI_bus_write(
volatile uint32_t * _addr,
uint32_t _data
);
uint32_t PCI_bus_read(
volatile uint32_t * _addr
);
uint32_t Read_pci_device_register(
uint32_t address
);
void Write_pci_device_register(
uint32_t address,
uint32_t data
);
#endif

108
c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c
View File

@@ -1,108 +0,0 @@
/*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <assert.h>
#include <stdio.h>
#include <inttypes.h>
#include <bsp.h>
#include <bsp/irq.h>
#include "PCI.h"
/*
* SCORE603e_FLASH_Disable
*/
unsigned int SCORE603e_FLASH_Disable(
uint32_t area
)
{
uint8_t value;
value = *SCORE603E_BOARD_CTRL_REG;
value = value | (~SCORE603E_BRD_FLASH_DISABLE_MASK);
*SCORE603E_BOARD_CTRL_REG = value;
return RTEMS_SUCCESSFUL;
}
unsigned int SCORE603e_FLASH_verify_enable( void )
{
volatile uint8_t *Ctrl_Status_Register =
(void *)SCORE603E_BOARD_CTRL_REG;
uint8_t ctrl_value;
uint32_t pci_value;
ctrl_value = *Ctrl_Status_Register;
if ( ctrl_value & SCORE603E_BRD_FLASH_DISABLE_MASK ) {
printf ("Flash Writes Disabled by board control register %x\n",
ctrl_value );
assert( 0x0 );
}
pci_value = Read_pci_device_register( 0x800000A8 );
if (( pci_value & 0x00001000 ) == 0) {
printf("Error PCI A8 \n");
assert( 0x0 );
}
pci_value = Read_pci_device_register( 0x800000AC );
if ( pci_value & 0x02000000) {
printf("Error PCI AC \n");
assert( 0x0 );
}
return RTEMS_SUCCESSFUL;
}
#if 0
unsigned int SCORE603e_FLASH_pci_reset_reg(
uint8_t reg,
uint32_t cmask,
uint32_t mask
)
{
uint32_t pci_value;
uint32_t value;
pci_value = Read_pci_device_register( reg );
pci_value &= cmask;
pci_value |= mask;
Write_pci_device_register( reg, pci_value );
value = Read_pci_device_register( reg );
if (value != pci_value) {
printf("Error PCI 0x%2"PRIX8" wrote 0x%8"PRIX32" read %8"PRIX32"\n", reg, pci_value, value);
}
return RTEMS_SUCCESSFUL;
}
#endif
/*
* SCORE603e_FLASH_Enable_writes
*/
unsigned int SCORE603e_FLASH_Enable_writes(
uint32_t area
)
{
uint8_t ctrl_value;
uint32_t pci_value;
ctrl_value = *SCORE603E_BOARD_CTRL_REG;
ctrl_value = ctrl_value & 0xbf;
*SCORE603E_BOARD_CTRL_REG = ctrl_value;
pci_value = Read_pci_device_register( 0x800000A8 );
pci_value |= 0x00001000;
Write_pci_device_register( 0x800000A8, pci_value );
pci_value = Read_pci_device_register( 0x800000AC );
pci_value &= (~0x02000000);
Write_pci_device_register( 0x000000AC, pci_value );
return RTEMS_SUCCESSFUL;
}

255
c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c
View File

@@ -1,255 +0,0 @@
/*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <assert.h>
#include <stdio.h>
#include <inttypes.h>
#include <rtems/bspIo.h>
#include <bsp.h>
#include "PCI.h"
typedef struct {
uint32_t PCI_ID; /* 0x80030000 */
uint32_t PCI_CSR; /* 0x80030004 */
uint32_t PCI_CLASS; /* 0x80030008 */
uint32_t PCI_MISC0; /* 0x8003000C */
uint32_t PCI_BS; /* 0x80030010 */
uint32_t Buf_0x80030014[ 0x0A ]; /* 0x80030014 */
uint32_t PCI_MISC1; /* 0x8003003C */
uint32_t Buf_0x80030040[ 0x30 ]; /* 0x80030040 */
uint32_t LSI0_CTL; /* 0x80030100 */
uint32_t LSI0_BS; /* 0x80030104 */
uint32_t LSI0_BD; /* 0x80030108 */
uint32_t LSI0_TO; /* 0x8003010C */
uint32_t Buf_0x80030110; /* 0x80030110 */
uint32_t LSI1_CTL; /* 0x80030114 */
uint32_t LSI1_BS; /* 0x80030118 */
uint32_t LSI1_BD; /* 0x8003011C */
uint32_t LSI1_TO; /* 0x80030120 */
uint32_t Buf_0x80030124; /* 0x80030124 */
uint32_t LSI2_CTL; /* 0x80030128 */
uint32_t LSI2_BS; /* 0x8003012C */
uint32_t LSI2_BD; /* 0x80030130 */
uint32_t LSI2_TO; /* 0x80030134 */
uint32_t Buf_0x80030138; /* 0x80030138 */
uint32_t LSI3_CTL; /* 0x8003013C */
uint32_t LSI3_BS; /* 0x80030140 */
uint32_t LSI3_BD; /* 0x80030144 */
uint32_t LSI3_TO; /* 0x80030148 */
uint32_t Buf_0x8003014C[ 0x09 ]; /* 0x8003014C */
uint32_t SCYC_CTL; /* 0x80030170 */
uint32_t SCYC_ADDR; /* 0x80030174 */
uint32_t SCYC_EN; /* 0x80030178 */
uint32_t SCYC_CMP; /* 0x8003017C */
uint32_t SCYC_SWP; /* 0x80030180 */
uint32_t LMISC; /* 0x80030184 */
uint32_t SLSI; /* 0x80030188 */
uint32_t L_CMDERR; /* 0x8003018C */
uint32_t LAERR; /* 0x80030190 */
uint32_t Buf_0x80030194[ 0x1B ]; /* 0x80030194 */
uint32_t DCTL; /* 0x80030200 */
uint32_t DTBC; /* 0x80030204 */
uint32_t DLA; /* 0x80030208 */
uint32_t Buf_0x8003020C; /* 0x8003020C */
uint32_t DVA; /* 0x80030210 */
uint32_t Buf_0x80030214; /* 0x80030214 */
uint32_t DCPP; /* 0x80030218 */
uint32_t Buf_0x8003021C; /* 0x8003021C */
uint32_t DGCS; /* 0x80030220 */
uint32_t D_LLUE; /* 0x80030224 */
uint32_t Buf_0x80030228[ 0x36 ]; /* 0x80030228 */
uint32_t LINT_EN; /* 0x80030300 */
uint32_t LINT_STAT; /* 0x80030304 */
uint32_t LINT_MAP0; /* 0x80030308 */
uint32_t LINT_MAP1; /* 0x8003030C */
uint32_t VINT_EN; /* 0x80030310 */
uint32_t VINT_STAT; /* 0x80030314 */
uint32_t VINT_MAP0; /* 0x80030318 */
uint32_t VINT_MAP1; /* 0x8003031C */
uint32_t STATID; /* 0x80030320 */
uint32_t V1_STATID; /* 0x80030324 */
uint32_t V2_STATID; /* 0x80030328 */
uint32_t V3_STATID; /* 0x8003032C */
uint32_t V4_STATID; /* 0x80030330 */
uint32_t V5_STATID; /* 0x80030334 */
uint32_t V6_STATID; /* 0x80030338 */
uint32_t V7_STATID; /* 0x8003033C */
uint32_t Buf_0x80030340[ 0x30 ]; /* 0x80030340 */
uint32_t MAST_CTL; /* 0x80030400 */
uint32_t MISC_CTL; /* 0x80030404 */
uint32_t MISC_STAT; /* 0x80030408 */
uint32_t USER_AM; /* 0x8003040C */
uint32_t Buf_0x80030410[ 0x2bc ];/* 0x80030410 */
uint32_t VSI0_CTL; /* 0x80030F00 */
uint32_t VSI0_BS; /* 0x80030F04 */
uint32_t VSI0_BD; /* 0x80030F08 */
uint32_t VSI0_TO; /* 0x80030F0C */
uint32_t Buf_0x80030f10; /* 0x80030F10 */
uint32_t VSI1_CTL; /* 0x80030F14 */
uint32_t VSI1_BS; /* 0x80030F18 */
uint32_t VSI1_BD; /* 0x80030F1C */
uint32_t VSI1_TO; /* 0x80030F20 */
uint32_t Buf_0x80030F24; /* 0x80030F24 */
uint32_t VSI2_CTL; /* 0x80030F28 */
uint32_t VSI2_BS; /* 0x80030F2C */
uint32_t VSI2_BD; /* 0x80030F30 */
uint32_t VSI2_TO; /* 0x80030F34 */
uint32_t Buf_0x80030F38; /* 0x80030F38 */
uint32_t VSI3_CTL; /* 0x80030F3C */
uint32_t VSI3_BS; /* 0x80030F40 */
uint32_t VSI3_BD; /* 0x80030F44 */
uint32_t VSI3_TO; /* 0x80030F48 */
uint32_t Buf_0x80030F4C[ 0x9 ]; /* 0x80030F4C */
uint32_t VRAI_CTL; /* 0x80030F70 */
uint32_t VRAI_BS; /* 0x80030F74 */
uint32_t Buf_0x80030F78[ 0x2 ]; /* 0x80030F78 */
uint32_t VCSR_CTL; /* 0x80030F80 */
uint32_t VCSR_TO; /* 0x80030F84 */
uint32_t V_AMERR; /* 0x80030F88 */
uint32_t VAERR; /* 0x80030F8C */
uint32_t Buf_0x80030F90[ 0x19 ]; /* 0x80030F90 */
uint32_t VCSR_CLR; /* 0x80030FF4 */
uint32_t VCSR_SET; /* 0x80030FF8 */
uint32_t VCSR_BS; /* 0x80030FFC */
} Universe_Memory;
volatile Universe_Memory *UNIVERSE =
(volatile Universe_Memory *)SCORE603E_UNIVERSE_BASE;
/********************************************************************
********************************************************************
********* *********
********* *********
********* *********
********************************************************************
********************************************************************/
/*
* Initializes the UNIVERSE chip. This routine is called automatically
* by the boot code. This routine should be called by user code only if
* a complete SCORE603e VME initialization is required.
*/
void initialize_universe(void)
{
uint32_t jumper_selection;
uint32_t pci_id;
/*
* Read the VME jumper location to determine the VME base address
*/
jumper_selection = PCI_bus_read(
(volatile uint32_t*)SCORE603E_VME_JUMPER_ADDR );
printk("initialize_universe: Read 0x%x = 0x%x\n",
SCORE603E_VME_JUMPER_ADDR, jumper_selection);
jumper_selection = (jumper_selection >> 3) & 0x1f;
/*
* Verify the UNIVERSE CHIP ID
*/
pci_id = Read_pci_device_register( SCORE603E_IO_VME_UNIVERSE_BASE );
/*
* compare to known ID
*/
if (pci_id != SCORE603E_UNIVERSE_CHIP_ID ){
printk ("Invalid SCORE603E_UNIVERSE_CHIP_ID: 0x08%" PRId32 "\n", pci_id);
rtems_fatal_error_occurred( 0x603e0bad );
} else {
printk("initialize_universe: Reg 0x%x read 0x%x\n",
SCORE603E_IO_VME_UNIVERSE_BASE, pci_id );
}
/*
* Do not modify the DINK setup of the universe chip.
*/
}
/*
* Set the slave VME base address to the specified base address.
* Note: Lower 12 bits[11:0] will be masked out prior to setting the VMEbus
* Slave Image 0 registers.
*/
void set_vme_base_address (
uint32_t base_address
)
{
volatile uint32_t temp;
/*
* Calculate the current size of the Slave VME image 0
*/
temp = ( PCI_bus_read( &UNIVERSE->VSI0_BD) & 0xFFFFF000) -
( PCI_bus_read( &UNIVERSE->VSI0_BS) & 0xFFFFF000);
/*
* Set the VMEbus Slave Image 0 Base Address to be
* the specifed base address on VSI0_BS register.
*/
PCI_bus_write( &UNIVERSE->VSI0_BS, (base_address & 0xFFFFF000) );
/*
* Update the VMEbus Slave Image 0 Bound Address.
*/
PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
/*
* Update the VMEbus Slave Image 0 Translation Offset
*/
temp = 0xFFFFFFFF - (base_address & 0xFFFFF000) + 1 + 0x80000000;
PCI_bus_write( &UNIVERSE->VSI0_TO, temp );
}
/*
* Gets the VME base address
*/
static uint32_t get_vme_base_address (void)
{
volatile uint32_t temp;
temp = PCI_bus_read( &UNIVERSE->VSI0_BS );
temp &= 0xFFFFF000;
return (temp);
}
uint32_t get_vme_slave_size(void)
{
volatile uint32_t temp;
temp = PCI_bus_read( &UNIVERSE->VSI0_BD);
temp &= 0xFFFFF000;
temp = temp - get_vme_base_address ();
return temp;
}
/*
* Set the size of the VME slave image
* Note: The maximum size is up to 24 M bytes. (00000000 - 017FFFFF)
*/
void set_vme_slave_size (uint32_t size)
{
volatile uint32_t temp;
if (size<0)
size = 0;
if (size > 0x17FFFFF)
size = 0x17FFFFF;
/*
* Read the VME slave image base address
*/
temp = get_vme_base_address ();
/*
* Update the VMEbus Slave Image 0 Bound Address.
*/
temp = temp + (size & 0xFFFFF000);
PCI_bus_write( &UNIVERSE->VSI0_BD, temp );
}

53
c/src/lib/libbsp/powerpc/score603e/README
View File

@@ -1,53 +0,0 @@
BSP NAME: score603e
BOARD: VISTA SCORE 603e Generation II and beyond
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC 603e
COPROCESSORS: N/A
MODE: 32 bit mode
DEBUG MONITOR: see note.
PERIPHERALS
===========
TIMERS: PPC internal Timebase register
RESOLUTION:
SERIAL PORTS: 2 Z85C30s
REAL-TIME CLOCK: Generation II and beyond: ICM7170AIBG
DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: PPC internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: PPC internal
TTY DRIVER: PPC internal
STDIO
=====
PORT: Console port 0
ELECTRICAL: na
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: n
STOP BITS: 1
Notes
=====
This BSP has been modified to use the latest exception model.
However, the modifications were never verified. This version
has been partially verified in that Hello.ralf will load and
run on the board.
This BSP has been tested using DINK Rom monitor. There have
been three rom chips loaded on the boards. One with the SDS
debug monitor, one with the firmworks monitor, and one with
the DINK monitor.
The SCORE603e first generation board is no longer available,
does not appear to be in use by any RTEMS users, and thus
is no longer supported.

13
c/src/lib/libbsp/powerpc/score603e/bsp_specs
View File

@@ -1,13 +0,0 @@
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
*startfile:
%{!qrtems: %(old_startfile)} \
%{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s start.o%s -e start -u __vectors}}
*endfile:
%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s}
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N}

84
c/src/lib/libbsp/powerpc/score603e/configure.ac
View File

@@ -1,84 +0,0 @@
## Process this file with autoconf to produce a configure script.
AC_PREREQ([2.69])
AC_INIT([rtems-c-src-lib-libbsp-powerpc-ep1a],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
AC_CONFIG_SRCDIR([bsp_specs])
RTEMS_TOP(../../../../../..)
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
RTEMS_BSP_CONFIGURE
RTEMS_PROG_CC_FOR_TARGET
RTEMS_CANONICALIZE_TOOLS
RTEMS_PROG_CCAS
RTEMS_BSPOPTS_SET_DATA_CACHE_ENABLED([*],[])
RTEMS_BSPOPTS_HELP_DATA_CACHE_ENABLED
RTEMS_BSPOPTS_SET_INSTRUCTION_CACHE_ENABLED([*],[])
RTEMS_BSPOPTS_HELP_INSTRUCTION_CACHE_ENABLED
## FIXME: This should be a 1 out of 3 selection
## and is somehow coupled to USE_DINK (cf. include/gen2.h)
RTEMS_BSPOPTS_SET([SCORE603E_USE_SDS],[*],[0])
RTEMS_BSPOPTS_HELP([SCORE603E_USE_SDS],
[use SDS ROM monitor])
RTEMS_BSPOPTS_SET([SCORE603E_OPEN_FIRMWARE],[*],[0])
RTEMS_BSPOPTS_HELP([SCORE603E_OPEN_FIRMWARE],
[use Open Firmware ROM monitor])
RTEMS_BSPOPTS_SET([SCORE603E_USE_NONE],[*],[0])
RTEMS_BSPOPTS_HELP([SCORE603E_USE_NONE],
[use no ROM monitor])
RTEMS_BSPOPTS_SET([SCORE603E_USE_DINK],[*],[1])
RTEMS_BSPOPTS_HELP([SCORE603E_USE_DINK],
[FIXME: Missing explanation.])
RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
[whether using console interrupts])
RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[1])
RTEMS_BSPOPTS_HELP([HAS_PMC_PSC8],
[whether has a PSC8 PMC board attached to PMC slot])
RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
[FIXME: Missing explanation])
RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
[If defined, then the PowerPC specific code in RTEMS will use some
of the special purpose registers to slightly optimize interrupt
response time. The use of these registers can conflict with
other tools like debuggers.])
RTEMS_BSPOPTS_SET([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK], [*], [1])
RTEMS_BSPOPTS_HELP([CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK],
[If defined then the BSP may reduce the available memory size
initially. This can be useful for debugging (reduce the core
size) or dynamic loading (std gcc text offsets/jumps are < +/-32M).
Note that the policy can still be defined by the application
(see sbrk.c, BSP_sbrk_policy). By undefining
CONFIGURE_MALLOC_BSP_SUPPORTS_SBRK this feature is removed
and a little memory is saved.])
RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
[This defines the base address of the exception table.
NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
# Explicitly list all Makefiles here
AC_CONFIG_FILES([Makefile])
RTEMS_PPC_EXCEPTIONS
AC_OUTPUT

422
c/src/lib/libbsp/powerpc/score603e/console/85c30.c
View File

@@ -1,422 +0,0 @@
/*
* This file contains the console driver chip level routines for the
* z85c30 chip.
*
* Currently only polled mode is supported.
*/
/*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <assert.h>
#include "85c30.h"
#include "consolebsp.h"
#define STATUS_REGISTER 0x00
#define DATA_REGISTER 0x08
#define Z8530_Status_Is_RX_character_available( _status ) \
( (_status) & 0x01 )
#define Z8530_Status_Is_TX_buffer_empty( _status ) \
( (_status) & 0x04 )
#define Z8530_Status_Is_break_abort( _status ) \
( (_status) & 0x80 )
typedef struct {
unsigned char read_setup;
unsigned char write_setup;
unsigned char mask_value;
} char_size_info;
static const char_size_info Char_size_85c30[] = {
{ Z8530_READ_CHARACTER_BITS_8, Z8530_WRITE_CHARACTER_BITS_8, 0xFF },
{ Z8530_READ_CHARACTER_BITS_7, Z8530_WRITE_CHARACTER_BITS_7, 0x7F },
{ Z8530_READ_CHARACTER_BITS_6, Z8530_WRITE_CHARACTER_BITS_6, 0x3F },
{ Z8530_READ_CHARACTER_BITS_5, Z8530_WRITE_CHARACTER_BITS_5, 0x1F }
};
static const unsigned char Clock_speed_85c30[] = {
Z8530_x1_CLOCK, Z8530_x16_CLOCK, Z8530_x32_CLOCK, Z8530_x64_CLOCK };
static const unsigned char Stop_bit_85c30[] = {
Z8530_STOP_BITS_1, Z8530_STOP_BITS_1_AND_A_HALF, Z8530_STOP_BITS_2 };
static const unsigned char Parity_85c30[] = {
Z8530_PARITY_NONE, Z8530_PARITY_ODD, Z8530_PARITY_EVEN };
/* PAGE
*
* Read_85c30_register
*
* Read a Z85c30 register
*/
static unsigned char Read_85c30_register(
volatile unsigned char *csr, /* IN */
unsigned char register_number /* IN */
)
{
unsigned char Data;
*csr = register_number;
rtems_bsp_delay_in_bus_cycles( 40 );
Data = *csr;
rtems_bsp_delay_in_bus_cycles( 40 );
return Data;
}
/*
* Write_85c30_register
*
* Write a Z85c30 register
*/
static void Write_85c30_register(
volatile unsigned char *csr, /* IN */
unsigned char register_number, /* IN */
unsigned char data /* IN */
)
{
*csr = register_number;
rtems_bsp_delay_in_bus_cycles( 40 );
*csr = data;
rtems_bsp_delay_in_bus_cycles( 40 );
}
/* PAGE
*
* Reset_85c30_chip
*
* Reset a 85c30 chip. The pointers for the control registers for both
* ports on the chip are used as input.
*/
void Reset_85c30_chip(
volatile unsigned char *ctrl_0, /* IN */
volatile unsigned char *ctrl_1 /* IN */
)
{
Write_85c30_register( ctrl_0, 0x09, 0x80 );
Write_85c30_register( ctrl_1, 0x09, 0x40 );
}
/* PAGE
*
* initialize_85c30_port
*
* initialize a z85c30 Port
*/
void initialize_85c30_port(
const Port_85C30_info *Port
)
{
uint16_t value;
volatile unsigned char *ctrl;
Console_Protocol *Setup;
uint16_t baud_constant;
Setup = Port->Protocol;
ctrl = Port->ctrl;
baud_constant = _Score603e_Z8530_Baud( Port->Chip->clock_frequency,
Port->Chip->clock_x, Setup->baud_rate );
/*
* Using register 4
* Set up the clock rate.
*/
value = Clock_speed_85c30[ Port->Chip->clock_speed ] |
Stop_bit_85c30[ Setup->stop_bits ] |
Parity_85c30[ Setup->parity ];
Write_85c30_register( ctrl, 0x04, value );
/*
* Set Write Register 1 to disable all interrupts
*/
Write_85c30_register( ctrl, 1, 0 );
#if CONSOLE_USE_INTERRUPTS
/*
* Set Write Register 2 to contain the interrupt vector
*/
Write_85c30_register( ctrl, 2, Port->Chip->vector );
#endif
/*
* Set Write Register 3 to disable the Receiver
*/
Write_85c30_register( ctrl, 0x03, 0x00 );
/*
* Set Write Register 5 to disable the Transmitter
*/
Write_85c30_register( ctrl, 5, 0x00 );
/* WR 6 -- unneeded in asynchronous mode */
/* WR 7 -- unneeded in asynchronous mode */
/*
* Set Write Register 9 to disable all interrupt sources
*/
Write_85c30_register( ctrl, 9, 0x00 );
/*
* Set Write Register 10 for simple Asynchronous operation
*/
Write_85c30_register( ctrl, 0x0a, 0x00 );
/*
* Setup the source of the receive and xmit
* clock as BRG output and the transmit clock
* as the output source for TRxC pin via register 11
*/
Write_85c30_register( ctrl, 0x0b, 0x56 );
value = baud_constant;
/*
* Setup the lower 8 bits time constants = 1E.
* If the time constans = 1E, then the desire
* baud rate will be equilvalent to 9600, via register 12.
*/
Write_85c30_register( ctrl, 0x0c, value & 0xff );
/*
* using register 13
* Setup the upper 8 bits time constants = 0
*/
Write_85c30_register( ctrl, 0x0d, value>>8 );
/*
* Set the DTR/REQ pin goes low when transmit
* buffer becomes empty and enable the baud
* rate generator enable with clock from the
* SCC's PCLK input via register 14.
*/
Write_85c30_register( ctrl, 0x0e, 0x07 );
/*
* Set Write Register 3 : Base Value is xx00_000x
* D6 - D7 : Receive Character Length (configured)
* D5 : Auto Enable (forced value)
* D4 : Enter Hunt Phase (forced value)
* D3 : Receive CRC Enable (forced value)
* D2 : Address Search Mode (0 if not SDLC) (forced value)
* D1 : Sync Character Load Inhibit (forced value)
* D0 : Receiver Enable (configured)
*/
value = 0x01;
value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
Write_85c30_register( ctrl, 0x03, value );
/*
* Set Write Register 5 : Base Value is 0xx0_x000
* D7 : Data Terminal Ready (DTR) (forced value)
* D5 - D6 : Transmit Character Length (configured)
* D4 : Send Break (forced value)
* D3 : Transmitter Enable (configured)
* D2 : CRC Select (forced value)
* D1 : Request to Send (forced value)
* D0 : Transmit CRC Enable (forced value)
*/
value = 0x8a;
value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup;
Write_85c30_register( ctrl, 0x05, value );
/*
* Reset Tx UNDERRUN/EOM LATCH and ERROR
* via register 0
*/
Write_85c30_register( ctrl, 0x00, 0xf0 );
#if CONSOLE_USE_INTERRUPTS
/*
* Set Write Register 1 to interrupt on Rx characters or special condition.
*/
Write_85c30_register( ctrl, 1, 0x10 );
#endif
/*
* Set Write Register 15 to disable extended functions.
*/
Write_85c30_register( ctrl, 15, 0x00 );
/*
* Set the Command Register to Reset Ext/STATUS.
*/
Write_85c30_register( ctrl, 0x00, 0x10 );
#if CONSOLE_USE_INTERRUPTS
/*
* Set Write Register 1 : Base Value is 0001_0110
* Enables Rx interrupt on all characters and special conditions.
* Enables parity as a special condition.
* Enables Tx interrupt.
*/
Write_85c30_register( ctrl, 1, 0x16 );
/*
* Set Write Register 9 to enable all interrupt sources
* Changed from 0 to a
*/
Write_85c30_register( ctrl, 9, 0x0A );
/* XXX */
/*
* Issue reset highest Interrupt Under Service (IUS) command.
*/
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
#endif
}
/* PAGE
*
* outbyte_polled_85c30
*
* This routine transmits a character using polling.
*/
void outbyte_polled_85c30(
volatile unsigned char *csr, /* IN */
char ch /* IN */
)
{
unsigned char z8530_status;
uint32_t isrlevel;
rtems_interrupt_disable( isrlevel );
/*
* Wait for the Transmit buffer to indicate that it is empty.
*/
do {
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
} while ( !Z8530_Status_Is_TX_buffer_empty( z8530_status ) );
/*
* Write the character.
*/
Write_85c30_register( csr, DATA_REGISTER, (unsigned char) ch );
rtems_interrupt_enable( isrlevel );
}
/* PAGE
*
* inbyte_nonblocking_85c30
*
* This routine polls for a character.
*/
int inbyte_nonblocking_85c30(
const Port_85C30_info *Port
)
{
volatile unsigned char *csr;
unsigned char z8530_status;
uint8_t data;
csr = Port->ctrl;
/*
* return -1 if a character is not available.
*/
z8530_status = Read_85c30_register( csr, STATUS_REGISTER );
if ( !Z8530_Status_Is_RX_character_available( z8530_status ) )
return -1;
/*
* Return the character read.
*/
data = Read_85c30_register( csr, DATA_REGISTER );
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
return data;
}
/*
* Interrupt driven console IO
*/
#if CONSOLE_USE_INTERRUPTS
/*
* Z8530_Async_Channel_ISR
*/
/* RR0 */
rtems_isr ISR_85c30_Async(
const Port_85C30_info *Port
)
{
uint16_t status;
volatile Console_Protocol *Protocol;
unsigned char data;
bool did_something = false;
Protocol = Port->Protocol;
status = Read_85c30_register( Port->ctrl, 0x00 );
/*
* Was this a RX interrupt? If so, then process it.
*/
if ( Z8530_Status_Is_RX_character_available( status ) ) {
data = Read_85c30_register( Port->ctrl, DATA_REGISTER );
data &= Char_size_85c30[ Port->Protocol->read_char_bits ].mask_value;
rtems_termios_enqueue_raw_characters( Port->Protocol->console_termios_data,
&data, 1 );
did_something = true;
}
/*
* Was this a TX empty interrupt? If so, then process it.
*/
if (Z8530_Status_Is_TX_buffer_empty( status ) ) {
if ( !Ring_buffer_Is_empty( &Protocol->TX_Buffer ) ) {
Ring_buffer_Remove_character( &Protocol->TX_Buffer, data );
Write_85c30_register( Port->ctrl, DATA_REGISTER, data );
} else {
Protocol->Is_TX_active = false;
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x28 );
}
did_something = true;
}
/*
* Issue reset highest Interrupt Under Service (IUS) command.
*/
/*
if ( did_something )
*/
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
}
#endif

52
c/src/lib/libbsp/powerpc/score603e/console/85c30.h
View File

@@ -1,52 +0,0 @@
/* 85c30.h
*
* This include file contains z85c30 chip information.
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __85c30_H
#define __85c30_H
/*
* Clock Speed Definations
*/
#define Z8530_x1_CLOCK 0x00
#define Z8530_x16_CLOCK 0x40
#define Z8530_x32_CLOCK 0x80
#define Z8530_x64_CLOCK 0xC0
/*
* Number of Stop Bits.
*/
#define Z8530_STOP_BITS_1 0x04
#define Z8530_STOP_BITS_1_AND_A_HALF 0x08
#define Z8530_STOP_BITS_2 0x0C
/*
* PARITY
*/
#define Z8530_PARITY_NONE 0x00
#define Z8530_PARITY_ODD 0x01
#define Z8530_PARITY_EVEN 0x03
/*
* Character Bits
*/
#define Z8530_READ_CHARACTER_BITS_8 0xC0
#define Z8530_READ_CHARACTER_BITS_7 0x40
#define Z8530_READ_CHARACTER_BITS_6 0x80
#define Z8530_READ_CHARACTER_BITS_5 0x00
#define Z8530_WRITE_CHARACTER_BITS_8 0x60
#define Z8530_WRITE_CHARACTER_BITS_7 0x20
#define Z8530_WRITE_CHARACTER_BITS_6 0x40
#define Z8530_WRITE_CHARACTER_BITS_5 0x00
#endif

413
c/src/lib/libbsp/powerpc/score603e/console/console.c
View File

@@ -1,413 +0,0 @@
/*
* This file contains the TTY driver for the serial ports on the SCORE603e.
*
* This driver uses the termios pseudo driver.
*
* Currently only polled mode is supported.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/libio.h>
#include <stdlib.h>
#include <assert.h>
#include "consolebsp.h"
#include <rtems/bspIo.h>
/*
* The Port Used for the Console interface is based upon which
* debugger is being used. The SDS debugger uses a binary
* interface on port 0 as part of the debugger. Thus port 0 can
* not be used as the console port for the SDS debugger.
*/
#define USE_FOR_CONSOLE_DEF 0
int USE_FOR_CONSOLE = USE_FOR_CONSOLE_DEF;
/*
*
* Console Device Driver Entry Points
*/
/*
* console_inbyte_nonblocking
*
* Console Termios polling input entry point.
*/
static int console_inbyte_nonblocking(
int minor
)
{
int port = minor;
/*
* verify port Number
*/
assert ( port < NUM_Z85C30_PORTS );
/*
* return a character from the 85c30 port.
*/
return inbyte_nonblocking_85c30( &Ports_85C30[ port ] );
}
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_close (arg);
}
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_read (arg);
}
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_write (arg);
}
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return rtems_termios_ioctl (arg);
}
/*
* Interrupt driven console IO
*/
#if CONSOLE_USE_INTERRUPTS
rtems_isr console_isr(
rtems_vector_number vector
)
{
int i;
for (i=0; i < NUM_Z85C30_PORTS; i++){
ISR_85c30_Async( &Ports_85C30[i] );
}
}
void console_exit()
{
int i;
volatile Ring_buffer_t *buffer;
uint32_t ch;
for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
buffer = &( Ports_85C30[i].Protocol->TX_Buffer);
while ( !Ring_buffer_Is_empty( buffer ) ) {
Ring_buffer_Remove_character( buffer, ch );
outbyte_polled_85c30( Ports_85C30[i].ctrl, ch );
}
}
}
void console_initialize_interrupts( void )
{
volatile Ring_buffer_t *buffer;
Console_Protocol *protocol;
int i;
for ( i=0 ; i < NUM_Z85C30_PORTS ; i++ ) {
protocol = Ports_85C30[i].Protocol;
/*
* Initialize the ring buffer and set to not transmitting.
*/
buffer = &protocol->TX_Buffer;
Ring_buffer_Initialize( buffer );
protocol->Is_TX_active = false;
}
/*
* Connect each vector to the interupt service routine.
*/
for (i=0; i < NUM_Z85C30_CHIPS; i++)
set_vector( console_isr, Chips_85C30[i].vector, 1 );
#warning "Install interrupts using proper method for PIC vectors."
atexit( console_exit );
}
void console_outbyte_interrupts(
const Port_85C30_info *Port,
char ch
);
#endif
/*
* console_initialize
*
* Routine called to initialize the console device driver.
*/
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
rtems_device_minor_number console;
int port, p0,p1;
/*
* initialize the termio interface.
*/
rtems_termios_initialize();
/*
* Register Device Names
*/
console = USE_FOR_CONSOLE;
status = rtems_io_register_name( "/dev/console", major, console );
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
/*
* Initialize Hardware
*/
/*
* INITIALIZE_COM_PORTS is defined in the linker script. If it is
* true all serial chips on the board are to be reset at startup
* otherwise the reset is assumed to occur elsewhere (ie. in the
* debugger...)
*/
#if ( INITIALIZE_COM_PORTS )
/*
* Force to perform a hardware reset w/o
* Master interrupt enable via register 9
*/
for (port=0; port<NUM_Z85C30_PORTS; port++){
p0 = port;
port++;
p1 = port;
Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl );
}
#else
/* TEMP - To see if this makes a diff with the new ports.
* Never reset chip 1 when using the chip as a monitor
*/
for (port=2; port<NUM_Z85C30_PORTS; port++){
p0 = port;
port++;
p1 = port;
Reset_85c30_chip( Ports_85C30[p0].ctrl, Ports_85C30[p1].ctrl );
}
#endif
/*
* Initialize each port.
* Note: the ports are numbered such that 0,1 are on the first chip
* 2,3 are on the second ....
*/
for (port=1; port<NUM_Z85C30_PORTS; port++) {
initialize_85c30_port( &Ports_85C30[port] );
}
#if CONSOLE_USE_INTERRUPTS
console_initialize_interrupts();
#endif
return RTEMS_SUCCESSFUL;
}
/*
* console_write_support
*
* Console Termios output entry point.
*
*/
static ssize_t console_write_support(
int minor,
const char *buf,
size_t len)
{
int nwrite = 0;
volatile uint8_t *csr;
int port = minor;
/*
* verify port Number
*/
assert ( port < NUM_Z85C30_PORTS );
/*
* Set the csr based upon the port number.
*/
csr = Ports_85C30[ port ].ctrl;
/*
* poll each byte in the string out of the port.
*/
while (nwrite < len) {
#if (CONSOLE_USE_INTERRUPTS)
console_outbyte_interrupts( &Ports_85C30[ port ], *buf++ );
#else
outbyte_polled_85c30( csr, *buf++ );
#endif
nwrite++;
}
/*
* return the number of bytes written.
*/
return nwrite;
}
/*
* console_open
*
* open a port as a termios console.
*/
rtems_device_driver console_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_status_code sc;
int port = minor;
#if (CONSOLE_USE_INTERRUPTS)
rtems_libio_open_close_args_t *args = arg;
static const rtems_termios_callbacks intrCallbacks = {
NULL, /* firstOpen */
NULL, /* lastClose */
NULL, /* pollRead */
console_write_support, /* write */
NULL, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
1 /* outputUsesInterrupts */
};
#else
static const rtems_termios_callbacks pollCallbacks = {
NULL, /* firstOpen */
NULL, /* lastClose */
console_inbyte_nonblocking, /* pollRead */
console_write_support, /* write */
NULL, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
0 /* outputUsesInterrupts */
};
#endif
/*
* Verify the minor number is valid.
*/
if (minor < 0)
return RTEMS_INVALID_NUMBER;
if ( port > NUM_Z85C30_PORTS )
return RTEMS_INVALID_NUMBER;
/*
* open the port as a termios console driver.
*/
#if (CONSOLE_USE_INTERRUPTS)
sc = rtems_termios_open( major, minor, arg, &intrCallbacks );
Ports_85C30[ minor ].Protocol->console_termios_data = args->iop->data1;
#else
sc = rtems_termios_open( major, minor, arg, &pollCallbacks );
#endif
return sc;
}
#if (CONSOLE_USE_INTERRUPTS)
/*
* console_outbyte_interrupts
*
* This routine transmits a character out.
*/
void console_outbyte_interrupts(
const Port_85C30_info *Port,
char ch
)
{
Console_Protocol *protocol;
uint32_t isrlevel;
protocol = Port->Protocol;
/*
* If this is the first character then we need to prime the pump
*/
if ( protocol->Is_TX_active == false ) {
rtems_interrupt_disable( isrlevel );
protocol->Is_TX_active = true;
outbyte_polled_85c30( Port->ctrl, ch );
rtems_interrupt_enable( isrlevel );
return;
}
while ( Ring_buffer_Is_full( &protocol->TX_Buffer ) );
Ring_buffer_Add_character( &protocol->TX_Buffer, ch );
}
#endif
/* const char arg to be compatible with BSP_output_char decl. */
static void debug_putc_onlcr(const char c)
{
int console;
volatile uint8_t *csr;
uint32_t isrlevel;
console = USE_FOR_CONSOLE;
csr = Ports_85C30[ console ].ctrl;
if ('\n'==c){
rtems_interrupt_disable( isrlevel );
outbyte_polled_85c30( csr, '\r' );
__asm__ volatile("isync");
rtems_interrupt_enable( isrlevel );
}
rtems_interrupt_disable( isrlevel );
outbyte_polled_85c30( csr, c );
__asm__ volatile("isync");
rtems_interrupt_enable( isrlevel );
}
BSP_output_char_function_type BSP_output_char = debug_putc_onlcr;
BSP_polling_getchar_function_type BSP_poll_char = NULL;
/* const char arg to be compatible with BSP_output_char decl. */

146
c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
View File

@@ -1,146 +0,0 @@
/* consolebsp.h
*
* This include file contains all console driver definations
*
* COPYRIGHT (c) 1989-2010.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __CONSOLEBSP_H
#define __CONSOLEBSP_H
#include <rtems.h>
#include <rtems/ringbuf.h>
#include <bsp.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
*
* Note: The Ports are numbered 0..NUM_Z85C30_CHIPS with port 0 and 1
* being on the first chip, and ports 2 and 3 being on the
* second chip...
*/
/*
* Z85c30 configuration informaiton.
*/
#if (HAS_PMC_PSC8)
#define NUM_Z85C30_CHIPS_ON_MEZZANINE 4
#else
#define NUM_Z85C30_CHIPS_ON_MEZZANINE 0
#endif
#define NUM_Z85C30_CHIPS (2 + NUM_Z85C30_CHIPS_ON_MEZZANINE)
#define NUM_Z85C30_PORTS (NUM_Z85C30_CHIPS * 2)
typedef enum {
CONSOLE_x1_CLOCK,
CONSOLE_x16_CLOCK,
CONSOLE_x32_CLOCK,
CONSOLE_x64_CLOCK,
} CONSOLE_Clock_speed;
typedef enum {
CONSOLE_STOP_BITS_1,
CONSOLE_STOP_BITS_1_AND_A_HALF,
CONSOLE_STOP_BITS_2,
} CONSOLE_Stop_bits;
typedef enum {
CONSOLE_PARITY_NONE,
CONSOLE_PARITY_ODD,
CONSOLE_PARITY_EVEN,
} CONSOLE_Parity;
typedef enum {
CONSOLE_CHARACTER_BITS_8,
CONSOLE_CHARACTER_BITS_7,
CONSOLE_CHARACTER_BITS_6,
CONSOLE_CHARACTER_BITS_5,
} CONSOLE_Character_bits;
typedef struct {
uint32_t baud_rate; /* baud rate value */
CONSOLE_Stop_bits stop_bits;
CONSOLE_Parity parity;
CONSOLE_Character_bits read_char_bits;
CONSOLE_Character_bits write_char_bits;
#if CONSOLE_USE_INTERRUPTS
volatile Ring_buffer_t TX_Buffer; /* Transmit Buffer */
volatile bool Is_TX_active; /* Transmitting */
void *console_termios_data;
#endif
} Console_Protocol;
/*
* Structure used for chip level information.
*/
typedef struct {
uint32_t vector;
uint32_t clock_frequency;
uint16_t clock_x;
CONSOLE_Clock_speed clock_speed;
} Chip_85C30_info;
/*
* Structure used for port level informaiton.
*/
typedef struct {
volatile unsigned char *ctrl; /* Port Ctrl byte */
volatile unsigned char *data; /* Port data byte */
unsigned char port; /* Port-id / minor # */
Console_Protocol *Protocol;
Chip_85C30_info *Chip; /* Chip specific info */
} Port_85C30_info;
/*
* Console port chip configuration tables.
*/
extern Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ];
extern const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ];
/*
* 85c30.c prototypes.
*/
void initialize_85c30_port(
const Port_85C30_info *Port
);
void outbyte_polled_85c30(
volatile unsigned char *csr, /* IN */
char ch
);
int inbyte_nonblocking_85c30(
const Port_85C30_info *Port
);
void Reset_85c30_chip(
volatile unsigned char *ctrl_0,
volatile unsigned char *ctrl_1
);
#if CONSOLE_USE_INTERRUPTS
rtems_isr ISR_85c30_Async(
const Port_85C30_info *Port
);
#endif
#ifdef __cplusplus
}
#endif
#endif

194
c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c
View File

@@ -1,194 +0,0 @@
/*
* This file contains the table for the z85c30 port
* used by the console driver.
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include "consolebsp.h"
#include <bsp.h>
#include <bsp/irq.h>
#define CONSOLE_DEFAULT_BAUD_RATE 9600
#define CONSOLE_DEFAULT_BAUD_CONSTANT Score603e_Z8530_Chip0_Baud(9600)
#define CONSOLE_DEFAULT_STOP_BITS CONSOLE_STOP_BITS_1
#define CONSOLE_DEFAULT_PARITY CONSOLE_PARITY_NONE
#define CONSOLE_DEFAULT_READ_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8
#define CONSOLE_DEFAULT_WRITE_CHARACTER_BITS CONSOLE_CHARACTER_BITS_8
#define CONSOLE_DEFAULT_CONSOLE_CLOCK CONSOLE_x16_CLOCK
#define DEFAULT_PROTOCOL { CONSOLE_DEFAULT_BAUD_RATE, \
CONSOLE_DEFAULT_STOP_BITS, \
CONSOLE_DEFAULT_PARITY, \
CONSOLE_DEFAULT_READ_CHARACTER_BITS, \
CONSOLE_DEFAULT_WRITE_CHARACTER_BITS }
/*
* Tables of information necessary to use the console 85c30 routines.
*/
Console_Protocol Protocols_85c30 [ NUM_Z85C30_PORTS ] =
{
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
#if (HAS_PMC_PSC8)
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
DEFAULT_PROTOCOL,
#endif
};
/*
* Table of chip unique information for each chip.
* See consolebsp.h for the Chip_85C30_info structure defination.
*/
Chip_85C30_info Chips_85C30 [ NUM_Z85C30_CHIPS ] =
{
{
SCORE603E_85C30_0_IRQ,
SCORE603E_85C30_0_CLOCK,
SCORE603E_85C30_0_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
{
SCORE603E_85C30_1_IRQ,
SCORE603E_85C30_1_CLOCK,
SCORE603E_85C30_1_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
#if (HAS_PMC_PSC8)
{
SCORE603E_85C30_2_IRQ,
SCORE603E_85C30_2_CLOCK,
SCORE603E_85C30_2_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
{
SCORE603E_85C30_3_IRQ,
SCORE603E_85C30_3_CLOCK,
SCORE603E_85C30_3_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
{
SCORE603E_85C30_4_IRQ,
SCORE603E_85C30_4_CLOCK,
SCORE603E_85C30_4_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
{
SCORE603E_85C30_5_IRQ,
SCORE603E_85C30_5_CLOCK,
SCORE603E_85C30_5_CLOCK_X,
CONSOLE_DEFAULT_CONSOLE_CLOCK
},
#endif
};
/*
* Table of port unique information for each port.
* See consolebsp.h for the Port_85C30_info structure defination.
*/
const Port_85C30_info Ports_85C30 [ NUM_Z85C30_PORTS ] = {
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_0,
(volatile unsigned char *) SCORE603E_85C30_DATA_0,
0x00,
&Protocols_85c30[0],
&Chips_85C30[0],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_1,
(volatile unsigned char *) SCORE603E_85C30_DATA_1,
0x01,
&Protocols_85c30[1],
&Chips_85C30[0],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_2,
(volatile unsigned char *) SCORE603E_85C30_DATA_2,
0x02,
&Protocols_85c30[2],
&Chips_85C30[1],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_3,
(volatile unsigned char *) SCORE603E_85C30_DATA_3,
0x03,
&Protocols_85c30[3],
&Chips_85C30[1],
},
#if (HAS_PMC_PSC8)
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_4,
(volatile unsigned char *) SCORE603E_85C30_DATA_4,
0x04,
&Protocols_85c30[4],
&Chips_85C30[2],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_5,
(volatile unsigned char *) SCORE603E_85C30_DATA_5,
0x05,
&Protocols_85c30[5],
&Chips_85C30[2],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_6,
(volatile unsigned char *) SCORE603E_85C30_DATA_6,
0x06,
&Protocols_85c30[6],
&Chips_85C30[3],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_7,
(volatile unsigned char *) SCORE603E_85C30_DATA_7,
0x07,
&Protocols_85c30[7],
&Chips_85C30[3],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_8,
(volatile unsigned char *) SCORE603E_85C30_DATA_8,
0x08,
&Protocols_85c30[8],
&Chips_85C30[4],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_9,
(volatile unsigned char *) SCORE603E_85C30_DATA_9,
0x09,
&Protocols_85c30[9],
&Chips_85C30[4],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_10,
(volatile unsigned char *) SCORE603E_85C30_DATA_10,
0x0a,
&Protocols_85c30[10],
&Chips_85C30[5],
},
{
(volatile unsigned char *) SCORE603E_85C30_CTRL_11,
(volatile unsigned char *) SCORE603E_85C30_DATA_11,
0x0b,
&Protocols_85c30[11],
&Chips_85C30[5],
},
#endif
};

199
c/src/lib/libbsp/powerpc/score603e/include/bsp.h
View File

@@ -1,199 +0,0 @@
/*
* This include file contains all board IO definitions.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_POWERPC_SCORE603E_BSP_H
#define LIBBSP_POWERPC_SCORE603E_BSP_H
#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
#include <bspopts.h>
#include <bsp/default-initial-extension.h>
#include <rtems.h>
#include <rtems/console.h>
#include <libcpu/io.h>
#include <rtems/clockdrv.h>
#include <bsp/vectors.h>
#ifdef ASM
/* Definition of where to store registers in alignment handler */
#define ALIGN_REGS 0x0140
#else
#include <rtems.h>
#include <rtems/console.h>
#include <rtems/clockdrv.h>
#include <rtems/iosupp.h>
/*
* We no longer support the first generation board.
*/
#include <gen2.h>
#include <bsp/irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* The following macro calculates the Baud constant. For the Z8530 chip.
*
* Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
* for the Score603e ((10,000,000 / 16) / (2 * Baud Rate)) - 2
*/
#define _Score603e_Z8530_Baud( _frequency, _clock_by, _baud_rate ) \
( (_frequency /( _clock_by * 2 * _baud_rate)) - 2)
#define Score603e_Z8530_Chip1_Baud( _value ) \
_Score603e_Z8530_Baud( SCORE603E_85C30_1_CLOCK, \
SCORE603E_85C30_1_CLOCK_X, _value )
#define Score603e_Z8530_Chip0_Baud( _value ) \
_Score603e_Z8530_Baud( SCORE603E_85C30_0_CLOCK, \
SCORE603E_85C30_0_CLOCK_X, _value )
#define Initialize_Board_ctrl_register() \
*SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG | \
SCORE603E_BRD_FLASH_DISABLE_MASK)
#define Processor_Synchronize() \
__asm__ volatile(" eieio ")
/* Constants */
/*
* Device Driver Table Entries
*/
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
/*
* Information placed in the linkcmds file.
*/
extern int RAM_START;
extern int RAM_END;
extern int RAM_SIZE;
extern int PROM_START;
extern int PROM_END;
extern int PROM_SIZE;
extern int CLOCK_SPEED;
extern int CPU_PPC_CLICKS_PER_MS;
extern int end; /* last address in the program */
/*
* Total RAM available
*/
extern int end; /* last address in the program */
extern int RAM_END;
extern uint32_t BSP_mem_size;
/*
* How many libio files we want
*/
#define BSP_LIBIO_MAX_FDS 20
/* functions */
/*
*
*/
rtems_isr_entry set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
);
void initialize_external_exception_vector(void);
/*
* Hwr_init.c
*/
void init_PCI(void);
void init_RTC(void);
void instruction_cache_enable(void);
void data_cache_enable(void);
void initialize_PCI_bridge(void);
uint16_t read_and_clear_irq(void);
void set_irq_mask(uint16_t value);
uint16_t get_irq_mask(void);
/*
* universe.c
*/
void initialize_universe(void);
void set_irq_mask(uint16_t value);
uint16_t get_irq_mask(void);
void unmask_irq(uint16_t irq_idx);
void mask_irq(uint16_t irq_idx);
void init_irq_data_register(void);
uint16_t read_and_clear_PMC_irq(uint16_t irq);
bool Is_PMC_IRQ( uint32_t pmc_irq, uint16_t status_word);
uint16_t read_and_clear_irq(void);
void set_vme_base_address(uint32_t base_address);
uint32_t get_vme_slave_size(void);
void set_vme_slave_size (uint32_t size);
/*
* FPGA.c
*/
void initialize_PCI_bridge(void);
void init_irq_data_register(void);
uint32_t Read_pci_device_register(uint32_t address);
void Write_pci_device_register(uint32_t address, uint32_t data);
/* flash.c */
unsigned int SCORE603e_FLASH_Disable(uint32_t unused);
unsigned int SCORE603e_FLASH_verify_enable(void);
unsigned int SCORE603e_FLASH_Enable_writes(uint32_t area);
/*
* PCI.c
*/
uint32_t PCI_bus_read(volatile uint32_t *_addr);
void PCI_bus_write(volatile uint32_t *_addr, uint32_t _data);
#define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area )
#define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area )
#define Convert_Endian_32( _data ) \
( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) | \
((_data&0x00ff0000)>>8) | ((_data&0xff000000)>>24) )
#define Convert_Endian_16( _data ) \
( ((_data&0x00ff)<<8) | ((_data&0xff00)>>8) )
/*
* Interfaces to required Clock Driver support methods
*/
int BSP_disconnect_clock_handler(void);
int BSP_connect_clock_handler(void);
#ifdef __cplusplus
}
#endif
#endif /* ASM */
#endif

209
c/src/lib/libbsp/powerpc/score603e/include/gen2.h
View File

@@ -1,209 +0,0 @@
/* Gen2.h
*
* This include file contains all Generation 2 board addreses
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __SCORE_GENERATION_2_h
#define __SCORE_GENERATION_2_h
#ifdef __cplusplus
extern "C" {
#endif
#include <rtems.h>
/*
* ISA/PCI I/O space.
*/
#define SCORE603E_VME_JUMPER_ADDR 0x00e20000
#define BSP_FLASH_BASE 0x04000000
#define SCORE603E_ISA_PCI_IO_BASE 0x80000000
#define SCORE603E_TIMER_PORT_C 0xfd000000
#define SCORE603E_TIMER_INT_ACK 0xfd000000
#define SCORE603E_TIMER_PORT_B 0xfd000008
#define SCORE603E_TIMER_PORT_A 0xfd000004
#define SCORE603E_BOARD_CTRL_REG ((volatile uint8_t*)0xfd00002c)
#define SCORE603E_BRD_FLASH_DISABLE_MASK 0x40
#define SCORE603E_85C30_CTRL_0 ((volatile uint8_t*)0xfe200020)
#define SCORE603E_85C30_DATA_0 ((volatile uint8_t*)0xfe200024)
#define SCORE603E_85C30_CTRL_1 ((volatile uint8_t*)0xfe200028)
#define SCORE603E_85C30_DATA_1 ((volatile uint8_t*)0xfe20002c)
#define SCORE603E_85C30_CTRL_2 ((volatile uint8_t*)0xfe200000)
#define SCORE603E_85C30_DATA_2 ((volatile uint8_t*)0xfe200004)
#define SCORE603E_85C30_CTRL_3 ((volatile uint8_t*)0xfe200008)
#define SCORE603E_85C30_DATA_3 ((volatile uint8_t*)0xfe20000c)
/*
* PSC8 - PMC Card
*/
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define BSP_PCI_CONFIGURATION_BASE 0x80800000
#define BSP_PMC_BASE BSP_PCI_CONFIGURATION_BASE
#define PCI_MEM_BASE_ADJUSTMENT 0
#define BSP_PCI_PMC_DEVICE_BASE 0x80808000
#define BSP_PCI_REGISTER_BASE 0xfc000000
#define BSP_PCI_DEVICE_ADDRESS( _offset) \
((volatile uint32_t *)( BSP_PCI_PMC_DEVICE_BASE + _offset ))
#define BSP_PMC_SERIAL_ADDRESS( _offset ) \
((volatile uint8_t*)(BSP_PCI_REGISTER_BASE + _offset))
/*
* PMC serial channels - (4-7: 232 and 8-11: 422)
*/
#define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x00200020)
#define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x00200024)
#define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x00200028)
#define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x0020002c)
#define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x00200030)
#define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x00200034)
#define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x00200038)
#define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x0020003c)
#define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x00200000)
#define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x00200004)
#define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x00200008)
#define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x0020000c)
#define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x00200010)
#define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x00200014)
#define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x00200018)
#define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x0020001c)
#define _IO_BASE PREP_ISA_IO_BASE
#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8
#define SCORE603E_PCI_IO_CFG_DATA 0x80000cfc
#define SCORE603E_UNIVERSE_BASE 0x80030000
#define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
#define PCI_MEM_BASE 0xc0000000
#define BSP_PCI_MEM_BASE PCI_MEM_BASE /* XXX - May want to remove this later */
#define BSP_NVRAM_BASE 0xfd100000
#define BSP_RTC_ADDRESS ((volatile unsigned char *)0xfd180000)
#define SCORE603E_JP1_JP2_PROM_BASE 0xfff00000
#define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
#define SCORE603E_VME_A16_OFFSET 0x04000000
#elif (SCORE603E_USE_DINK)
#define SCORE603E_VME_A16_OFFSET 0x11000000
#define SCORE603E_VME_A24_OFFSET 0x10000000
#define BSP_VME_A24_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
#else
#error "SCORE603E gen2.h -- what ROM monitor are you using"
#endif
#define BSP_VME_A16_BASE (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
/*
* Definations for the ICM 1770 RTC chip
*/
/*
* These values are programed into a register and must not be changed.
*/
#define ICM1770_CRYSTAL_FREQ_32K 0x00
#define ICM1770_CRYSTAL_FREQ_1M 0x01
#define ICM1770_CRYSTAL_FREQ_2M 0x02
#define ICM1770_CRYSTAL_FREQ_4M 0x03
#define BSP_RTC_FREQUENCY ICM1770_CRYSTAL_FREQ_32K
/*
* Z85C30 Definations for the 423 interface.
*/
#define SCORE603E_85C30_0_CLOCK 14745600 /* 10,000,000 ?10->14.5 */
#define SCORE603E_85C30_0_CLOCK_X 16
/*
* Z85C30 Definations for the 422 interface.
*/
#define SCORE603E_85C30_1_CLOCK 16000000 /* 10,000,000 ?10->14.5 */
#define SCORE603E_85C30_1_CLOCK_X 16
/*
* Z85C30 Definations for the PMC serial chips
*/
#define SCORE603E_85C30_PMC_CLOCK 16000000 /* 10,000,000 ?10->14.5 */
#define SCORE603E_85C30_PMC_CLOCK_X 16
#define SCORE603E_85C30_2_CLOCK SCORE603E_85C30_PMC_CLOCK
#define SCORE603E_85C30_3_CLOCK SCORE603E_85C30_PMC_CLOCK
#define SCORE603E_85C30_4_CLOCK SCORE603E_85C30_PMC_CLOCK
#define SCORE603E_85C30_5_CLOCK SCORE603E_85C30_PMC_CLOCK
#define SCORE603E_85C30_2_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X
#define SCORE603E_85C30_3_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X
#define SCORE603E_85C30_4_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X
#define SCORE603E_85C30_5_CLOCK_X SCORE603E_85C30_PMC_CLOCK_X
#define SCORE603E_UNIVERSE_CHIP_ID 0x000010E3
/*
* FPGA Interupt Address Definations.
*/
#define SCORE603E_FPGA_VECT_DATA ((volatile uint16_t*)0xfd000040)
#define SCORE603E_FPGA_BIT1_15_0 ((volatile uint16_t*)0xfd000044)
#define SCORE603E_FPGA_MASK_DATA ((volatile uint16_t*)0xfd000048)
#define SCORE603E_FPGA_IRQ_INPUT ((volatile uint16_t*)0xfd00004c)
/*
* The PMC status word is at the PMC base address
*/
#define BSP_PMC_STATUS_ADDRESS (BSP_PMC_SERIAL_ADDRESS (0))
#define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80) /* SCC 422-1 */
#define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40) /* SCC 232-1 */
#define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20) /* SCC 422-2 */
#define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08) /* SCC 232-2 */
#define SCORE603E_PMC_CONTROL_ADDRESS BSP_PMC_SERIAL_ADDRESS(0x100000)
#define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)
#define PMC_SET_232_LOOPBACK(_word) (_word | 0x02)
#define PMC_CLEAR_232_LOOPBACK(_word) (_word & 0xfd)
#define PMC_SET_422_LOOPBACK(_word) (_word | 0x01)
#define PMC_CLEAR_422_LOOPBACK(_word) (_word & 0xfe)
/*
* Score603e Interupt Definations.
*/
/*
* BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID for the shared timer
* driver.
*/
#define BSP_TIMER_AVG_OVERHEAD 4 /* It typically takes xx clicks */
/* to start/stop the timer. */
#define BSP_TIMER_LEAST_VALID 1 /* Don't trust a value lower than this */
/*
* Convert decrement value to tenths of microsecnds (used by
* shared timer driver).
*
* + CPU has a 66.67 Mhz bus,
* + There are 4 bus cycles per click
* + We return value in 1/10 microsecond units.
* Modified following equation to integer equation to remove
* floating point math.
* (int) ((float)(_value) / ((66.67 * 0.1) / 4.0))
*/
#define BSP_Convert_decrementer( _value ) \
(int) (((_value) * 4000) / 6667)
#ifdef __cplusplus
}
#endif
#endif

68
c/src/lib/libbsp/powerpc/score603e/include/tm27.h
View File

@@ -1,68 +0,0 @@
/*
* @file
* @ingroup powerpc_score603e
* @brief Implementations for interrupt mechanisms for Time Test 27
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef _RTEMS_TMTEST27
#error "This is an RTEMS internal file you must not include directly."
#endif
#ifndef __tm27_h
#define __tm27_h
#include <bsp/irq.h>
/*
* Stuff for Time Test 27
*/
#define MUST_WAIT_FOR_INTERRUPT 1
void nullFunc() {}
static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
0,
(rtems_irq_enable)nullFunc,
(rtems_irq_disable)nullFunc,
(rtems_irq_is_enabled) nullFunc};
void Install_tm27_vector(void (*_handler)())
{
clockIrqData.hdl = _handler;
if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
printk("Error installing clock interrupt handler!\n");
rtems_fatal_error_occurred(1);
}
}
#define Cause_tm27_intr() \
do { \
uint32_t _clicks = 8; \
__asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Clear_tm27_intr() \
do { \
uint32_t _clicks = 0xffffffff; \
__asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
} while (0)
#define Lower_tm27_intr() \
do { \
uint32_t _msr = 0; \
_ISR_Set_level( 0 ); \
__asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
_msr |= 0x8002; \
__asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
} while (0)
#endif

180
c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
View File

@@ -1,180 +0,0 @@
/*
* FPGA.c -- Bridge for second and subsequent generations
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <bsp/irq.h>
#include <string.h>
#include <fcntl.h>
#include <assert.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <rtems/bspIo.h>
/*
* initialize FPGA
*/
void initialize_PCI_bridge (void)
{
/* Note: Accept DINKs setup of the PCI Bridge and don't
* change anything.
*/
}
void set_irq_mask(
uint16_t value
)
{
volatile uint16_t *loc;
loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
*loc = value;
}
uint16_t get_irq_mask( void )
{
volatile uint16_t *loc;
uint16_t value;
loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
value = *loc;
return value;
}
void mask_irq(
uint16_t irq_idx
)
{
uint16_t value;
uint32_t mask_idx = irq_idx;
value = get_irq_mask();
#if (HAS_PMC_PSC8)
switch (irq_idx + Score_IRQ_First ) {
case SCORE603E_85C30_4_IRQ:
case SCORE603E_85C30_2_IRQ:
case SCORE603E_85C30_5_IRQ:
case SCORE603E_85C30_3_IRQ:
mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
break;
default:
break;
}
#endif
value |= (0x1 << mask_idx);
set_irq_mask( value );
}
void unmask_irq(
uint16_t irq_idx
)
{
uint16_t value;
uint32_t mask_idx = irq_idx;
value = get_irq_mask();
#if (HAS_PMC_PSC8)
switch (irq_idx + Score_IRQ_First ) {
case SCORE603E_85C30_4_IRQ:
case SCORE603E_85C30_2_IRQ:
case SCORE603E_85C30_5_IRQ:
case SCORE603E_85C30_3_IRQ:
mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
break;
default:
break;
}
#endif
value &= (~(0x1 << mask_idx));
set_irq_mask( value );
}
void init_irq_data_register(void)
{
uint32_t index;
uint32_t i;
set_irq_mask( 0xffff );
/*
* Clear any existing interupts from the vector data register.
*/
for (i=0; i<20; i++) {
index = (*SCORE603E_FPGA_VECT_DATA);
if ( (index&0x10) != 0x10 )
break;
}
}
uint16_t read_and_clear_PMC_irq(
uint16_t irq
)
{
uint16_t status_word = irq;
status_word = (*BSP_PMC_STATUS_ADDRESS);
return status_word;
}
bool Is_PMC_IRQ(
uint32_t pmc_irq,
uint16_t status_word
)
{
bool result = false;
switch(pmc_irq) {
case SCORE603E_85C30_4_IRQ:
result = Is_PMC_85C30_4_IRQ( status_word ) ? true : false;
break;
case SCORE603E_85C30_2_IRQ:
result = Is_PMC_85C30_2_IRQ( status_word ) ? true : false;
break;
case SCORE603E_85C30_5_IRQ:
result = Is_PMC_85C30_5_IRQ( status_word ) ? true : false;
break;
case SCORE603E_85C30_3_IRQ:
result = Is_PMC_85C30_3_IRQ( status_word ) ? true : false;
break;
default:
assert( 0 );
break;
}
return result;
}
uint16_t read_and_clear_irq(void)
{
uint16_t irq;
irq = (*SCORE603E_FPGA_VECT_DATA);
Processor_Synchronize();
if ((irq & 0xffff0) != 0x10) {
printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
return (irq | 0x80);
}
irq &=0xf;
irq += Score_IRQ_First;
return irq;
}

495
c/src/lib/libbsp/powerpc/score603e/irq/irq.c
View File

@@ -1,495 +0,0 @@
/*
* This file contains the implementation of the function described in irq.h
*
* Copyright (C) 1998, 1999 valette@crf.canon.fr
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <stdlib.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/VME.h>
#include <rtems/score/apiext.h> /* for post ISR signal processing */
#include <libcpu/io.h>
#include <bsp/vectors.h>
#include <stdlib.h>
#include <rtems/bspIo.h> /* for printk */
/*
* default handler connected on each irq after bsp initialization
*/
static rtems_irq_connect_data default_rtems_entry;
/*
* location used to store initial tables used for interrupt
* management.
*/
static rtems_irq_global_settings* internal_config;
static rtems_irq_connect_data* rtems_hdl_tbl;
/*
* Check if IRQ is an ISA IRQ
*/
static inline int is_isa_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
);
}
/*
* Check if IRQ is an pci IRQ
*/
static inline int is_pci_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
);
}
/*
* Check if IRQ is a Processor IRQ
*/
static inline int is_processor_irq(const rtems_irq_number irqLine)
{
return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
);
}
/*
* ------------------------ RTEMS Irq helper functions ----------------
*/
/*
* This function check that the value given for the irq line
* is valid.
*/
static int isValidInterrupt(int irq)
{
if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
return 0;
return 1;
}
/*
* ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
rtems_irq_connect_data* vchain;
printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
rtems_interrupt_disable(level);
if ( (int)rtems_hdl_tbl[irq->name].next_handler == -1 ) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected to an unshared handler\n",irq->name);
return 0;
}
vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
/* save off topmost handler */
vchain[0]= rtems_hdl_tbl[irq->name];
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
/* link chain to new topmost handler */
rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
/*
* XXX FIX ME
*/
if (is_pci_irq(irq->name)) {
}
if (is_processor_irq(irq->name)) {
/*
* Enable exception at processor level
*/
}
/*
* Enable interrupt on device
*/
if (irq->on)
irq->on(irq);
rtems_interrupt_enable(level);
return 1;
}
/*
* This function disables a given XXX interrupt
*/
rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
{
/* XXX FIX ME!!!! */
printk("bsp_interrupt_vector_disable: 0x%x\n", irqLine );
return RTEMS_SUCCESSFUL;
}
rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
{
/* XXX FIX ME!!!! */
printk("bsp_interrupt_vector_enable: 0x%x\n", irqLine );
return RTEMS_SUCCESSFUL;
}
/*
* ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via i386_get_current_idt_entry
* and then disconnect it using i386_delete_idt_entry.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
rtems_interrupt_disable(level);
if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
rtems_interrupt_enable(level);
printk("IRQ vector %d already connected\n",irq->name);
return 0;
}
/*
* store the data provided by user
*/
rtems_hdl_tbl[irq->name] = *irq;
rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
/* XXX -FIX ME !! */
if (is_pci_irq(irq->name)) {
/*
* Enable interrupt
*/
printk("is_pci_irq = TRUE - FIX THIS!\n");
}
if (is_processor_irq(irq->name)) {
/*
* Enable exception at processor level
*/
printk("is_processor_irq = TRUE : Fix This\n");
}
/*
* Enable interrupt on device
*/
if (irq->on) {
printk("Call 0x%x\n", irq->on );
irq->on(irq);
}
rtems_interrupt_enable(level);
return 1;
}
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
printk(" BSP_get_current_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
return 0;
}
rtems_interrupt_disable(level);
*irq = rtems_hdl_tbl[irq->name];
rtems_interrupt_enable(level);
return 1;
}
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
rtems_interrupt_level level;
printk(" BSP_remove_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
return 0;
}
/*
* Check if default handler is actually connected. If not issue an error.
* You must first get the current handler via i386_get_current_idt_entry
* and then disconnect it using i386_delete_idt_entry.
* RATIONALE : to always have the same transition by forcing the user
* to get the previous handler before accepting to disconnect.
*/
rtems_interrupt_disable(level);
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
rtems_interrupt_enable(level);
return 0;
}
if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
{
int found = 0;
for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
(vchain->hdl != default_rtems_entry.hdl);
(pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
{
if( vchain->hdl == irq->hdl )
{
found= -1; break;
}
}
if( !found )
{
rtems_interrupt_enable(level);
return 0;
}
}
else
{
if (rtems_hdl_tbl[irq->name].hdl != irq->hdl)
{
rtems_interrupt_enable(level);
return 0;
}
}
/* XXX - FIX ME !! */
if (is_pci_irq(irq->name)) {
/*
* disable interrupt
*/
}
if (is_processor_irq(irq->name)) {
/*
* disable exception at processor level
*/
}
/*
* Disable interrupt on device
*/
if (irq->off)
irq->off(irq);
/*
* restore the default irq value
*/
if( !vchain )
{
/* single handler vector... */
rtems_hdl_tbl[irq->name] = default_rtems_entry;
}
else
{
if( pchain )
{
/* non-first handler being removed */
pchain->next_handler = vchain->next_handler;
}
else
{
/* first handler isn't malloc'ed, so just overwrite it. Since
the contents of vchain are being struct copied, vchain itself
goes away */
rtems_hdl_tbl[irq->name]= *vchain;
}
free(vchain);
}
rtems_interrupt_enable(level);
return 1;
}
/*
* RTEMS Global Interrupt Handler Management Routines
*/
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
{
int i;
rtems_interrupt_level level;
/*
* Store various code accelerators
*/
internal_config = config;
default_rtems_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
printk(" BSP_rtems_irq_mngt_set\n");
rtems_interrupt_disable(level);
/*
* set up internal tables used by rtems interrupt prologue
*/
/*
* XXX - FIX ME !!!
*/
for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
{
rtems_irq_connect_data* vchain;
for( vchain = &rtems_hdl_tbl[i];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
if (vchain->on)
vchain->on(vchain);
}
}
}
else {
/* if (rtems_hdl_tbl[i].off) rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); */
{
rtems_irq_connect_data* vchain;
for( vchain = &rtems_hdl_tbl[i];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
if (vchain->off)
vchain->off(vchain);
}
}
}
}
/*
* finish with Processor exceptions handled like IRQ
*/
for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER; i++){
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
{
rtems_irq_connect_data* vchain;
for( vchain = &rtems_hdl_tbl[i];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
if (vchain->on)
vchain->on(vchain);
}
}
}
else {
{
rtems_irq_connect_data* vchain;
for( vchain = &rtems_hdl_tbl[i];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
if (vchain->off)
vchain->off(vchain);
}
}
}
}
rtems_interrupt_enable(level);
return 1;
}
int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
{
*config = internal_config;
return 0;
}
unsigned BSP_spuriousIntr = 0;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
{
register unsigned int irq;
register unsigned msr;
register unsigned new_msr;
if (excNum == ASM_DEC_VECTOR) {
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
_CPU_MSR_SET(msr);
return 0;
}
irq = read_and_clear_irq();
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
_CPU_MSR_SET(new_msr);
/* rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); */
{
rtems_irq_connect_data* vchain;
for( vchain = &rtems_hdl_tbl[irq];
((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl);
vchain = (rtems_irq_connect_data*)vchain->next_handler )
{
vchain->hdl(vchain->handle);
}
}
_CPU_MSR_SET(msr);
return 0;
}
rtems_status_code bsp_interrupt_facility_initialize(void)
{
/* Install exception handler */
if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
return RTEMS_IO_ERROR;
}
if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
return RTEMS_IO_ERROR;
}
if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
return RTEMS_IO_ERROR;
}
return RTEMS_SUCCESSFUL;
}
void bsp_interrupt_handler_default( rtems_vector_number vector )
{
if (vector != BSP_DECREMENTER) {
printk( "Spurious interrupt: 0x%08x\n", vector);
}
}

153
c/src/lib/libbsp/powerpc/score603e/irq/irq.h
View File

@@ -1,153 +0,0 @@
/* irq.h
*
* This include file describe the data structure and the functions implemented
* by RTEMS to write interrupt handlers.
*
* This code is heavilly inspired by the public specification of STREAM V2
* that can be found at :
*
* <http://www.chorus.com/Documentation/index.html> by following
* the STREAM API Specification Document link.
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef BSP_POWERPC_IRQ_H
#define BSP_POWERPC_IRQ_H
#define BSP_SHARED_HANDLER_SUPPORT 1
#include <rtems/irq.h>
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/*
* rtems_irq_number Definitions
*/
/*
* ISA IRQ handler related definitions
*/
#define BSP_ISA_IRQ_NUMBER (16)
#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
/*
* PCI IRQ handlers related definitions
*/
#define BSP_PCI_IRQ_NUMBER (16)
#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
/*
* PMC IRQ
*/
#define BSP_PMC_IRQ_NUMBER (4)
#define BSP_PMC_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
#define BSP_PMC_IRQ_MAX_OFFSET (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
/*
* PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
* handler might be connected
*/
#define BSP_PROCESSOR_IRQ_NUMBER (1)
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
/* Misc vectors for OPENPIC irqs (IPI, timers)
*/
#define BSP_MISC_IRQ_NUMBER (8)
#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
/*
* Summary
*/
#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
/*
* Some Processor execption handled as RTEMS IRQ symbolic name definition
*/
#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
/*
* First Score Unique IRQ
*/
#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
/*
* The Following Are part of a Score603e FPGA.
*/
#define SCORE603E_IRQ00 ( Score_IRQ_First + 0 )
#define SCORE603E_IRQ01 ( Score_IRQ_First + 1 )
#define SCORE603E_IRQ02 ( Score_IRQ_First + 2 )
#define SCORE603E_IRQ03 ( Score_IRQ_First + 3 )
#define SCORE603E_IRQ04 ( Score_IRQ_First + 4 )
#define SCORE603E_IRQ05 ( Score_IRQ_First + 5 )
#define SCORE603E_IRQ06 ( Score_IRQ_First + 6 )
#define SCORE603E_IRQ07 ( Score_IRQ_First + 7 )
#define SCORE603E_IRQ08 ( Score_IRQ_First + 8 )
#define SCORE603E_IRQ09 ( Score_IRQ_First + 9 )
#define SCORE603E_IRQ10 ( Score_IRQ_First + 10 )
#define SCORE603E_IRQ11 ( Score_IRQ_First + 11 )
#define SCORE603E_IRQ12 ( Score_IRQ_First + 12 )
#define SCORE603E_IRQ13 ( Score_IRQ_First + 13 )
#define SCORE603E_IRQ14 ( Score_IRQ_First + 14 )
#define SCORE603E_IRQ15 ( Score_IRQ_First + 15 )
#define SCORE603E_TIMER1_IRQ SCORE603E_IRQ00
#define SCORE603E_TIMER2_IRQ SCORE603E_IRQ01
#define SCORE603E_TIMER3_IRQ SCORE603E_IRQ02
#define SCORE603E_85C30_1_IRQ SCORE603E_IRQ03
#define SCORE603E_85C30_0_IRQ SCORE603E_IRQ04
#define SCORE603E_RTC_IRQ SCORE603E_IRQ05
#define SCORE603E_PCI_IRQ_0 SCORE603E_IRQ06
#define SCORE603E_PCI_IRQ_1 SCORE603E_IRQ07
#define SCORE603E_PCI_IRQ_2 SCORE603E_IRQ08
#define SCORE603E_PCI_IRQ_3 SCORE603E_IRQ09
#define SCORE603E_UNIVERSE_IRQ SCORE603E_IRQ10
#define SCORE603E_1553_IRQ SCORE603E_IRQ11
#define SCORE603E_MAIL_BOX_IRQ_0 SCORE603E_IRQ12
#define SCORE603E_MAIL_BOX_IRQ_1 SCORE603E_IRQ13
#define SCORE603E_MAIL_BOX_IRQ_2 SCORE603E_IRQ14
#define SCORE603E_MAIL_BOX_IRQ_3 SCORE603E_IRQ15
/*
* The Score FPGA maps all interrupts comming from the PMC card to
* the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
* read to indicate which interrupt was chained to the FPGA.
*/
#define SCORE603E_IRQ16 ( Score_IRQ_First + 16 )
#define SCORE603E_IRQ17 ( Score_IRQ_First + 17 )
#define SCORE603E_IRQ18 ( Score_IRQ_First + 18 )
#define SCORE603E_IRQ19 ( Score_IRQ_First + 19 )
/*
* IRQ'a read from the PMC card
*/
#define SCORE603E_85C30_4_IRQ SCORE603E_IRQ16 /* SCC 422-1 */
#define SCORE603E_85C30_2_IRQ SCORE603E_IRQ17 /* SCC 232-1 */
#define SCORE603E_85C30_5_IRQ SCORE603E_IRQ18 /* SCC 422-2 */
#define SCORE603E_85C30_3_IRQ SCORE603E_IRQ19 /* SCC 232-2 */
#define MAX_BOARD_IRQS SCORE603E_IRQ19
extern void BSP_rtems_irq_mng_init(unsigned cpuId);
#ifdef __cplusplus
}
#endif
#endif
#endif

131
c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
View File

@@ -1,131 +0,0 @@
/* irq_init.c
*
* This file contains the implementation of rtems initialization
* related to interrupt handling.
*
* CopyRight (C) 1999 valette@crf.canon.fr
*
* Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
* to make it valid for MVME2300 Motorola boards.
*
* Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
* Use the new interface to openpic_init
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <libcpu/io.h>
#include <libcpu/spr.h>
#include <bsp/pci.h>
#include <bsp/residual.h>
#include <bsp/irq.h>
#include <bsp.h>
#include <bsp/vectors.h>
#include <rtems/bspIo.h>
#define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
#define SCAN_PCI_PRINT 1
#define TRACE_IRQ_INIT 0
typedef struct {
unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */
unsigned char device;
unsigned char function;
} pci_isa_bridge_device;
pci_isa_bridge_device* via_82c586 = 0;
extern unsigned int external_exception_vector_prolog_code_size[];
extern void external_exception_vector_prolog_code(void);
extern unsigned int decrementer_exception_vector_prolog_code_size[];
extern void decrementer_exception_vector_prolog_code(void);
static void IRQ_Default_rtems_irq_hdl(
rtems_irq_hdl_param ptr
)
{
}
static void IRQ_Default_rtems_irq_enable(
const struct __rtems_irq_connect_data__ *ptr
)
{
}
static void IRQ_Default_rtems_irq_disable(
const struct __rtems_irq_connect_data__ *ptr
)
{
}
static int IRQ_Default_rtems_irq_is_enabled(
const struct __rtems_irq_connect_data__ *ptr)
{
return 1;
}
static rtems_irq_connect_data rtemsIrq[BSP_IRQ_NUMBER];
static rtems_irq_global_settings initial_config;
static rtems_irq_connect_data defaultIrq = {
.name = 0,
.hdl = IRQ_Default_rtems_irq_hdl,
.handle = NULL,
.on = IRQ_Default_rtems_irq_enable,
.on = IRQ_Default_rtems_irq_disable,
.isOn = IRQ_Default_rtems_irq_is_enabled
};
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
/*
* This code assumes the exceptions management setup has already
* been done. We just need to replace the exceptions that will
* be handled like interrupt. On mcp750/mpc750 and many PPC processors
* this means the decrementer exception and the external exception.
*/
void BSP_rtems_irq_mng_init(unsigned cpuId)
{
int i;
/*
* First initialize the Interrupt management hardware
*/
/*
* Initialize RTEMS management interrupt table
*/
/*
* re-init the rtemsIrq table
*/
for (i = 0; i < BSP_IRQ_NUMBER; i++) {
irqPrioTable[i] = 8;
rtemsIrq[i] = defaultIrq;
rtemsIrq[i].name = i;
#ifdef BSP_SHARED_HANDLER_SUPPORT
rtemsIrq[i].next_handler = NULL;
#endif
}
/*
* Init initial Interrupt management config
*/
initial_config.irqNb = BSP_IRQ_NUMBER;
initial_config.defaultEntry = defaultIrq;
initial_config.irqHdlTbl = rtemsIrq;
initial_config.irqBase = BSP_LOWEST_OFFSET;
initial_config.irqPrioTbl = irqPrioTable;
if (!BSP_rtems_irq_mngt_set(&initial_config)) {
/*
* put something here that will show the failure...
*/
BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
}
#ifdef TRACE_IRQ_INIT
printk("RTEMS IRQ management is now operational\n");
#endif
}

82
c/src/lib/libbsp/powerpc/score603e/irq/no_pic.c
View File

@@ -1,82 +0,0 @@
/*
*
* This file contains the implementation of the function described in irq.h
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/irq_supp.h>
#include <bsp/vectors.h>
static rtems_irq_connect_data *rtems_hdl_tbl;
static rtems_irq_connect_data dflt_entry;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
int C_dispatch_irq_handler(
BSP_Exception_frame *frame,
unsigned int excNum
)
{
register unsigned int irq;
#if (HAS_PMC_PSC8)
uint16_t check_irq;
uint16_t status_word;
#endif
if (excNum == ASM_DEC_VECTOR) {
bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, dflt_entry.hdl);
return 0;
}
irq = read_and_clear_irq();
#if (HAS_PMC_PSC8)
if (irq == SCORE603E_PCI_IRQ_0) {
status_word = read_and_clear_PMC_irq( irq );
for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
if ( Is_PMC_IRQ( check_irq, status_word )) {
bsp_irq_dispatch_list_base(rtems_hdl_tbl, check_irq, dflt_entry.hdl);
}
}
} else
#endif
{
bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, dflt_entry.hdl);
}
return 0;
}
void
BSP_enable_irq_at_pic(const rtems_irq_number irq)
{
uint16_t vec_idx = irq - Score_IRQ_First;
unmask_irq( vec_idx );
}
int
BSP_disable_irq_at_pic(const rtems_irq_number irq)
{
uint16_t vec_idx = irq - Score_IRQ_First;
unmask_irq( vec_idx );
return 0;
}
int
BSP_setup_the_pic(rtems_irq_global_settings *config)
{
dflt_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
init_irq_data_register();
return 1;
}

29
c/src/lib/libbsp/powerpc/score603e/make/custom/score603e.cfg
View File

@@ -1,29 +0,0 @@
#
# Config file for a PowerPC 603e based Vista VMEbus Single Board Computer.
# This BSP should work with the following models:
#
# + Vista SCORE 603e
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=powerpc
RTEMS_CPU_MODEL=mpc6xx
# This is the actual bsp directory used during the build process.
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
CPU_CFLAGS = -mcpu=603e -Dppc603e
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g -fno-keep-inline-functions
define bsp-post-link
$(default-bsp-post-link)
$(OBJCOPY) -O srec $(basename $@)$(EXEEXT) $(basename $@).s1
sed -e 's/.$$//' $(basename $@).s1 | \
$(PACKHEX) >$(basename $@)$(DOWNEXT)
rm -f $(basename $@).s1
endef

103
c/src/lib/libbsp/powerpc/score603e/preinstall.am
View File

@@ -1,103 +0,0 @@
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
all-am: $(PREINSTALL_FILES)
PREINSTALL_FILES =
CLEANFILES = $(PREINSTALL_FILES)
all-local: $(TMPINSTALL_FILES)
TMPINSTALL_FILES =
CLEANFILES += $(TMPINSTALL_FILES)
$(PROJECT_LIB)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_LIB)
@: > $(PROJECT_LIB)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
$(PROJECT_INCLUDE)/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)
@: > $(PROJECT_INCLUDE)/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
$(PROJECT_INCLUDE)/bsp/$(dirstamp):
@$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
@: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
$(PROJECT_INCLUDE)/gen2.h: include/gen2.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gen2.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/gen2.h
$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
$(PROJECT_INCLUDE)/bsp/PCI.h: PCI_bus/PCI.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/PCI.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/PCI.h
$(PROJECT_INCLUDE)/bsp/residual.h: ../../powerpc/shared/residual/residual.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/residual.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/residual.h
$(PROJECT_INCLUDE)/bsp/pnp.h: ../../powerpc/shared/residual/pnp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pnp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pnp.h
$(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../powerpc/shared/console/consoleIo.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/consoleIo.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)

126
c/src/lib/libbsp/powerpc/score603e/start/start.S
View File

@@ -1,126 +0,0 @@
/*
* This is based on the mvme-crt0.S file from libgloss/rs6000.
* crt0.S -- startup file for PowerPC systems.
*
* Copyright (c) 1995 Cygnus Support
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#include "ppc-asm.h"
.file "start.s"
.section ".got2","aw"
.align 2
.LCTOC1 = .+32768
.extern FUNC_NAME(atexit)
.globl FUNC_NAME(__atexit)
.section ".sdata","aw"
.align 2
FUNC_NAME(__atexit): /* tell C's eabi-ctor's we have an atexit function */
.long FUNC_NAME(atexit)@fixup /* and that it is to register __do_global_dtors */
.section ".fixup","aw"
.align 2
.long FUNC_NAME(__atexit)
.section ".got2","aw"
.Ltable = .-.LCTOC1
.long .LCTOC1 /* address we think .LCTOC1 is loaded at */
.Lbss_start = .-.LCTOC1
.long _edata /* includes sbss and bss */
.Lend = .-.LCTOC1
.long _end
.Lstack = .-.LCTOC1 /* stack address if set by user */
.long __stack
.text
.Lptr:
.long .LCTOC1-.Laddr
.globl start
.globl _start
.type start,@function
.type _start,@function
start:
_start:
b past_constants
/* Set MSR */
.long _etext /* end of code space */
.long _edata /* end of code and data space */
past_constants:
lis r5,0
mr r4,r5
ori r4,r4,0x0000 /* 0x2030 */
mtmsr r4
/* The first generation board needed initialization here but the */
/* second does not. */
bl .Laddr /* get current address */
.Laddr:
mflr r4 /* real address of .Laddr */
lwz r5,(.Lptr-.Laddr)(r4) /* linker generated address of .LCTOC1 */
add r5,r5,r4 /* correct to real pointer */
lwz r4,.Ltable(r5) /* get linker's idea of where .Laddr is */
subf r4,r4,r5 /* calculate difference between where linked and current */
/* clear bss */
lwz r6,.Lbss_start(r5) /* calculate beginning of the BSS */
lwz r7,.Lend(r5) /* calculate end of the BSS */
add r6,r6,r4 /* adjust pointers */
add r7,r7,r4
cmplw 1,r6,r7
bc 4,4,.Ldone
subf r8,r6,r7 /* number of bytes to zero */
srwi r9,r8,2 /* number of words to zero */
mtctr r9
li r0,0 /* zero to clear memory */
addi r6,r6,-4 /* adjust so we can use stwu */
.Lloop:
stwu r0,4(r6) /* zero bss */
bdnz .Lloop
.Ldone:
lwz r0,.Lstack(r5) /* stack address or 0 */
cmplwi 1,r0,0 /* equal to 0? */
bc 12,6,.Lnostack /* use default stack if == 0 */
mr sp,r0 /* use user defined stack */
.Lnostack:
lis r13,_SDA_BASE_@ha
la r13,_SDA_BASE_@l(r13) /* Read-write small data */
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0
stw r0,0(sp) /* clear back chain */
stwu sp,-56(sp) /* push another stack frame */
li r3, 0 /* command line */
/* Let her rip */
bl FUNC_NAME(boot_card)
/* return value from boot_card is argument to exit */
bl FUNC_NAME(exit)
trap
.Lstart:
.size _start,.Lstart-_start

142
c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
View File

@@ -1,142 +0,0 @@
/* Hwr_init.c
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#define PPC603e_SPR_HID0 1008
#define PPC603e_SPR_HID1 1009
#define PPC603e_SPR_IBAT0U 528
#define PPC603e_SPR_IBAT0L 529
#define PPC603e_SPR_DBAT0U 536
#define PPC603e_SPR_DBAT0L 537
#define PPC603e_SPR_IBAT1U 530
#define PPC603e_SPR_IBAT1L 531
#define PPC603e_SPR_DBAT1U 538
#define PPC603e_SPR_DBAT1L 539
#define PPC603e_SPR_IBAT2U 532
#define PPC603e_SPR_IBAT2L 533
#define PPC603e_SPR_DBAT2U 540
#define PPC603e_SPR_DBAT2L 541
#define PPC603e_SPR_IBAT3U 534
#define PPC603e_SPR_IBAT3L 535
#define PPC603e_SPR_DBAT3U 542
#define PPC603e_SPR_DBAT3L 543
#define PPC603e_SPR_DMISS 976
#define PPC603e_SPR_DCMP 977
#define PPC603e_SPR_HASH1 978
#define PPC603e_SPR_HASH2 979
#define PPC603e_SPR_IMISS 980
#define PPC603e_SPR_ICMP 981
#define PPC603e_SPR_RPA 982
#define PPC603e_SPR_SDR1 25
#define PPC603e_SPR_PVR 287
#define PPC603e_SPR_DAR 19
#define PPC603e_SPR_SPRG0 272
#define PPC603e_SPR_SPRG1 273
#define PPC603e_SPR_SPRG2 274
#define PPC603e_SPR_SPRG3 275
#define PPC603e_SPR_DSISR 18
#define PPC603e_SPR_SRR0 26
#define PPC603e_SPR_SRR1 27
#define PPC603e_SPR_TBL_WRITE 284
#define PPC603e_SPR_TBU_WRITE 285
#define PPC603e_SPR_DEC 22
#define PPC603e_SPR_IABR 1010
#define PPC603e_SPR_EAR 282
#define PCI_MEM_CMD (SCORE603E_PCI_MEM_BASE >> 16)
typedef struct {
uint32_t counter_1_100;
uint32_t counter_hours;
uint32_t counter_min;
uint32_t counter_sec;
uint32_t counter_month;
uint32_t counter_date;
uint32_t counter_year;
uint32_t counter_day_of_week;
uint32_t RAM_1_100;
uint32_t RAM_hours;
uint32_t RAM_month;
uint32_t RAM_date;
uint32_t RAM_year;
uint32_t RAM_day_of_week;
uint32_t interupt_status_mask;
uint32_t command_register;
}Harris_RTC;
void init_RTC(void)
{
volatile Harris_RTC *the_RTC;
the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS;
the_RTC->command_register = 0x0;
}
void init_PCI(void)
{
/* DINK Monitor setsup and uses all 4 BAT registers. */
/* The fourth BAT register can be modified to access this area */
}
#define PPC_Get_HID0( _value ) \
do { \
_value = 0; /* to avoid warnings */ \
__asm__ volatile( \
"mfspr %0, 0x3f0;" /* get HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
#define PPC_Set_HID0( _value ) \
do { \
__asm__ volatile( \
"isync;" \
"mtspr 0x3f0, %0;" /* load HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
void instruction_cache_enable (void)
{
uint32_t value;
/*
* Enable the instruction cache
*/
PPC_Get_HID0( value );
value |= 0x00008000; /* Set ICE bit */
PPC_Set_HID0( value );
}
void data_cache_enable (void)
{
uint32_t value;
/*
* enable data cache
*/
PPC_Get_HID0( value );
value |= 0x00004000; /* set DCE bit */
PPC_Set_HID0( value );
}

232
c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
View File

@@ -1,232 +0,0 @@
/*
* This routine does the bulk of the system initialization.
*/
/*
* COPYRIGHT (c) 1989-2010.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <string.h>
#include <bsp.h>
#include <bsp/bootcard.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <rtems/bspIo.h>
#include <rtems/counter.h>
#include <libcpu/cpuIdent.h>
#include <bsp/irq.h>
#define DEBUG 0
/*
* Where the heap starts; is used by bsp_pretasking_hook;
*/
unsigned int BSP_heap_start;
/*
* PCI Bus Frequency
*/
unsigned int BSP_bus_frequency;
/*
* processor clock frequency
*/
unsigned int BSP_processor_frequency;
/*
* Time base divisior (how many tick for 1 second).
* Note: Calibrated with an application using a 20ms timer and
* a scope.
*/
unsigned int BSP_time_base_divisor = 3960;
/*
* Driver configuration parameters
*/
uint32_t bsp_clicks_per_usec;
/*
* Memory on this board.
*/
extern char RamSize[];
uint32_t BSP_mem_size;
extern unsigned long __rtems_end[];
void BSP_panic(char *s)
{
printk("%s PANIC %s\n",_RTEMS_version, s);
__asm__ __volatile ("sc");
}
void _BSP_Fatal_error(unsigned int v)
{
printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
__asm__ __volatile ("sc");
}
/*
* bsp_predriver_hook
*
* Before drivers are setup initialize interupt vectors.
*/
void init_RTC(void);
void initialize_PMC(void);
void bsp_predriver_hook(void)
{
init_PCI();
initialize_universe();
#if DEBUG
printk("bsp_predriver_hook: initialize_PCI_bridge\n");
#endif
initialize_PCI_bridge ();
#if (HAS_PMC_PSC8)
#if DEBUG
printk("bsp_predriver_hook: initialize_PMC\n");
#endif
initialize_PMC();
#endif
#if DEBUG
printk("bsp_predriver_hook: End of routine\n");
#endif
}
/*PAGE
*
* initialize_PMC
*/
void initialize_PMC(void) {
volatile uint32_t *PMC_addr;
uint32_t data;
/*
* Clear status, enable SERR and memory space only.
*/
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x020080cc;
#if DEBUG
printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, 0x020080cc);
#endif
/*
* set PMC base address.
*/
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
#if DEBUG
printk("initialize_PMC: 0x%x = 0x%x\n", PMC_addr, ((BSP_PCI_REGISTER_BASE >> 24) & 0x3f));
#endif
PMC_addr = (volatile uint32_t*)
BSP_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
#if DEBUG
printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data );
printk("initialize_PMC: Read 0x%x (0x%x)\n", PMC_addr, data & 0xfc );
#endif
*PMC_addr = data & 0xfc;
}
/*PAGE
*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
void bsp_start( void )
{
unsigned int msr_value = 0x0000;
uintptr_t intrStackStart;
uintptr_t intrStackSize;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
rtems_bsp_delay( 1000 );
/*
* Zero out lots of memory
*/
#if DEBUG
printk("bsp_start: Zero out lots of memory\n");
#endif
BSP_processor_frequency = 266000000;
BSP_bus_frequency = 66000000;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
* later...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
printk("Cpu: 0x%x Revision: %d\n", myCpu, myCpuRevision);
printk("Cpu %s\n", get_ppc_cpu_type_name(myCpu) );
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uintptr_t) __rtems_end;
intrStackSize = rtems_configuration_get_interrupt_stack_size();
printk("Interrupt Stack Start: 0x%x Size: 0x%x Heap Start: 0x%x\n",
intrStackStart, intrStackSize, BSP_heap_start
);
BSP_mem_size = (uint32_t) RamSize;
printk("BSP_mem_size: %p\n", RamSize );
/*
* Initialize default raw exception handlers.
*/
ppc_exc_initialize(intrStackStart, intrStackSize);
msr_value = 0x2030;
_CPU_MSR_SET( msr_value );
__asm__ volatile("sync; isync");
/*
* initialize the device driver parameters
*/
#if DEBUG
printk("bsp_start: set clicks poer usec\n");
#endif
bsp_clicks_per_usec = 66 / 4;
rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000);
#if BSP_DATA_CACHE_ENABLED
#if DEBUG
printk("bsp_start: cache_enable\n");
#endif
instruction_cache_enable ();
data_cache_enable ();
#if DEBUG
printk("bsp_start: END BSP_DATA_CACHE_ENABLED\n");
#endif
#endif
/*
* Initalize RTEMS IRQ system
*/
#if DEBUG
printk("bspstart: Call BSP_rtems_irq_mng_init\n");
#endif
BSP_rtems_irq_mng_init(0);
#if DEBUG
printk("bsp_start: end BSPSTART\n");
ShowBATS();
#endif
}

166
c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
View File

@@ -1,166 +0,0 @@
/*
* These routines handle the external exception. Multiple ISRs occur off
* of this one interrupt.
*
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/chain.h>
#include <rtems/bspIo.h>
#include <assert.h>
#include <stdio.h> /* for sprintf */
/*
* Proto types for this file
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
);
#define NUM_LIRQ_HANDLERS 20
#define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
/*
* Structure to for one of possible multiple interrupt handlers for
* a given interrupt.
*/
typedef struct
{
rtems_chain_node Node;
rtems_isr_entry handler; /* isr routine */
rtems_vector_number vector; /* vector number */
} EE_ISR_Type;
/* Note: The following will not work if we add a method to remove
* handlers at a later time.
*/
EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS];
uint16_t Nodes_Used;
rtems_chain_control ISR_Array [NUM_LIRQ];
/* XXX */
void init_irq_data_register(void);
void Init_EE_mask_init(void)
{
}
/*
* This routine installs one of multiple ISRs for the general purpose
* inerrupt.
*/
rtems_isr_entry set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
)
{
uint16_t vec_idx = vector - Score_IRQ_First;
uint32_t index;
assert (Nodes_Used < NUM_LIRQ_HANDLERS);
/*
* If we have already installed this handler for this vector, then
* just reset it.
*/
for ( index=0 ; index <= Nodes_Used ; index++ ) {
if ( ISR_Nodes[index].vector == vector &&
ISR_Nodes[index].handler == handler )
return NULL;
}
/*
* Doing things in this order makes them more atomic
*/
Nodes_Used++;
index = Nodes_Used - 1;
ISR_Nodes[index].handler = handler;
ISR_Nodes[index].vector = vector;
/* printf( "Vector Index: %04x, Vector: %d (%x)\n",
vec_idx, vector, vector); */
rtems_chain_append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
/*
* Unmask the interrupt.
*/
unmask_irq( vec_idx );
return NULL;
}
/*
* This interrupt service routine is called for an External Exception.
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
)
{
uint16_t index;
EE_ISR_Type *node;
uint16_t value;
#if (HAS_PMC_PSC8)
uint16_t PMC_irq;
uint16_t check_irq;
uint16_t status_word;
#endif
index = read_and_clear_irq();
if ( index >= NUM_LIRQ ) {
printk( "ERROR:: Invalid interrupt number (%02x)\n", index );
return;
}
#if (HAS_PMC_PSC8)
PMC_irq = SCORE603E_PCI_IRQ_0 - SCORE603E_IRQ00;
if (index == PMC_irq) {
status_word = read_and_clear_PMC_irq( index );
for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
if ( Is_PMC_IRQ( check_irq, status_word )) {
index = check_irq - SCORE603E_IRQ00;
node = (EE_ISR_Type *)(ISR_Array[ index ].first);
if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
printk ("ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
value = get_irq_mask();
printk(" Mask = %02x\n", value);
}
while ( !rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
(*node->handler)( node->vector );
node = (EE_ISR_Type *) node->Node.next;
}
}
}
}
else
#endif
{
node = (EE_ISR_Type *)(ISR_Array[ index ].first);
if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
printk( "ERROR:: interrupt %02x has no isr\n", index);
value = get_irq_mask();
printk(" Mask = %02x\n", value);
return;
}
while ( !rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
(*node->handler)( node->vector );
node = (EE_ISR_Type *) node->Node.next;
}
}
}

248
c/src/lib/libbsp/powerpc/score603e/startup/linkcmds
View File

@@ -1,248 +0,0 @@
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
OUTPUT_ARCH(powerpc)
ENTRY(_start)
/*
* Number of Decrementer countdowns per millisecond
*
* Calculated by: (66 Mhz * 1000) / 4 cycles per click
*/
PROVIDE(CPU_PPC_CLICKS_PER_MS = 16500);
RamBase = DEFINED(RamBase) ? RamBase : 0x0;
RamSize = DEFINED(RamSize) ? RamSize : 31M;
MEMORY
{
VECTORS : ORIGIN = 0, LENGTH = 64K
RAM : ORIGIN = 1M, LENGTH = 31M
EPROM : ORIGIN = 0xFFF00000, LENGTH = 0x80000
}
SECTIONS
{
.vectors 0x00100 :
{
*(.vectors)
}
/* Read-only sections, merged into text segment: */
/* SDS ROM worked at 0x30000 */
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.dyn :
{
*(.rel.init)
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
*(.rel.fini)
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
*(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
*(.rel.ctors)
*(.rel.dtors)
*(.rel.got)
*(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
*(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
*(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
*(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
} >RAM
.rela.dyn :
{
*(.rela.init)
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
*(.rela.fini)
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
*(.rela.ctors)
*(.rela.dtors)
*(.rela.got)
*(.rela.got1)
*(.rela.got2)
*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
} >RAM
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.plt : { *(.plt) }
.text 0x100000:
{
*(.text*)
*(.gnu.linkonce.t.*)
*(.descriptors)
/*
* Special FreeBSD sysctl sections.
*/
. = ALIGN (16);
__start_set_sysctl_set = .;
*(set_sysctl_*);
__stop_set_sysctl_set = ABSOLUTE(.);
*(set_domain_*);
*(set_pseudo_*);
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >RAM
.init : { _init = .; __init = .; *(.init) } >RAM
.fini : { _fini = .; __fini = .; *(.fini) } >RAM
.rodata : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } >RAM
.rodata1 : { *(.rodata1) } >RAM
.tdata : {
_TLS_Data_begin = .;
*(.tdata .tdata.* .gnu.linkonce.td.*)
_TLS_Data_end = .;
} >RAM
.tbss : {
_TLS_BSS_begin = .;
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
_TLS_BSS_end = .;
} >RAM
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
.eh_frame : { *(.eh_frame) } >RAM
_etext = .;
PROVIDE (_etext = .);
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) } >RAM
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >RAM
PROVIDE (__SBSS2_END__ = .);
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
. = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
. = ALIGN(8) + 0x40000;
PROVIDE (sdata = .);
.data :
{
*(.data)
*(.data.*)
KEEP (*(SORT(.rtemsrwset.*)))
*(.gnu.linkonce.d.*)
CONSTRUCTORS
} >RAM
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table : { *(.gcc_except_table*) } >RAM
PROVIDE (__EXCEPT_END__ = .);
.data1 : { *(.data1) } >RAM
.got1 : { *(.got1) } >RAM
.dynamic : { *(.dynamic) } >RAM
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
get relocated with -mrelocatable. Also put in the .fixup pointers.
The current compiler no longer needs this, but keep it around for 2.7.2 */
PROVIDE (_GOT2_START_ = .);
.got2 : { *(.got2) } >RAM
PROVIDE (__GOT2_END__ = .);
PROVIDE (__CTOR_LIST__ = .);
.ctors : { *(.ctors) } >RAM
PROVIDE (__CTOR_END__ = .);
PROVIDE (__DTOR_LIST__ = .);
.dtors : { *(.dtors) } >RAM
PROVIDE (__DTOR_END__ = .);
PROVIDE (_FIXUP_START_ = .);
.fixup : { *(.fixup) } >RAM
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (_GOT2_END_ = .);
.got : {
PROVIDE (_GOT_START_ = .);
s.got = .;
*(.got)
} >RAM
.got.plt : { *(.got.plt) } >RAM
PROVIDE (_GOT_END_ = .);
PROVIDE (__GOT_END__ = .);
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
PROVIDE (__SDATA_START__ = .);
.sdata : {
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} >RAM
PROVIDE (_edata = .);
PROVIDE (RAM_END = ADDR(.text) + 10M);
. = ALIGN(8) + 0x1000;
.sbss :
{
PROVIDE (__sbss_start = .);
*(.sbss*)
*(.scommon)
*(.gnu.linkonce.sb.*)
PROVIDE (__sbss_end = .);
} >RAM
.bss :
{
PROVIDE (__bss_start = .);
*(.dynbss)
*(.bss .bss* .gnu.linkonce.b*)
*(COMMON)
} >RAM
. = ALIGN(16) + 0x8000;
PROVIDE (__stack = .);
__rtems_end = . ;
. = ALIGN(8) + 0x8000;
PROVIDE(_end = .);
PROVIDE(end = .);
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) } >RAM
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}

48
c/src/lib/libbsp/powerpc/score603e/startup/vmeintr.c
View File

@@ -1,48 +0,0 @@
/*
* VMEbus support routines for the Generation I board.
*/
/*
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/vmeintr.h>
/*
* VME_interrupt_Disable
*/
void VME_interrupt_Disable(
VME_interrupt_Mask mask /* IN */
)
{
volatile uint8_t *VME_interrupt_enable;
uint8_t value;
VME_interrupt_enable = 0;
value = *VME_interrupt_enable;
value &= ~mask; /* turn off interrupts for all levels in mask */
*VME_interrupt_enable = value;
}
/*
* VME_interrupt_Enable
*/
void VME_interrupt_Enable(
VME_interrupt_Mask mask /* IN */
)
{
volatile uint8_t *VME_interrupt_enable;
uint8_t value;
VME_interrupt_enable = 0;
value = *VME_interrupt_enable;
value |= mask; /* turn on interrupts for all levels in mask */
*VME_interrupt_enable = value;
}

77
c/src/lib/libbsp/powerpc/score603e/timer/timer.c
View File

@@ -1,77 +0,0 @@
/* timer.c
*
* This file implements a benchmark timer using the General Purpose Timer.
*
* Notes:
*
* BSP_TIMER_AVG_OVERHEAD and BSP_TIMER_LEAST_VALID are required to be
* provided in bsp.h
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <assert.h>
#include <bsp.h>
#include <rtems/btimer.h>
uint64_t Timer_driver_Start_time;
bool benchmark_timer_find_average_overhead;
/*
* benchmark_timer_initialize
*/
void benchmark_timer_initialize()
{
/*
* Timer runs long and accurate enough not to require an interrupt.
*/
Timer_driver_Start_time = PPC_Get_timebase_register();
}
/*
* benchmark_timer_read
*/
benchmark_timer_t benchmark_timer_read()
{
uint64_t clicks;
uint64_t total64;
uint32_t total;
/* approximately CLOCK_SPEED clicks per microsecond */
clicks = PPC_Get_timebase_register();
assert( clicks > Timer_driver_Start_time );
total64 = clicks - Timer_driver_Start_time;
assert( total64 <= 0xffffffff ); /* fits into a uint32_t */
total = (uint32_t) total64;
if ( benchmark_timer_find_average_overhead == true )
return total; /* in "clicks" of the decrementer units */
if ( total < BSP_TIMER_LEAST_VALID )
return 0; /* below timer resolution */
return BSP_Convert_decrementer(total - BSP_TIMER_AVG_OVERHEAD);
}
void benchmark_timer_disable_subtracting_average_overhead(
bool find_flag
)
{
benchmark_timer_find_average_overhead = find_flag;
}

172
c/src/lib/libbsp/powerpc/score603e/tod/tod.c
View File

@@ -1,172 +0,0 @@
/*
* Real Time Clock (Harris ICM7170) for RTEMS
*
* This part is found on the second generation of this board.
*
* COPYRIGHT (c) 1989-2009.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <tod.h>
#include <bsp.h>
/*
* These values are programed into a register and must not be changed.
*/
#define ICM1770_CRYSTAL_FREQ_32K 0x00
#define ICM1770_CRYSTAL_FREQ_1M 0x01
#define ICM1770_CRYSTAL_FREQ_2M 0x02
#define ICM1770_CRYSTAL_FREQ_4M 0x03
void ICM7170_GetTOD(
volatile unsigned char *imc1770_regs,
uint8_t icm1770_freq,
rtems_time_of_day *rtc_tod
);
void ICM7170_SetTOD(
volatile unsigned char *imc1770_regs,
uint8_t icm1770_freq,
rtems_time_of_day *rtc_tod
);
/*
* This code is dependent on the Vista 603e's use of the ICM7170 RTC/NVRAM
* and should remain in this file.
*/
void setRealTimeToRTEMS()
{
rtems_time_of_day rtc_tod;
ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
rtems_clock_set( &rtc_tod );
}
void setRealTimeFromRTEMS()
{
rtems_time_of_day rtems_tod;
rtems_clock_get_tod( &rtems_tod );
ICM7170_SetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtems_tod );
}
int checkRealTime()
{
rtems_time_of_day rtems_tod;
rtems_time_of_day rtc_tod;
ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
rtems_clock_get_tod( &rtems_tod );
if( rtems_tod.year == rtc_tod.year &&
rtems_tod.month == rtc_tod.month &&
rtems_tod.day == rtc_tod.day ) {
return ((rtems_tod.hour - rtc_tod.hour) * 3600) +
((rtems_tod.minute - rtc_tod.minute) * 60) +
(rtems_tod.second - rtc_tod.second);
}
return 9999;
}
/*
* These routines are ICM7170 should be in
* a separate support library.
* XXX Make static
*/
static int ICM7170_GetField(
volatile unsigned char *imc1770_regs,
int reg
)
{
unsigned char x;
x = imc1770_regs[reg*4];
return x;
}
static void ICM7170_SetField(
volatile unsigned char *imc1770_regs,
int reg,
unsigned char d
)
{
imc1770_regs[reg*4] = d;
}
void ICM7170_GetTOD(
volatile unsigned char *imc1770_regs,
uint8_t icm1770_freq,
rtems_time_of_day *rtc_tod
)
{
int year;
int usec;
static bool init = true;
/* Initialize the clock at once prior to reading */
if (init ) {
ICM7170_SetField( imc1770_regs, 0x11, (0x0c | icm1770_freq) );
init = false;
}
/* Latch times */
/* rtc_tod->ticks = */
usec = ICM7170_GetField( imc1770_regs, 0x00 );
year = ICM7170_GetField( imc1770_regs, 0x06 );
if ( year >= 88 )
year += 1900;
else
year += 2000;
rtc_tod->year = year;
rtc_tod->month = ICM7170_GetField( imc1770_regs, 0x04 );
rtc_tod->day = ICM7170_GetField( imc1770_regs, 0x05 );
rtc_tod->hour = ICM7170_GetField( imc1770_regs, 0x01 );
rtc_tod->minute = ICM7170_GetField( imc1770_regs, 0x02 );
rtc_tod->second = ICM7170_GetField( imc1770_regs, 0x03 );
rtc_tod->ticks = ICM7170_GetField( imc1770_regs, 0x00 );
}
void ICM7170_SetTOD(
volatile unsigned char *imc1770_regs,
uint8_t icm1770_freq,
rtems_time_of_day *rtc_tod
)
{
int year;
year = rtc_tod->year;
if ( year >= 2088 ) /* plan ahead :) */
rtems_fatal_error_occurred( 0xBAD0BAD0 );
if ( year >= 2000 )
year -= 2000;
else
year -= 1900;
ICM7170_SetField( imc1770_regs, 0x11, (0x04 |icm1770_freq ) );
ICM7170_SetField( imc1770_regs, 0x06, year );
ICM7170_SetField( imc1770_regs, 0x04, rtc_tod->month );
ICM7170_SetField( imc1770_regs, 0x05, rtc_tod->day );
ICM7170_SetField( imc1770_regs, 0x01, rtc_tod->hour );
ICM7170_SetField( imc1770_regs, 0x02, rtc_tod->minute );
ICM7170_SetField( imc1770_regs, 0x03, rtc_tod->second );
/*
* I don't know which day of week is
*
*/
ICM7170_SetField( imc1770_regs, 0x07, 1 );
ICM7170_SetField( imc1770_regs, 0x11, (0x0c | icm1770_freq) );
}

97
c/src/lib/libbsp/powerpc/score603e/vme/VMEConfig.h
View File

@@ -1,97 +0,0 @@
#ifndef RTEMS_BSP_VME_CONFIG_H
#define RTEMS_BSP_VME_CONFIG_H
/* BSP specific address space configuration parameters */
/*
* Authorship
* ----------
* This software was created by
* Till Straumann <strauman@slac.stanford.edu>, 2002,
* Stanford Linear Accelerator Center, Stanford University.
*
* Acknowledgement of sponsorship
* ------------------------------
* This software was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
* nor any of their employees, makes any warranty, express or implied, or
* assumes any legal liability or responsibility for the accuracy,
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
* SLAC software, this and all the preceding Stanford University notices
* are to remain affixed to any copy or derivative of this software made
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
/*
* The BSP maps VME address ranges into
* one BAT.
* NOTE: the BSP (startup/bspstart.c) uses
* hardcoded window lengths that match this
* layout:
*
* BSP_VME_BAT_IDX defines
* which BAT to use for mapping the VME bus.
* If this is undefined, no extra BAT will be
* configured and VME has to share the available
* PCI address space with PCI devices.
*/
#undef BSP_VME_BAT_IDX
#define _VME_A32_WIN0_ON_PCI 0x10000000
#define _VME_A24_ON_PCI 0x1f000000
#define _VME_A16_ON_PCI 0x1fff0000
/* start of the A32 window on the VME bus
* TODO: this should perhaps be a configuration option
*/
#define _VME_A32_WIN0_ON_VME 0x20000000
/* if _VME_DRAM_OFFSET is defined, the BSP
* will map our RAM onto the VME bus, starting
* at _VME_DRAM_OFFSET
*/
#undef _VME_DRAM_OFFSET
/* Tell the interrupt manager that the universe driver
* already called openpic_eoi() and that this step hence
* must be omitted.
*/
#undef _VME_CSR_ON_PCI
#undef BSP_PCI_VME_DRIVER_DOES_EOI
extern int BSP_VMEInit();
extern int BSP_VMEIrqMgrInstall();
#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \
do { \
err = vmeUniverseInstallIrqMgr(0,5,1,6); \
} while (0)
#endif