forked from Imagelibrary/rtems
bfin_eZKit533: added new doxygen
This commit is contained in:
Daniel Ramirez
committed by
Gedare Bloom
Gedare Bloom
parent
c51645f339
commit
997f22342c
@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup bfin_ezkit533
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* @brief Global BSP definitions.
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*/
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/* bsp.h
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*
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* This include file contains all board IO definitions for eZKit533.
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@@ -30,55 +36,72 @@ extern "C" {
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#include <rtems/score/bfin.h>
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#include <rtems/bfin/bf533.h>
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/*
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* PLL and clock setup values:
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/**
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* @defgroup bfin_ezkit533 eZKit533 Support
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* @ingroup bsp_bfin
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* @brief eZKit533 Board Support Package
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* @{
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*/
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/*
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* PLL configuration for ezkit533
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/**
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* @name PLL and clock setup values:
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* @brief PLL configuration for ezkit533
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*
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* XTL = 27 MHz
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* CLKIN = 13 MHz
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* VCO = 391 MHz
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* CCLK = 391 MHz
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* SCLK = 130 MHz
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*
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* @{
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*
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*/
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#define PLL_CSEL 0x0000 /* CCLK = VCO */
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#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */
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#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */
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#define PLL_DF 0x0001 /* CLKIN = XTL/2 */
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#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */
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#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */
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#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */
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#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */
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#define CCLK 391000000 /* CORE CLOCK */
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#define SCLK 130000000 /* SYSTEM CLOCK */
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#define CCLK 391000000 ///< @brief CORE CLOCK */
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#define SCLK 130000000 ///< @brief SYSTEM CLOCK */
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/*
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* UART setup values
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/** @} */
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/**
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* @name UART setup values
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* @{
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*/
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#define BAUDRATE 57600 /* Console Baudrate */
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#define WORD_5BITS 0x00 /* 5 bits word */
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#define WORD_6BITS 0x01 /* 6 bits word */
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#define WORD_7BITS 0x02 /* 7 bits word */
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#define WORD_8BITS 0x03 /* 8 bits word */
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#define EVEN_PARITY 0x18 /* Enable EVEN parity */
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#define ODD_PARITY 0x08 /* Enable ODD parity */
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#define TWO_STP_BIT 0x04 /* 2 stop bits */
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/*
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* Ezkit flash ports
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#define BAUDRATE 57600 ///< @brief Console Baudrate */
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#define WORD_5BITS 0x00 ///< @brief 5 bits word */
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#define WORD_6BITS 0x01 ///< @brief 6 bits word */
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#define WORD_7BITS 0x02 ///< @brief 7 bits word */
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#define WORD_8BITS 0x03 ///< @brief 8 bits word */
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#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */
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#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */
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#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */
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/** @} */
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/**
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* @name Ezkit flash ports
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* @{
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*/
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#define FlashA_PortB_Dir 0x20270007L
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#define FlashA_PortB_Data 0x20270005L
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/*
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* Blackfin environment memory map
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/** @} */
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/**
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* @brief Blackfin environment memory map
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*/
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#define L1_DATA_SRAM_A 0xff800000L
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#define FIFOLENGTH 0x100
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/*
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* Simple spin delay in microsecond units for device drivers.
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/**
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* @brief Simple spin delay in microsecond units for device drivers.
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* This is very dependent on the clock speed of the target.
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*/
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@@ -86,30 +109,42 @@ extern "C" {
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{ \
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}
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/* Constants */
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/**
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* @name Constants
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* @{
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*/
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#define RAM_START 0
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#define RAM_END 0x100000
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/* functions */
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/** @} */
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/*
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* Helper Function to use the EzKits LEDS.
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/**
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* @name functions
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* @{
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*/
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/**
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* @brief Helper Function to use the EzKits LEDS.
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* Can be used by the Application.
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*/
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void setLED (uint8_t value);
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/*
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* Helper Function to use the EzKits LEDS
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/**
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* @brief Helper Function to use the EzKits LEDS
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*/
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uint8_t getLED (void);
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rtems_isr_entry set_vector( /* returns old vector */
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rtems_isr_entry handler, /* isr routine */
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rtems_vector_number vector, /* vector number */
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int type /* RTEMS or RAW intr */
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rtems_isr_entry set_vector( ///< @brief returns old vector */
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rtems_isr_entry handler, ///< @brief isr routine */
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rtems_vector_number vector, ///< @brief vector number */
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int type ///< @brief RTEMS or RAW intr */
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);
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/** @} */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup ezkit533_cplb
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* @brief CPLB configurations.
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*/
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/* cplb.h
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*
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* Copyright (c) 2006 by Atos Automacao Industrial Ltda.
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@@ -10,6 +16,13 @@
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#ifndef _CPLB_H
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#define _CPLB_H
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/**
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* @defgroup ezkit533_cplb CPLB Configuration
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* @ingroup bfin_ezkit533
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* @brief CPLB Configuration
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* @{
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*/
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/* CPLB configurations */
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#define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT
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#define CPLB_DEF_CACHE_WB CPLB_L1_CHBL
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@@ -29,4 +42,6 @@
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#define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT
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#define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB
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/** @} */
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#endif /* _CPLB_H */
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@@ -1,3 +1,9 @@
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/**
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* @file
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* @ingroup ezkit533_tm27
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* @brief Interrupt mechanisms for the tm27 test.
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*/
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/*
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* tm27.h
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*
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@@ -13,6 +19,13 @@
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#ifndef __tm27_h
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#define __tm27_h
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/**
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* @defgroup ezkit533_tm27 TM27 Test Support
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* @ingroup bfin_ezkit533
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* @brief Interrupt Mechanisms for TM27
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* @{
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*/
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/*
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* Define the interrupt mechanism for Time Test 27
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*/
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@@ -30,4 +43,6 @@
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#define Lower_tm27_intr() /* empty */
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/** @} */
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#endif
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