forked from Imagelibrary/rtems
sparc: Move ISR handler install routines
Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate files. The goal is to make their use optional. Update #4458. Update #4459.
This commit is contained in:
Sebastian Huber
@@ -1621,6 +1621,7 @@ librtemscpu_a_SOURCES += score/cpu/sparc/sparc-access.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-validate.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-validate.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-volatile-clobber.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-context-volatile-clobber.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-counter-asm.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-counter-asm.S
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librtemscpu_a_SOURCES += score/cpu/sparc/sparc-isr-install.c
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librtemscpu_a_SOURCES += score/cpu/sparc/syscall.S
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librtemscpu_a_SOURCES += score/cpu/sparc/syscall.S
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librtemscpu_a_SOURCES += score/cpu/sparc/window.S
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librtemscpu_a_SOURCES += score/cpu/sparc/window.S
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@@ -1,7 +1,12 @@
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/**
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/**
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* @file
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* @file
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*
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*
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* @brief SPARC CPU Dependent Source
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* @ingroup RTEMSScoreCPUSPARC
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*
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* @brief This source file contains static assertions to ensure the consistency
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* of interfaces used in C and assembler and it contains the SPARC-specific
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* implementation of _CPU_Initialize(), _CPU_ISR_Get_level(), and
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* _CPU_Context_Initialize().
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*/
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*/
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/*
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/*
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@@ -19,11 +24,9 @@
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#include "config.h"
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#include "config.h"
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#endif
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#endif
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#include <rtems/score/isr.h>
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#include <rtems/score/percpu.h>
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#include <rtems/score/percpu.h>
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#include <rtems/score/tls.h>
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#include <rtems/score/tls.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/thread.h>
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#include <rtems/rtems/cache.h>
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#if SPARC_HAS_FPU == 1
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#if SPARC_HAS_FPU == 1
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RTEMS_STATIC_ASSERT(
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RTEMS_STATIC_ASSERT(
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@@ -144,22 +147,6 @@ RTEMS_STATIC_ASSERT(
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CPU_Interrupt_frame_alignment
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CPU_Interrupt_frame_alignment
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);
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);
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/*
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* This initializes the set of opcodes placed in each trap
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* table entry. The routine which installs a handler is responsible
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* for filling in the fields for the _handler address and the _vector
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* trap type.
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*
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* The constants following this structure are masks for the fields which
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* must be filled in when the handler is installed.
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*/
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const CPU_Trap_table_entry _CPU_Trap_slot_template = {
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0xa1480000, /* mov %psr, %l0 */
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0x29000000, /* sethi %hi(_handler), %l4 */
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0x81c52000, /* jmp %l4 + %lo(_handler) */
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0xa6102000 /* mov _vector, %l3 */
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};
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/*
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/*
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* _CPU_Initialize
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* _CPU_Initialize
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*
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*
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@@ -197,160 +184,6 @@ uint32_t _CPU_ISR_Get_level( void )
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return level;
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return level;
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}
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}
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/*
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* _CPU_ISR_install_raw_handler
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*
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* This routine installs the specified handler as a "raw" non-executive
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* supported trap handler (a.k.a. interrupt service routine).
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*
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* Input Parameters:
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* vector - trap table entry number plus synchronous
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* vs. asynchronous information
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* new_handler - address of the handler to be installed
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* old_handler - pointer to an address of the handler previously installed
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*
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* Output Parameters: NONE
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* *new_handler - address of the handler previously installed
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*
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* NOTE:
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*
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* On the SPARC, there are really only 256 vectors. However, the executive
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* has no easy, fast, reliable way to determine which traps are synchronous
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* and which are asynchronous. By default, synchronous traps return to the
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* instruction which caused the interrupt. So if you install a software
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* trap handler as an executive interrupt handler (which is desirable since
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* RTEMS takes care of window and register issues), then the executive needs
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* to know that the return address is to the trap rather than the instruction
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* following the trap.
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*
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* So vectors 0 through 255 are treated as regular asynchronous traps which
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* provide the "correct" return address. Vectors 256 through 512 are assumed
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* by the executive to be synchronous and to require that the return address
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* be fudged.
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*
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* If you use this mechanism to install a trap handler which must reexecute
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* the instruction which caused the trap, then it should be installed as
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* an asynchronous trap. This will avoid the executive changing the return
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* address.
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*/
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void _CPU_ISR_install_raw_handler(
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uint32_t vector,
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CPU_ISR_raw_handler new_handler,
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CPU_ISR_raw_handler *old_handler
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)
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{
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uint32_t real_vector;
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CPU_Trap_table_entry *tbr;
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CPU_Trap_table_entry *slot;
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uint32_t u32_tbr;
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uint32_t u32_handler;
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/*
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* Get the "real" trap number for this vector ignoring the synchronous
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* versus asynchronous indicator included with our vector numbers.
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*/
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real_vector = SPARC_REAL_TRAP_NUMBER( vector );
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/*
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* Get the current base address of the trap table and calculate a pointer
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* to the slot we are interested in.
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*/
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sparc_get_tbr( u32_tbr );
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u32_tbr &= 0xfffff000;
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tbr = (CPU_Trap_table_entry *) u32_tbr;
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slot = &tbr[ real_vector ];
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/*
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* Get the address of the old_handler from the trap table.
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*
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* NOTE: The old_handler returned will be bogus if it does not follow
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* the RTEMS model.
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*/
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#define HIGH_BITS_MASK 0xFFFFFC00
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#define HIGH_BITS_SHIFT 10
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#define LOW_BITS_MASK 0x000003FF
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if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
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u32_handler =
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(slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) |
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(slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
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*old_handler = (CPU_ISR_raw_handler) u32_handler;
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} else
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*old_handler = 0;
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/*
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* Copy the template to the slot and then fix it.
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*/
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*slot = _CPU_Trap_slot_template;
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u32_handler = (uint32_t) new_handler;
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slot->mov_vector_l3 |= vector;
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slot->sethi_of_handler_to_l4 |=
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(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
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slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
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/*
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* There is no instruction cache snooping, so we need to invalidate
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* the instruction cache to make sure that the processor sees the
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* changes to the trap table. This step is required on both single-
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* and multiprocessor systems.
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*
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* In a SMP configuration a change to the trap table might be
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* missed by other cores. If the system state is up, the other
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* cores can be notified using SMP messages that they need to
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* flush their icache. If the up state has not been reached
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* there is no need to notify other cores. They will do an
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* automatic flush of the icache just after entering the up
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* state, but before enabling interrupts.
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*/
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rtems_cache_invalidate_entire_instruction();
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}
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void _CPU_ISR_install_vector(
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uint32_t vector,
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CPU_ISR_handler new_handler,
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CPU_ISR_handler *old_handler
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)
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{
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uint32_t real_vector;
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CPU_ISR_raw_handler ignored;
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/*
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* Get the "real" trap number for this vector ignoring the synchronous
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* versus asynchronous indicator included with our vector numbers.
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*/
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real_vector = SPARC_REAL_TRAP_NUMBER( vector );
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/*
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* Return the previous ISR handler.
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*/
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*old_handler = _ISR_Vector_table[ real_vector ];
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/*
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* Install the wrapper so this ISR can be invoked properly.
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*/
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_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
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/*
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* We put the actual user ISR address in '_ISR_vector_table'. This will
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* be used by the _ISR_Handler so the user gets control.
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*/
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_ISR_Vector_table[ real_vector ] = new_handler;
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}
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void _CPU_Context_Initialize(
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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Context_Control *the_context,
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uint32_t *stack_base,
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uint32_t *stack_base,
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194
cpukit/score/cpu/sparc/sparc-isr-install.c
Normal file
194
cpukit/score/cpu/sparc/sparc-isr-install.c
Normal file
@@ -0,0 +1,194 @@
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/**
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* @file
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*
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* @ingroup RTEMSScoreCPUSPARC
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*
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* @brief This source file contains the SPARC-specific implementation of
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* _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector().
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*/
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/*
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* COPYRIGHT (c) 1989-2007.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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|
* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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|
#ifdef HAVE_CONFIG_H
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#include "config.h"
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|
#endif
|
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#include <rtems/score/isr.h>
|
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#include <rtems/rtems/cache.h>
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|
|
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|
/*
|
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|
* This initializes the set of opcodes placed in each trap
|
||||||
|
* table entry. The routine which installs a handler is responsible
|
||||||
|
* for filling in the fields for the _handler address and the _vector
|
||||||
|
* trap type.
|
||||||
|
*
|
||||||
|
* The constants following this structure are masks for the fields which
|
||||||
|
* must be filled in when the handler is installed.
|
||||||
|
*/
|
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|
const CPU_Trap_table_entry _CPU_Trap_slot_template = {
|
||||||
|
0xa1480000, /* mov %psr, %l0 */
|
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|
0x29000000, /* sethi %hi(_handler), %l4 */
|
||||||
|
0x81c52000, /* jmp %l4 + %lo(_handler) */
|
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|
0xa6102000 /* mov _vector, %l3 */
|
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|
};
|
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|
|
||||||
|
/*
|
||||||
|
* _CPU_ISR_install_raw_handler
|
||||||
|
*
|
||||||
|
* This routine installs the specified handler as a "raw" non-executive
|
||||||
|
* supported trap handler (a.k.a. interrupt service routine).
|
||||||
|
*
|
||||||
|
* Input Parameters:
|
||||||
|
* vector - trap table entry number plus synchronous
|
||||||
|
* vs. asynchronous information
|
||||||
|
* new_handler - address of the handler to be installed
|
||||||
|
* old_handler - pointer to an address of the handler previously installed
|
||||||
|
*
|
||||||
|
* Output Parameters: NONE
|
||||||
|
* *new_handler - address of the handler previously installed
|
||||||
|
*
|
||||||
|
* NOTE:
|
||||||
|
*
|
||||||
|
* On the SPARC, there are really only 256 vectors. However, the executive
|
||||||
|
* has no easy, fast, reliable way to determine which traps are synchronous
|
||||||
|
* and which are asynchronous. By default, synchronous traps return to the
|
||||||
|
* instruction which caused the interrupt. So if you install a software
|
||||||
|
* trap handler as an executive interrupt handler (which is desirable since
|
||||||
|
* RTEMS takes care of window and register issues), then the executive needs
|
||||||
|
* to know that the return address is to the trap rather than the instruction
|
||||||
|
* following the trap.
|
||||||
|
*
|
||||||
|
* So vectors 0 through 255 are treated as regular asynchronous traps which
|
||||||
|
* provide the "correct" return address. Vectors 256 through 512 are assumed
|
||||||
|
* by the executive to be synchronous and to require that the return address
|
||||||
|
* be fudged.
|
||||||
|
*
|
||||||
|
* If you use this mechanism to install a trap handler which must reexecute
|
||||||
|
* the instruction which caused the trap, then it should be installed as
|
||||||
|
* an asynchronous trap. This will avoid the executive changing the return
|
||||||
|
* address.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void _CPU_ISR_install_raw_handler(
|
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|
uint32_t vector,
|
||||||
|
CPU_ISR_raw_handler new_handler,
|
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|
CPU_ISR_raw_handler *old_handler
|
||||||
|
)
|
||||||
|
{
|
||||||
|
uint32_t real_vector;
|
||||||
|
CPU_Trap_table_entry *tbr;
|
||||||
|
CPU_Trap_table_entry *slot;
|
||||||
|
uint32_t u32_tbr;
|
||||||
|
uint32_t u32_handler;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the "real" trap number for this vector ignoring the synchronous
|
||||||
|
* versus asynchronous indicator included with our vector numbers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
real_vector = SPARC_REAL_TRAP_NUMBER( vector );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the current base address of the trap table and calculate a pointer
|
||||||
|
* to the slot we are interested in.
|
||||||
|
*/
|
||||||
|
|
||||||
|
sparc_get_tbr( u32_tbr );
|
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|
|
||||||
|
u32_tbr &= 0xfffff000;
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|
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|
tbr = (CPU_Trap_table_entry *) u32_tbr;
|
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|
|
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|
slot = &tbr[ real_vector ];
|
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|
|
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|
/*
|
||||||
|
* Get the address of the old_handler from the trap table.
|
||||||
|
*
|
||||||
|
* NOTE: The old_handler returned will be bogus if it does not follow
|
||||||
|
* the RTEMS model.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define HIGH_BITS_MASK 0xFFFFFC00
|
||||||
|
#define HIGH_BITS_SHIFT 10
|
||||||
|
#define LOW_BITS_MASK 0x000003FF
|
||||||
|
|
||||||
|
if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
|
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|
u32_handler =
|
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|
(slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) |
|
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|
(slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
|
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|
*old_handler = (CPU_ISR_raw_handler) u32_handler;
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|
} else
|
||||||
|
*old_handler = 0;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copy the template to the slot and then fix it.
|
||||||
|
*/
|
||||||
|
|
||||||
|
*slot = _CPU_Trap_slot_template;
|
||||||
|
|
||||||
|
u32_handler = (uint32_t) new_handler;
|
||||||
|
|
||||||
|
slot->mov_vector_l3 |= vector;
|
||||||
|
slot->sethi_of_handler_to_l4 |=
|
||||||
|
(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
|
||||||
|
slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* There is no instruction cache snooping, so we need to invalidate
|
||||||
|
* the instruction cache to make sure that the processor sees the
|
||||||
|
* changes to the trap table. This step is required on both single-
|
||||||
|
* and multiprocessor systems.
|
||||||
|
*
|
||||||
|
* In a SMP configuration a change to the trap table might be
|
||||||
|
* missed by other cores. If the system state is up, the other
|
||||||
|
* cores can be notified using SMP messages that they need to
|
||||||
|
* flush their icache. If the up state has not been reached
|
||||||
|
* there is no need to notify other cores. They will do an
|
||||||
|
* automatic flush of the icache just after entering the up
|
||||||
|
* state, but before enabling interrupts.
|
||||||
|
*/
|
||||||
|
rtems_cache_invalidate_entire_instruction();
|
||||||
|
}
|
||||||
|
|
||||||
|
void _CPU_ISR_install_vector(
|
||||||
|
uint32_t vector,
|
||||||
|
CPU_ISR_handler new_handler,
|
||||||
|
CPU_ISR_handler *old_handler
|
||||||
|
)
|
||||||
|
{
|
||||||
|
uint32_t real_vector;
|
||||||
|
CPU_ISR_raw_handler ignored;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Get the "real" trap number for this vector ignoring the synchronous
|
||||||
|
* versus asynchronous indicator included with our vector numbers.
|
||||||
|
*/
|
||||||
|
|
||||||
|
real_vector = SPARC_REAL_TRAP_NUMBER( vector );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the previous ISR handler.
|
||||||
|
*/
|
||||||
|
|
||||||
|
*old_handler = _ISR_Vector_table[ real_vector ];
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Install the wrapper so this ISR can be invoked properly.
|
||||||
|
*/
|
||||||
|
|
||||||
|
_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We put the actual user ISR address in '_ISR_vector_table'. This will
|
||||||
|
* be used by the _ISR_Handler so the user gets control.
|
||||||
|
*/
|
||||||
|
|
||||||
|
_ISR_Vector_table[ real_vector ] = new_handler;
|
||||||
|
}
|
||||||
@@ -37,6 +37,7 @@ source:
|
|||||||
- cpukit/score/cpu/sparc/sparc-context-validate.S
|
- cpukit/score/cpu/sparc/sparc-context-validate.S
|
||||||
- cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
|
- cpukit/score/cpu/sparc/sparc-context-volatile-clobber.S
|
||||||
- cpukit/score/cpu/sparc/sparc-counter-asm.S
|
- cpukit/score/cpu/sparc/sparc-counter-asm.S
|
||||||
|
- cpukit/score/cpu/sparc/sparc-isr-install.c
|
||||||
- cpukit/score/cpu/sparc/syscall.S
|
- cpukit/score/cpu/sparc/syscall.S
|
||||||
- cpukit/score/cpu/sparc/window.S
|
- cpukit/score/cpu/sparc/window.S
|
||||||
type: build
|
type: build
|
||||||
|
|||||||
Reference in New Issue
Block a user