forked from Imagelibrary/rtems
955c045b3c
Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate files. The goal is to make their use optional. Update #4458. Update #4459.
257 lines
7.1 KiB
C
257 lines
7.1 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSScoreCPUSPARC
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*
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* @brief This source file contains static assertions to ensure the consistency
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* of interfaces used in C and assembler and it contains the SPARC-specific
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* implementation of _CPU_Initialize(), _CPU_ISR_Get_level(), and
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* _CPU_Context_Initialize().
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*/
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/*
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* COPYRIGHT (c) 1989-2007.
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* On-Line Applications Research Corporation (OAR).
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*
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* Copyright (c) 2017 embedded brains GmbH
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/score/percpu.h>
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#include <rtems/score/tls.h>
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#include <rtems/score/thread.h>
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#if SPARC_HAS_FPU == 1
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RTEMS_STATIC_ASSERT(
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offsetof( Per_CPU_Control, cpu_per_cpu.fsr)
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== SPARC_PER_CPU_FSR_OFFSET,
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SPARC_PER_CPU_FSR_OFFSET
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);
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#if defined(SPARC_USE_LAZY_FP_SWITCH)
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RTEMS_STATIC_ASSERT(
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offsetof( Per_CPU_Control, cpu_per_cpu.fp_owner)
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== SPARC_PER_CPU_FP_OWNER_OFFSET,
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SPARC_PER_CPU_FP_OWNER_OFFSET
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);
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#endif
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#endif
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#define SPARC_ASSERT_OFFSET(field, off) \
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RTEMS_STATIC_ASSERT( \
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offsetof(Context_Control, field) == off ## _OFFSET, \
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Context_Control_offset_ ## field \
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)
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SPARC_ASSERT_OFFSET(g5, G5);
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SPARC_ASSERT_OFFSET(g7, G7);
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RTEMS_STATIC_ASSERT(
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offsetof(Context_Control, l0_and_l1) == L0_OFFSET,
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Context_Control_offset_L0
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);
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RTEMS_STATIC_ASSERT(
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offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET,
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Context_Control_offset_L1
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);
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SPARC_ASSERT_OFFSET(l2, L2);
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SPARC_ASSERT_OFFSET(l3, L3);
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SPARC_ASSERT_OFFSET(l4, L4);
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SPARC_ASSERT_OFFSET(l5, L5);
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SPARC_ASSERT_OFFSET(l6, L6);
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SPARC_ASSERT_OFFSET(l7, L7);
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SPARC_ASSERT_OFFSET(i0, I0);
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SPARC_ASSERT_OFFSET(i1, I1);
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SPARC_ASSERT_OFFSET(i2, I2);
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SPARC_ASSERT_OFFSET(i3, I3);
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SPARC_ASSERT_OFFSET(i4, I4);
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SPARC_ASSERT_OFFSET(i5, I5);
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SPARC_ASSERT_OFFSET(i6_fp, I6_FP);
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SPARC_ASSERT_OFFSET(i7, I7);
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SPARC_ASSERT_OFFSET(o6_sp, O6_SP);
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SPARC_ASSERT_OFFSET(o7, O7);
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SPARC_ASSERT_OFFSET(psr, PSR);
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SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK);
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#if defined(RTEMS_SMP)
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SPARC_ASSERT_OFFSET(is_executing, SPARC_CONTEXT_CONTROL_IS_EXECUTING);
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#endif
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#define SPARC_ASSERT_ISF_OFFSET(field, off) \
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RTEMS_STATIC_ASSERT( \
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offsetof(CPU_Interrupt_frame, field) == ISF_ ## off ## _OFFSET, \
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CPU_Interrupt_frame_offset_ ## field \
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)
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SPARC_ASSERT_ISF_OFFSET(psr, PSR);
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SPARC_ASSERT_ISF_OFFSET(pc, PC);
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SPARC_ASSERT_ISF_OFFSET(npc, NPC);
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SPARC_ASSERT_ISF_OFFSET(g1, G1);
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SPARC_ASSERT_ISF_OFFSET(g2, G2);
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SPARC_ASSERT_ISF_OFFSET(g3, G3);
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SPARC_ASSERT_ISF_OFFSET(g4, G4);
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SPARC_ASSERT_ISF_OFFSET(g5, G5);
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SPARC_ASSERT_ISF_OFFSET(g7, G7);
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SPARC_ASSERT_ISF_OFFSET(i0, I0);
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SPARC_ASSERT_ISF_OFFSET(i1, I1);
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SPARC_ASSERT_ISF_OFFSET(i2, I2);
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SPARC_ASSERT_ISF_OFFSET(i3, I3);
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SPARC_ASSERT_ISF_OFFSET(i4, I4);
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SPARC_ASSERT_ISF_OFFSET(i5, I5);
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SPARC_ASSERT_ISF_OFFSET(i6_fp, I6_FP);
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SPARC_ASSERT_ISF_OFFSET(i7, I7);
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SPARC_ASSERT_ISF_OFFSET(y, Y);
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SPARC_ASSERT_ISF_OFFSET(tpc, TPC);
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#define SPARC_ASSERT_FP_OFFSET(field, off) \
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RTEMS_STATIC_ASSERT( \
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offsetof(Context_Control_fp, field) == SPARC_FP_CONTEXT_OFFSET_ ## off, \
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Context_Control_fp_offset_ ## field \
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)
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SPARC_ASSERT_FP_OFFSET(f0_f1, F0_F1);
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SPARC_ASSERT_FP_OFFSET(f2_f3, F2_F3);
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SPARC_ASSERT_FP_OFFSET(f4_f5, F4_F5);
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SPARC_ASSERT_FP_OFFSET(f6_f7, F6_F7);
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SPARC_ASSERT_FP_OFFSET(f8_f9, F8_F9);
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SPARC_ASSERT_FP_OFFSET(f10_f11, F10_F11);
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SPARC_ASSERT_FP_OFFSET(f12_f13, F12_F13);
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SPARC_ASSERT_FP_OFFSET(f14_f15, F14_F15);
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SPARC_ASSERT_FP_OFFSET(f16_f17, F16_F17);
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SPARC_ASSERT_FP_OFFSET(f18_f19, F18_F19);
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SPARC_ASSERT_FP_OFFSET(f20_f21, F20_F21);
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SPARC_ASSERT_FP_OFFSET(f22_f23, F22_F23);
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SPARC_ASSERT_FP_OFFSET(f24_f25, F24_F25);
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SPARC_ASSERT_FP_OFFSET(f26_f27, F26_F27);
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SPARC_ASSERT_FP_OFFSET(f28_f29, F28_F29);
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SPARC_ASSERT_FP_OFFSET(f30_f31, F30_F31);
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SPARC_ASSERT_FP_OFFSET(fsr, FSR);
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RTEMS_STATIC_ASSERT(
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sizeof(SPARC_Minimum_stack_frame) == SPARC_MINIMUM_STACK_FRAME_SIZE,
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SPARC_MINIMUM_STACK_FRAME_SIZE
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);
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/* https://devel.rtems.org/ticket/2352 */
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RTEMS_STATIC_ASSERT(
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sizeof(CPU_Interrupt_frame) % CPU_ALIGNMENT == 0,
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CPU_Interrupt_frame_alignment
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);
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/*
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* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS: NONE
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*
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* Output Parameters: NONE
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*
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* NOTE: There is no need to save the pointer to the thread dispatch routine.
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* The SPARC's assembly code can reference it directly with no problems.
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*/
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void _CPU_Initialize(void)
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{
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#if defined(SPARC_USE_LAZY_FP_SWITCH)
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__asm__ volatile (
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".global SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET\n"
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".set SPARC_THREAD_CONTROL_REGISTERS_FP_CONTEXT_OFFSET, %0\n"
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".global SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET\n"
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".set SPARC_THREAD_CONTROL_FP_CONTEXT_OFFSET, %1\n"
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:
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: "i" (offsetof(Thread_Control, Registers.fp_context)),
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"i" (offsetof(Thread_Control, fp_context))
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);
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#endif
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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uint32_t level;
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sparc_get_interrupt_level( level );
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return level;
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}
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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uint32_t *stack_base,
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uint32_t size,
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uint32_t new_level,
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void *entry_point,
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bool is_fp,
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void *tls_area
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)
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{
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uint32_t stack_high; /* highest "stack aligned" address */
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uint32_t tmp_psr;
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/*
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* On CPUs with stacks which grow down (i.e. SPARC), we build the stack
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* based on the stack_high address.
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*/
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stack_high = ((uint32_t)(stack_base) + size);
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stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
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/*
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* See the README in this directory for a diagram of the stack.
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*/
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the_context->o7 = ((uint32_t) entry_point) - 8;
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the_context->o6_sp = stack_high - SPARC_MINIMUM_STACK_FRAME_SIZE;
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the_context->i6_fp = 0;
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/*
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* Build the PSR for the task. Most everything can be 0 and the
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* CWP is corrected during the context switch.
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*
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* The EF bit determines if the floating point unit is available.
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* The FPU is ONLY enabled if the context is associated with an FP task
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* and this SPARC model has an FPU.
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*/
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sparc_get_psr( tmp_psr );
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tmp_psr &= ~SPARC_PSR_PIL_MASK;
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tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
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tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */
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/* _CPU_Context_restore_heir() relies on this */
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_Assert( ( tmp_psr & SPARC_PSR_ET_MASK ) != 0 );
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#if (SPARC_HAS_FPU == 1)
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/*
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* If this bit is not set, then a task gets a fault when it accesses
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* a floating point register. This is a nice way to detect floating
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* point tasks which are not currently declared as such.
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*/
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if ( is_fp )
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tmp_psr |= SPARC_PSR_EF_MASK;
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#endif
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the_context->psr = tmp_psr;
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/*
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* Since THIS thread is being created, there is no way that THIS
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* thread can have an interrupt stack frame on its stack.
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*/
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the_context->isr_dispatch_disable = 0;
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if ( tls_area != NULL ) {
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void *tcb = _TLS_TCB_after_TLS_block_initialize( tls_area );
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the_context->g7 = (uintptr_t) tcb;
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}
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}
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