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2008-06-19 Matthew Riek <matthew.riek@ibiscomputer.com.au>

Browse Source 
* mcf52235/README, mcf52235/gdb-init, mcf52235/clock/clock.c,
	mcf52235/console/console.c, mcf52235/include/bsp.h,
	mcf52235/include/coverhd.h, mcf52235/start/start.S,
	mcf52235/startup/bspclean.c, mcf52235/startup/bspstart.c,
	mcf52235/startup/linkcmds, mcf52235/timer/timer.c: Cleaned up
	white space and code formmated to adhere to RTEMS standards. Fixed
	a bug in the nano seconds since last tick support. Fixed a bug
	with the location of the start stack (no longer within
	.bss). Removed double definition of IPSBAR and some type defs
	etc.. Added timing test overhead results.
This commit is contained in:
Chris Johns
2008-06-19 05:46:19 +00:00
parent 8f25cec8bb
commit 9374e9b082
12 changed files with 644 additions and 622 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
c/src/lib/libbsp/m68k/mcf52235/ChangeLog
View File

@@ -1,3 +1,16 @@
2008-06-19 Matthew Riek <matthew.riek@ibiscomputer.com.au>
* mcf52235/README, mcf52235/gdb-init, mcf52235/clock/clock.c,
mcf52235/console/console.c, mcf52235/include/bsp.h,
mcf52235/include/coverhd.h, mcf52235/start/start.S,
mcf52235/startup/bspclean.c, mcf52235/startup/bspstart.c,
mcf52235/startup/linkcmds, mcf52235/timer/timer.c: Cleaned up
white space and code formmated to adhere to RTEMS standards. Fixed
a bug in the nano seconds since last tick support. Fixed a bug
with the location of the start stack (no longer within
.bss). Removed double definition of IPSBAR and some type defs
etc.. Added timing test overhead results.
2008-06-10 Matthew Riek <matthew.riek@ibiscomputer.com.au>
* .cvsignore, ChangeLog, Makefile.am, README, bsp_specs,

125
c/src/lib/libbsp/m68k/mcf52235/README
View File

@@ -3,7 +3,7 @@
#
Description: Motorola MCF52235EVB
============
============================================================================
CPU: MCF52235, 60MHz
SRAM: 32K
FLASH: 256K
@@ -11,10 +11,10 @@ FLASH: 256K
This is a Motorola evaluation board that uses the MCF52235 Coldfire CPU.
This board is running at 60MHz scaled from a 25MHz oscillator.
============================================================================
NOTES:
======
Currently this BSP must be configured with most (all?) RTEMS features turned
Currently this BSP must be configured with most RTEMS features turned
off as RAM usage is too high.
Configure as follows:
@@ -22,17 +22,35 @@ configure --target=m68k-rtems4.9 --enable-rtemsbsp=mcf52235 \
--disable-networking --disable-posix --disable-itron --disable-cxx \
--disable-tests
TODO:
=====
To get the tests to compile (but not run) change the linkcmds to specify
a larger sram memory region (256K works). This of course will let you
compile all tests, but many or most of them wont run.
See testsuites/samples/minumum for an example of what type of config flags
you need for this BSP!
In you project before you include confdefs.h, define some or all of the
following:
#define CONFIGURE_DISABLE_CLASSIC_API_NOTEPADS
#define CONFIGURE_DISABLE_CLASSIC_NOTEPADS
#define CONFIGURE_INIT_TASK_STACK_SIZE x
#define CONFIGURE_MINIMUM_TASK_STACK_SIZE x
#define CONFIGURE_INTERRUPT_STACK_SIZE x
Note that the default stack size is 1K
Note that the default number of priorities is 15
============================================================================
TODO:
*) Work with TINY RTEMS to get the ram usage down.
*) Add drivers for I2C, ADC, FEC
*) Support for LWIP
*) Update the coverhd.h (calling overheads) page 21 of the BSP guide
*) Adjust initial stack so that it's space is not forever unusable after init
*) Fix up constants used by cfinit such as clockspeed, rambase, flashbase etc.
*) Recover the 1K stack space reserved in linkcmds used for board startup.
============================================================================
Interrupt map
+-----+-----------------------------------------------------------------------+
@@ -46,7 +64,7 @@ TODO:
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 5 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 4 | FEC RX | FEC TX | | | | | | PIT |
| 4 | | | | | | | | PIT |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 3 | UART 0 | UART 1 | UART 2 | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -54,3 +72,92 @@ TODO:
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
| 1 | | | | | | | | |
+-----+--------+--------+--------+--------+--------+--------+--------+--------+
============================================================================
*** TIME TEST 1 ***
rtems_semaphore_create 8
rtems_semaphore_delete 10
rtems_semaphore_obtain: available 3
rtems_semaphore_obtain: not available -- NO_WAIT 3
rtems_semaphore_release: no waiting tasks 7
*** END OF TEST 1 ***
*** TIME TEST OVERHEAD ***
rtems_shutdown_executive 0
rtems_task_create 0
rtems_task_ident 0
rtems_task_start 0
rtems_task_restart 0
rtems_task_delete 0
rtems_task_suspend 0
rtems_task_resume 0
rtems_task_set_priority 0
rtems_task_mode 0
rtems_task_get_note 0
rtems_task_set_note 0
rtems_task_wake_when 0
rtems_task_wake_after 0
rtems_interrupt_catch 0
rtems_clock_get 0
rtems_clock_set 0
rtems_clock_tick 0
<pause>
rtems_timer_create 0
rtems_timer_delete 0
rtems_timer_ident 0
rtems_timer_fire_after 0
rtems_timer_fire_when 1
rtems_timer_reset 0
rtems_timer_cancel 0
rtems_semaphore_create 0
rtems_semaphore_delete 0
rtems_semaphore_ident 0
rtems_semaphore_obtain 0
rtems_semaphore_release 0
rtems_message_queue_create 0
rtems_message_queue_ident 0
rtems_message_queue_delete 0
rtems_message_queue_send 0
rtems_message_queue_urgent 0
rtems_message_queue_broadcast 0
rtems_message_queue_receive 0
rtems_message_queue_flush 0
<pause>
rtems_event_send 0
rtems_event_receive 0
rtems_signal_catch 0
rtems_signal_send 0
rtems_partition_create 0
rtems_partition_ident 0
rtems_partition_delete 0
rtems_partition_get_buffer 0
rtems_partition_return_buffer 0
rtems_region_create 0
rtems_region_ident 0
rtems_region_delete 0
rtems_region_get_segment 0
rtems_region_return_segment 0
rtems_port_create 0
rtems_port_ident 0
rtems_port_delete 0
rtems_port_external_to_internal 0
rtems_port_internal_to_external 0
<pause>
rtems_io_initialize 0
rtems_io_open 0
rtems_io_close 0
rtems_io_read 0
rtems_io_write 0
rtems_io_control 0
rtems_fatal_error_occurred 0
rtems_rate_monotonic_create 0
rtems_rate_monotonic_ident 0
rtems_rate_monotonic_delete 0
rtems_rate_monotonic_cancel 0
rtems_rate_monotonic_period 0
rtems_multiprocessing_announce 0
*** END OF TIME OVERHEAD ***

72
c/src/lib/libbsp/m68k/mcf52235/clock/clock.c
View File

@@ -17,15 +17,19 @@ static uint32_t s_nanoScale = 0;
/*
* Provide nanosecond extension
* Interrupts are disabled when this is called
*/
static uint32_t bsp_clock_nanoseconds_since_last_tick(void)
{
uint32_t i = MCF_PIT1_PCNTR;
if(MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF)
{
i = MCF_PIT1_PCNTR + MCF_PIT1_PMR;
}
return (i - s_pcntrAtTick) * s_nanoScale;
uint32_t i;
if (MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) {
i = s_pcntrAtTick + (MCF_PIT1_PMR - MCF_PIT1_PCNTR);
}
else {
i = s_pcntrAtTick - MCF_PIT1_PCNTR;
}
return i * s_nanoScale;
}
#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick
@@ -50,9 +54,9 @@ static uint32_t bsp_clock_nanoseconds_since_last_tick(void)
/*
* Turn off the clock
*/
static void Clock_driver_support_shutdown_hardware()
static void Clock_driver_support_shutdown_hardware()
{
MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN;
MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN;
}
/*
@@ -62,35 +66,33 @@ static void Clock_driver_support_shutdown_hardware()
*/
static void Clock_driver_support_initialize_hardware()
{
int level;
uint32_t pmr;
uint32_t preScaleCode = 0;
uint32_t clk = bsp_get_CPU_clock_speed() >> 1;
uint32_t tps = 1000000 / Configuration.microseconds_per_tick;
while (preScaleCode < 15) {
pmr = (clk >> preScaleCode) / tps;
if(pmr < (1 << 15)) break;
preScaleCode++;
}
s_nanoScale = 1000000000 / (clk >> preScaleCode);
int level;
uint32_t pmr;
uint32_t preScaleCode = 0;
uint32_t clk = bsp_get_CPU_clock_speed() >> 1;
uint32_t tps = 1000000 / Configuration.microseconds_per_tick;
MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) |
MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY);
rtems_interrupt_disable( level );
MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56;
MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN;
rtems_interrupt_enable( level );
while (preScaleCode < 15) {
pmr = (clk >> preScaleCode) / tps;
if (pmr < (1 << 15))
break;
preScaleCode++;
}
s_nanoScale = 1000000000 / (clk >> preScaleCode);
MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) |
MCF_PIT_PCSR_OVW |
MCF_PIT_PCSR_PIE |
MCF_PIT_PCSR_RLD;
MCF_PIT1_PMR = pmr;
MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) |
MCF_PIT_PCSR_PIE |
MCF_PIT_PCSR_RLD |
MCF_PIT_PCSR_EN;
s_pcntrAtTick = MCF_PIT1_PCNTR;
MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) |
MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY);
rtems_interrupt_disable(level);
MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56;
MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN;
rtems_interrupt_enable(level);
MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) |
MCF_PIT_PCSR_OVW | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD;
MCF_PIT1_PMR = pmr;
MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) |
MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN;
s_pcntrAtTick = MCF_PIT1_PCNTR;
}
#include "../../../shared/clockdrv_shell.c"

935
c/src/lib/libbsp/m68k/mcf52235/console/console.c
View File

File diff suppressed because it is too large Load Diff

6
c/src/lib/libbsp/m68k/mcf52235/gdb-init
View File

@@ -24,10 +24,12 @@ define show-exception-sframe
end
# Add -v and -d flags for bdm info
# Add -B flags to utilize hardware breakpoints when they are availiable
#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0
target remote | m68k-bdm-gdbserver pipe /dev/tblcf2 -B
#monitor set remote-debug 1
monitor bdm-reset
# Set VBR to the beginning of what will be SRAM
@@ -42,5 +44,5 @@ monitor bdm-ctl-set 0x0C04 0x00000061
# Enable PST[3:0] signals
set *((char*) 0x40100074) = 0x0F
# Add the load when debugging from ram, should never happen with rtems
# Add the load when debugging from ram which won't happen with rtems!
#load

16
c/src/lib/libbsp/m68k/mcf52235/include/bsp.h
View File

@@ -19,16 +19,13 @@ extern "C" {
/***************************************************************************/
/** Hardware data structure headers **/
#include <mcf52235/mcf52235.h> /* internal MCF52235 modules */
#include <mcf5223x/mcf5223x.h>
/* Declare base address of peripherals area */
#define __IPSBAR ((vuint8 *) 0x40000000)
/***************************************************************************/
/** Network driver configuration **/
#if 0
struct rtems_bsdnet_ifconfig;
extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching );
#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach
#endif
/***************************************************************************/
/** User Definable configuration **/
@@ -58,7 +55,9 @@ extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int at
/* functions */
uint32_t bsp_get_CPU_clock_speed(void);
void bsp_cleanup(void);
m68k_isr_entry set_vector(
rtems_isr_entry handler,
rtems_vector_number vector,
@@ -69,9 +68,6 @@ m68k_isr_entry set_vector(
* Interrupt assignments
* Highest-priority listed first
*/
#define FEC_IRQ_LEVEL 4
#define FEC_IRQ_RX_PRIORITY 7
#define FEC_IRQ_TX_PRIORITY 6
#define PIT3_IRQ_LEVEL 4
#define PIT3_IRQ_PRIORITY 0

8
c/src/lib/libbsp/m68k/mcf52235/include/coverhd.h
View File

@@ -40,17 +40,17 @@
#define CALLING_OVERHEAD_TASK_MODE 0
#define CALLING_OVERHEAD_TASK_GET_NOTE 0
#define CALLING_OVERHEAD_TASK_SET_NOTE 0
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
#define CALLING_OVERHEAD_CLOCK_GET 1
#define CALLING_OVERHEAD_CLOCK_SET 1
#define CALLING_OVERHEAD_CLOCK_GET 0
#define CALLING_OVERHEAD_CLOCK_SET 0
#define CALLING_OVERHEAD_CLOCK_TICK 0
#define CALLING_OVERHEAD_TIMER_CREATE 0
#define CALLING_OVERHEAD_TIMER_IDENT 0
#define CALLING_OVERHEAD_TIMER_DELETE 0
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1
#define CALLING_OVERHEAD_TIMER_RESET 0
#define CALLING_OVERHEAD_TIMER_CANCEL 0

29
c/src/lib/libbsp/m68k/mcf52235/start/start.S
View File

@@ -31,7 +31,7 @@ SYM(_INTERRUPT_VECTOR):
.long SYM(_uhoh) /* 02 Access Error */
.long SYM(_uhoh) /* 03 Address Error */
.long SYM(_uhoh) /* 04 Illegal Instruction */
.long SYM(_uhoh) /* 05 Reserved */
.long SYM(_uhoh) /* 05 Divide by Zero */
.long SYM(_uhoh) /* 06 Reserved */
.long SYM(_uhoh) /* 07 Reserved */
.long SYM(_uhoh) /* 08 Privilege Violation */
@@ -41,7 +41,7 @@ SYM(_INTERRUPT_VECTOR):
.long SYM(_uhoh) /* 12 Debug Interrupt */
.long SYM(_uhoh) /* 13 Reserved */
.long SYM(_uhoh) /* 14 Format Error */
.long SYM(_uhoh) /* 15 Unitialized Int. */
.long SYM(_uhoh) /* 15 Reserved */
.long SYM(_uhoh) /* 16 Reserved */
.long SYM(_uhoh) /* 17 Reserved */
.long SYM(_uhoh) /* 18 Reserved */
@@ -51,13 +51,13 @@ SYM(_INTERRUPT_VECTOR):
.long SYM(_uhoh) /* 22 Reserved */
.long SYM(_uhoh) /* 23 Reserved */
.long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */
.long SYM(_uhoh) /* 25 Autovector Level 1 */
.long SYM(_uhoh) /* 26 Autovector Level 2 */
.long SYM(_uhoh) /* 27 Autovector Level 3 */
.long SYM(_uhoh) /* 28 Autovector Level 4 */
.long SYM(_uhoh) /* 29 Autovector Level 5 */
.long SYM(_uhoh) /* 30 Autovector Level 6 */
.long SYM(_uhoh) /* 31 Autovector Level 7 */
.long SYM(_uhoh) /* 25 Reserved */
.long SYM(_uhoh) /* 26 Reserved */
.long SYM(_uhoh) /* 27 Reserved */
.long SYM(_uhoh) /* 28 Reserved */
.long SYM(_uhoh) /* 29 Reserved */
.long SYM(_uhoh) /* 30 Reserved */
.long SYM(_uhoh) /* 31 Reserved */
.long SYM(_uhoh) /* 32 TRAP #0 */
.long SYM(_uhoh) /* 33 TRAP #1 */
.long SYM(_uhoh) /* 34 TRAP #2 */
@@ -314,17 +314,6 @@ _cfm_msec: .long 0x00000000
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
/*
link a6,#0
lea -20(sp), sp
movem.l d0-d2/a0-a1, (sp)
pea.l 20(sp) | push exception frame address
jsr mcf5xxx_exception_handler
movem.l 4(sp), d0-d2/a0-a1
lea 24(sp), sp
unlk a6
rte
*/
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever

14
c/src/lib/libbsp/m68k/mcf52235/startup/bspclean.c
View File

@@ -22,13 +22,11 @@
#include <bsp.h>
#include <rtems/bspIo.h>
void bsp_cleanup( void )
void bsp_cleanup(void)
{
printk("\nRTEMS exited!\n");
for ( ;; )
{
asm volatile ( " nop " );
asm volatile ( " nop " );
}
printk("\nRTEMS exited!\n");
for (;;) {
asm volatile (" nop ");
asm volatile (" nop ");
}
}

4
c/src/lib/libbsp/m68k/mcf52235/startup/bspstart.c
View File

@@ -54,11 +54,11 @@ void _CPU_cache_invalidate_1_data_line(const void *addr) {}
*
* This routine does the bulk of the system initialisation.
*/
void bsp_start( void )
void bsp_start(void)
{
}
uint32_t bsp_get_CPU_clock_speed(void)
{
return 60000000;
return 60000000;
}

11
c/src/lib/libbsp/m68k/mcf52235/startup/linkcmds
View File

@@ -21,7 +21,6 @@ _HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
_StackSize = DEFINED(_StackSize) ? _StackSize : 0x400;
_FlashBase = DEFINED(_FlashBase) ? _FlashBase : 0x00000000;
__IPSBAR = DEFINED(__IPSBAR) ? __IPSBAR : 0x40000000;
_VBR = 0x20000000;
ENTRY(start)
@@ -143,21 +142,23 @@ SECTIONS
.bss :
{
_clear_start = .;
PROVIDE (_clear_start = .);
*(.bss*)
*(COMMON)
. = ALIGN (16);
PROVIDE (_end = .);
PROVIDE (_clear_end = .);
} >sram
.stack :
{
/*
* Starting Stack
*/
. += _StackSize;
. = ALIGN (16);
PROVIDE(_StackInit = .);
_clear_end = .;
_WorkspaceBase = .;
PROVIDE(_WorkspaceBase = .);
} >sram
/* Stabs debugging sections. */

33
c/src/lib/libbsp/m68k/mcf52235/timer/timer.c
View File

@@ -16,43 +16,32 @@
#include <rtems.h>
#include <bsp.h>
typedef volatile unsigned char vuint8;
typedef volatile unsigned short vuint16;
typedef volatile unsigned long vuint32;
/* Declare base address of peripherals area */
#define __IPSBAR ((vuint8 *) 0x40000000)
void
Timer_initialize(void)
void Timer_initialize(void)
{
uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000;
MCF_DTIM3_DTMR = 0;
MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) |
MCF_DTIM_DTMR_CLK_DIV1 |
MCF_DTIM_DTMR_RST;
uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000;
MCF_DTIM3_DTMR = 0;
MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) |
MCF_DTIM_DTMR_CLK_DIV1 | MCF_DTIM_DTMR_RST;
}
/*
* Return timer value in microsecond units
*/
int
Read_timer(void)
int Read_timer(void)
{
return MCF_DTIM3_DTCN;
return MCF_DTIM3_DTCN;
}
/*
* Empty function call used in loops to measure basic cost of looping
* in Timing Test Suite.
*/
rtems_status_code
Empty_function(void)
rtems_status_code Empty_function(void)
{
return RTEMS_SUCCESSFUL;
return RTEMS_SUCCESSFUL;
}
void
Set_find_average_overhead(rtems_boolean find_flag)
void Set_find_average_overhead(rtems_boolean find_flag)
{
}