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bsp/xilinx-zynq: Simplify configure.ac

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This commit is contained in:
Sebastian Huber
2019-10-23 14:11:17 +02:00
parent 1e1afa3779
commit 8c66f1aa06
1 changed files with 10 additions and 24 deletions
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34
c/src/lib/libbsp/arm/xilinx-zynq/configure.ac
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@@ -73,49 +73,35 @@ RTEMS_BSPOPTS_HELP([BSP_ZYNQ_RAM_LENGTH],[override a BSP's default RAM length])
RTEMS_BSPOPTS_SET([BSP_ZYNQ_NOCACHE_LENGTH],[*],[1M])
RTEMS_BSPOPTS_HELP([BSP_ZYNQ_NOCACHE_LENGTH],[length of nocache RAM region])
ZYNQ_RAM_MMU_LENGTH="16k"
ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
ZYNQ_RAM_INT_1_LENGTH="64k - 512"
AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_a9_qemu],
[ZYNQ_RAM_ORIGIN="0x00000000"
ZYNQ_RAM_MMU="0x0fffc000"
ZYNQ_RAM_MMU_LENGTH="16k"
ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN}"
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"
ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 16k"])
AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc702],
[ZYNQ_RAM_ORIGIN="0x00100000"
ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
ZYNQ_RAM_MMU_LENGTH="16k"
ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"])
AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zc706],
[ZYNQ_RAM_ORIGIN="0x00400000"
ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
ZYNQ_RAM_MMU_LENGTH="16k"
ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"
ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 4M - 16k"])
AS_IF([test "x${RTEMS_BSP}" == xxilinx_zynq_zedboard],
[ZYNQ_RAM_ORIGIN="0x00100000"
ZYNQ_RAM_MMU="${ZYNQ_RAM_ORIGIN}"
ZYNQ_RAM_MMU_LENGTH="16k"
ZYNQ_RAM_ORIGIN_AVAILABLE="${ZYNQ_RAM_ORIGIN} + 0x00004000"
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"
ZYNQ_RAM_INT_0_ORIGIN="0x00000000"
ZYNQ_RAM_INT_0_LENGTH="64k + 64k + 64k"
ZYNQ_RAM_INT_1_ORIGIN="0xFFFF0000"
ZYNQ_RAM_INT_1_LENGTH="64k - 512"])
ZYNQ_RAM_LENGTH_AVAILABLE="${BSP_ZYNQ_RAM_LENGTH} - 1M - 16k"])
AC_DEFUN([ZYNQ_LINKCMD],[
AC_ARG_VAR([$1],[$2; default $3])dnl