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Patch from Eric Valette <valette@crf.canon.fr>:

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- Use the "hlt" instruction for the Idle thread,
        - Optimise interrupt PATH leadding to thread wakeup,
        - Preparation for Intel exception management that should
        come before the end of the week...
This commit is contained in:
Joel Sherrill
1998-08-19 20:09:59 +00:00
parent 7549e147ae
commit 8b2ee37c38
5 changed files with 94 additions and 59 deletions
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9
c/src/exec/score/cpu/i386/cpu.c
View File

@@ -75,4 +75,11 @@ unsigned32 _CPU_ISR_Get_level( void )
return level;
}
void _CPU_Thread_Idle_body ()
{
while(1){
asm volatile ("hlt");
}
}

33
c/src/exec/score/cpu/i386/cpu.h
View File

@@ -64,7 +64,7 @@ extern "C" {
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_USE_DEFERRED_FP_SWITCH TRUE
#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
#define CPU_PROVIDES_IDLE_THREAD_BODY YES
#define CPU_STACK_GROWS_UP FALSE
#define CPU_STRUCTURE_ALIGNMENT
@@ -101,14 +101,39 @@ typedef struct {
/* 28 bytes for environment */
} Context_Control_fp;
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt.
* on the current stack by RTEMS upon receipt of execptions.
*
* idtIndex is either the interrupt number or the trap/exception number.
* faultCode is the code pushed by the processor on some exceptions.
*/
typedef struct {
unsigned32 TBD; /* XXX Fix for this CPU */
} CPU_Interrupt_frame;
unsigned32 edi,
esi,
ebp,
esp0,
ebx,
edx,
ecx,
eax,
idtIndex,
faultCode,
eip,
cs,
eflags;
}CPU_Exception_frame;
/*
* The following structure defines the set of information saved
* on the current stack by RTEMS upon receipt of each interrupt
* that will lead to re-enter the kernel to signal the thread.
*/
typedef CPU_Exception_frame CPU_Interrupt_frame;
/*
* The following table contains the information required to configure

12
c/src/lib/libbsp/i386/shared/irq/irq.c
View File

@@ -356,3 +356,15 @@ int pc386_rtems_irq_mngt_get(rtems_irq_global_settings** config)
*config = internal_config;
return 0;
}
void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx)
{
/*
* If I understand the _Thread_Dispatch routine correctly
* I do not see how this routine can be called given the
* actual code. I plan to use this so far unused feature
* to implement remote debugger ptrace("attach", ...)
* command.
*/
printk(" _ThreadProcessSignalsFromIrq called! mail valette@crf.canon.fr\n");
}

90
c/src/lib/libbsp/i386/shared/irq/irq_asm.s
View File

@@ -14,48 +14,12 @@
#include "asm.h"
#include <irq_asm.h>
.set SAVED_REGS , 32 # space consumed by saved regs
.set EIP_OFFSET , SAVED_REGS # offset of tasks eip
.set CS_OFFSET , EIP_OFFSET+4 # offset of tasks code segment
.set EFLAGS_OFFSET , CS_OFFSET+4 # offset of tasks eflags
/*PAGE
* void _New_ISR_Displatch()
*
* Entry point from the outermost interrupt service routine exit.
* The current stack is the supervisor mode stack.
*/
PUBLIC (_New_ISR_Displatch)
SYM (_New_ISR_Displatch):
call SYM (_Thread_Dispatch) # invoke Dispatcher
/*
* BEGINNING OF DE-ESTABLISH SEGMENTS
*
* NOTE: Make sure there is code here if code is added to
* load the segment registers.
*
*/
/***** DE-ESTABLISH SEGMENTS CODE GOES HERE ****/
/*
* END OF DE-ESTABLISH SEGMENTS
*/
popa # restore general registers
iret # return to interrupted thread
SYM (_New_ISR_Handler):
SYM (_ISR_Handler):
/*
* Before this was point is reached the vectors unique
* entry point did the following:
*
* 1. saved sctach registers registers eax edx ecx"
* 1. saved scratch registers registers eax edx ecx"
* 2. put the vector number in ecx.
*
* BEGINNING OF ESTABLISH SEGMENTS
@@ -176,29 +140,48 @@ nested:
cmpl $0, SYM (_Context_Switch_necessary)
# Is task switch necessary?
jne bframe # Yes, then build stack
jne .schedule # Yes, then call the scheduler
cmpl $0, SYM (_ISR_Signals_to_thread_executing)
# signals sent to Run_thread
# while in interrupt handler?
je .exit # No, exit
bframe:
.bframe:
movl $0, SYM (_ISR_Signals_to_thread_executing)
/*
* complete code as if a pusha had been executed on entry
* This code is the less critical path. In order to have a single
* Thread Context, we take the same frame than the one pushed on
* exceptions. This makes sense because Signal is a software
* exception.
*/
pushl ebx
pushl esp
pushl ebp
pushl esi
pushl edi
# push the isf for Isr_dispatch
pushl EFLAGS_OFFSET(esp) # push tasks eflags
push cs # cs of Isr_dispatch
pushl $ SYM (_New_ISR_Displatch)# entry point
iret
popl edx
popl ecx
popl eax
pushl $0 # fake fault code
pushl $0 # fake exception number
pusha
pushl esp
call _ThreadProcessSignalsFromIrq
addl $4, esp
popa
addl $8, esp
iret
.schedule:
/*
* the scratch registers have already been saved and we are already
* back on the thread system stack. So we can call _Thread_Displatch
* directly
*/
call _Thread_Dispatch
/*
* fall through exit to restore complete contex (scratch registers
* eip, CS, Flags).
*/
.exit:
/*
* BEGINNING OF DE-ESTABLISH SEGMENTS
@@ -217,7 +200,8 @@ bframe:
popl ecx
popl eax
iret
#define DISTINCT_INTERRUPT_ENTRY(_vector) \
.p2align 4 ; \
PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
@@ -226,7 +210,7 @@ SYM (rtems_irq_prologue_ ## _vector ): \
pushl ecx ; \
pushl edx ; \
movl $ _vector, ecx ; \
jmp SYM (_New_ISR_Handler) ;
jmp SYM (_ISR_Handler) ;
DISTINCT_INTERRUPT_ENTRY(0)
DISTINCT_INTERRUPT_ENTRY(1)

9
cpukit/score/cpu/i386/cpu.c
View File

@@ -75,4 +75,11 @@ unsigned32 _CPU_ISR_Get_level( void )
return level;
}
void _CPU_Thread_Idle_body ()
{
while(1){
asm volatile ("hlt");
}
}