forked from Imagelibrary/rtems
Remove.
This commit is contained in:
Ralf Corsepius
@@ -1,695 +0,0 @@
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/*
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Based upon IDT provided code with the following release:
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This source code has been made available to you by IDT on an AS-IS
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basis. Anyone receiving this source is licensed under IDT copyrights
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||||
to use it in any way he or she deems fit, including copying it,
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modifying it, compiling it, and redistributing it either with or
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||||
without modifications. No license under IDT patents or patent
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applications is to be implied by the copyright license.
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||||
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Any user of this software should understand that IDT cannot provide
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||||
technical support for this software and will not be responsible for
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||||
any consequences resulting from the use of this software.
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Any person who transfers this source code or any derivative work must
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include the IDT copyright notice, this paragraph, and the preceeding
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two paragraphs in the transferred software.
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COPYRIGHT IDT CORPORATION 1996
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LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
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$Id$
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*/
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/*
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** idtcpu.h -- cpu related defines
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*/
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#ifndef _IDTCPU_H__
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#define _IDTCPU_H__
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/*
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* 950313: Ketan added Register definition for XContext reg.
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* added define for WAIT instruction.
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* 950421: Ketan added Register definition for Config reg (R3081)
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*/
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/*
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** memory configuration and mapping
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*/
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#define K0BASE 0x80000000
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#define K0SIZE 0x20000000
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#define K1BASE 0xa0000000
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#define K1SIZE 0x20000000
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#define K2BASE 0xc0000000
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#define K2SIZE 0x20000000
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#if __mips == 3
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#define KSBASE 0xe0000000
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#define KSSIZE 0x20000000
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#endif
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#define KUBASE 0
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#define KUSIZE 0x80000000
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/*
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** Exception Vectors
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*/
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#if __mips == 1
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#define UT_VEC K0BASE /* utlbmiss vector */
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#define DB_VEC (K0BASE+0x40) /* debug vector */
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#define E_VEC (K0BASE+0x80) /* exception vector */
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#elif __mips == 32
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#define T_VEC (K0BASE+0x000) /* tlbmiss vector */
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#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
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#define C_VEC (K0BASE+0x100) /* cache error vector */
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#define E_VEC (K0BASE+0x180) /* exception vector */
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#elif __mips == 3
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#define T_VEC (K0BASE+0x000) /* tlbmiss vector */
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#define X_VEC (K0BASE+0x080) /* xtlbmiss vector */
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#define C_VEC (K0BASE+0x100) /* cache error vector */
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#define E_VEC (K0BASE+0x180) /* exception vector */
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#else
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#error "EXCEPTION VECTORS: unknown ISA level"
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#endif
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#define R_VEC (K1BASE+0x1fc00000) /* reset vector */
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/*
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** Address conversion macros
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*/
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#ifdef CLANGUAGE
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#define CAST(as) (as)
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#else
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#define CAST(as)
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#endif
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#define K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */
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#define K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */
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#define K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */
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#define K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */
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#define PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */
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#define PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */
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/*
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** Cache size constants
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*/
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#define MINCACHE 0x200 /* 512 For 3041. */
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#define MAXCACHE 0x40000 /* 256*1024 256k */
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#if __mips == 32
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/* R4000 configuration register definitions */
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#define CFG_CM 0x80000000 /* Master-Checker mode */
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#define CFG_ECMASK 0x70000000 /* System Clock Ratio */
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#define CFG_ECBY2 0x00000000 /* divide by 2 */
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#define CFG_ECBY3 0x10000000 /* divide by 3 */
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#define CFG_ECBY4 0x20000000 /* divide by 4 */
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#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */
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#define CFG_EPD 0x00000000 /* D */
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#define CFG_EPDDX 0x01000000 /* DDX */
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#define CFG_EPDDXX 0x02000000 /* DDXX */
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#define CFG_EPDXDX 0x03000000 /* DXDX */
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#define CFG_EPDDXXX 0x04000000 /* DDXXX */
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#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */
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#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */
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#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */
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#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */
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#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */
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#define CFG_SBSHIFT 22
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#define CFG_SB4 0x00000000 /* 4 words */
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#define CFG_SB8 0x00400000 /* 8 words */
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#define CFG_SB16 0x00800000 /* 16 words */
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#define CFG_SB32 0x00c00000 /* 32 words */
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#define CFG_SS 0x00200000 /* Split secondary cache */
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#define CFG_SW 0x00100000 /* Secondary cache port width */
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#define CFG_EWMASK 0x000c0000 /* System port width */
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#define CFG_EWSHIFT 18
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#define CFG_EW64 0x00000000 /* 64 bit */
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#define CFG_EW32 0x00010000 /* 32 bit */
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#define CFG_SC 0x00020000 /* Secondary cache absent */
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#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */
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#define CFG_BE 0x00008000 /* Big Endian */
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#define CFG_EM 0x00004000 /* ECC mode enable */
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#define CFG_EB 0x00002000 /* Block ordering */
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#define CFG_ICMASK 0x00000e00 /* Instruction cache size */
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#define CFG_ICSHIFT 9
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#define CFG_DCMASK 0x000001c0 /* Data cache size */
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#define CFG_DCSHIFT 6
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#define CFG_IB 0x00000020 /* Instruction cache block size */
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#define CFG_DB 0x00000010 /* Data cache block size */
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#define CFG_CU 0x00000008 /* Update on Store Conditional */
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#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
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/*
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* R4000 primary cache mode
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*/
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#define CFG_C_UNCACHED 2
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#define CFG_C_NONCOHERENT 3
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#define CFG_C_COHERENTXCL 4
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#define CFG_C_COHERENTXCLW 5
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#define CFG_C_COHERENTUPD 6
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/*
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* R4000 cache operations (should be in assembler...?)
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*/
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#define Index_Invalidate_I 0x0 /* 0 0 */
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#define Index_Writeback_Inv_D 0x1 /* 0 1 */
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#define Index_Invalidate_SI 0x2 /* 0 2 */
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#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
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#define Index_Load_Tag_I 0x4 /* 1 0 */
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#define Index_Load_Tag_D 0x5 /* 1 1 */
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#define Index_Load_Tag_SI 0x6 /* 1 2 */
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#define Index_Load_Tag_SD 0x7 /* 1 3 */
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#define Index_Store_Tag_I 0x8 /* 2 0 */
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#define Index_Store_Tag_D 0x9 /* 2 1 */
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#define Index_Store_Tag_SI 0xA /* 2 2 */
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#define Index_Store_Tag_SD 0xB /* 2 3 */
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#define Create_Dirty_Exc_D 0xD /* 3 1 */
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#define Create_Dirty_Exc_SD 0xF /* 3 3 */
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#define Hit_Invalidate_I 0x10 /* 4 0 */
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#define Hit_Invalidate_D 0x11 /* 4 1 */
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#define Hit_Invalidate_SI 0x12 /* 4 2 */
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#define Hit_Invalidate_SD 0x13 /* 4 3 */
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#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
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#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
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#define Fill_I 0x14 /* 5 0 */
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#define Hit_Writeback_D 0x19 /* 6 1 */
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#define Hit_Writeback_SD 0x1B /* 6 3 */
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#define Hit_Writeback_I 0x18 /* 6 0 */
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#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
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#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
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#ifndef WAIT
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#define WAIT .word 0x42000020
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#endif /* WAIT */
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/* Disabled by joel -- horrible overload of common word.
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#ifndef wait
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#define wait .word 0x42000020
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#endif wait
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*/
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#endif
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#if __mips == 3
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/* R4000 configuration register definitions */
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#define CFG_CM 0x80000000 /* Master-Checker mode */
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#define CFG_ECMASK 0x70000000 /* System Clock Ratio */
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#define CFG_ECBY2 0x00000000 /* divide by 2 */
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#define CFG_ECBY3 0x10000000 /* divide by 3 */
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#define CFG_ECBY4 0x20000000 /* divide by 4 */
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#define CFG_EPMASK 0x0f000000 /* Transmit data pattern */
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#define CFG_EPD 0x00000000 /* D */
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#define CFG_EPDDX 0x01000000 /* DDX */
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#define CFG_EPDDXX 0x02000000 /* DDXX */
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#define CFG_EPDXDX 0x03000000 /* DXDX */
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#define CFG_EPDDXXX 0x04000000 /* DDXXX */
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#define CFG_EPDDXXXX 0x05000000 /* DDXXXX */
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#define CFG_EPDXXDXX 0x06000000 /* DXXDXX */
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#define CFG_EPDDXXXXX 0x07000000 /* DDXXXXX */
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#define CFG_EPDXXXDXXX 0x08000000 /* DXXXDXXX */
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#define CFG_SBMASK 0x00c00000 /* Secondary cache block size */
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#define CFG_SBSHIFT 22
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#define CFG_SB4 0x00000000 /* 4 words */
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#define CFG_SB8 0x00400000 /* 8 words */
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#define CFG_SB16 0x00800000 /* 16 words */
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#define CFG_SB32 0x00c00000 /* 32 words */
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#define CFG_SS 0x00200000 /* Split secondary cache */
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#define CFG_SW 0x00100000 /* Secondary cache port width */
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#define CFG_EWMASK 0x000c0000 /* System port width */
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#define CFG_EWSHIFT 18
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#define CFG_EW64 0x00000000 /* 64 bit */
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#define CFG_EW32 0x00010000 /* 32 bit */
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#define CFG_SC 0x00020000 /* Secondary cache absent */
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#define CFG_SM 0x00010000 /* Dirty Shared mode disabled */
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#define CFG_BE 0x00008000 /* Big Endian */
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#define CFG_EM 0x00004000 /* ECC mode enable */
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#define CFG_EB 0x00002000 /* Block ordering */
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#define CFG_ICMASK 0x00000e00 /* Instruction cache size */
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#define CFG_ICSHIFT 9
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#define CFG_DCMASK 0x000001c0 /* Data cache size */
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#define CFG_DCSHIFT 6
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#define CFG_IB 0x00000020 /* Instruction cache block size */
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#define CFG_DB 0x00000010 /* Data cache block size */
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#define CFG_CU 0x00000008 /* Update on Store Conditional */
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#define CFG_K0MASK 0x00000007 /* KSEG0 coherency algorithm */
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/*
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* R4000 primary cache mode
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*/
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#define CFG_C_UNCACHED 2
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#define CFG_C_NONCOHERENT 3
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#define CFG_C_COHERENTXCL 4
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#define CFG_C_COHERENTXCLW 5
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#define CFG_C_COHERENTUPD 6
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/*
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* R4000 cache operations (should be in assembler...?)
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*/
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#define Index_Invalidate_I 0x0 /* 0 0 */
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#define Index_Writeback_Inv_D 0x1 /* 0 1 */
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#define Index_Invalidate_SI 0x2 /* 0 2 */
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#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
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#define Index_Load_Tag_I 0x4 /* 1 0 */
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#define Index_Load_Tag_D 0x5 /* 1 1 */
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#define Index_Load_Tag_SI 0x6 /* 1 2 */
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#define Index_Load_Tag_SD 0x7 /* 1 3 */
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#define Index_Store_Tag_I 0x8 /* 2 0 */
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#define Index_Store_Tag_D 0x9 /* 2 1 */
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#define Index_Store_Tag_SI 0xA /* 2 2 */
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#define Index_Store_Tag_SD 0xB /* 2 3 */
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#define Create_Dirty_Exc_D 0xD /* 3 1 */
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#define Create_Dirty_Exc_SD 0xF /* 3 3 */
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#define Hit_Invalidate_I 0x10 /* 4 0 */
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#define Hit_Invalidate_D 0x11 /* 4 1 */
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#define Hit_Invalidate_SI 0x12 /* 4 2 */
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#define Hit_Invalidate_SD 0x13 /* 4 3 */
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#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
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#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
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#define Fill_I 0x14 /* 5 0 */
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#define Hit_Writeback_D 0x19 /* 6 1 */
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#define Hit_Writeback_SD 0x1B /* 6 3 */
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#define Hit_Writeback_I 0x18 /* 6 0 */
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#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
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#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
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#ifndef WAIT
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#define WAIT .word 0x42000020
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#endif /* WAIT */
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/* Disabled by joel -- horrible overload of common word.
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||||
#ifndef wait
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#define wait .word 0x42000020
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#endif wait
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*/
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#endif
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/*
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||||
** TLB resource defines
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||||
*/
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||||
#if __mips == 1
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||||
#define N_TLB_ENTRIES 64
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#define TLB_PGSIZE 0x1000
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#define RANDBASE 8
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||||
#define TLBLO_PFNMASK 0xfffff000
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#define TLBLO_PFNSHIFT 12
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||||
#define TLBLO_N 0x800 /* non-cacheable */
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||||
#define TLBLO_D 0x400 /* writeable */
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||||
#define TLBLO_V 0x200 /* valid bit */
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||||
#define TLBLO_G 0x100 /* global access bit */
|
||||
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||||
#define TLBHI_VPNMASK 0xfffff000
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||||
#define TLBHI_VPNSHIFT 12
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||||
#define TLBHI_PIDMASK 0xfc0
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||||
#define TLBHI_PIDSHIFT 6
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||||
#define TLBHI_NPID 64
|
||||
|
||||
#define TLBINX_PROBE 0x80000000
|
||||
#define TLBINX_INXMASK 0x00003f00
|
||||
#define TLBINX_INXSHIFT 8
|
||||
|
||||
#define TLBRAND_RANDMASK 0x00003f00
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||||
#define TLBRAND_RANDSHIFT 8
|
||||
|
||||
#define TLBCTXT_BASEMASK 0xffe00000
|
||||
#define TLBCTXT_BASESHIFT 21
|
||||
|
||||
#define TLBCTXT_VPNMASK 0x001ffffc
|
||||
#define TLBCTXT_VPNSHIFT 2
|
||||
#endif
|
||||
#if __mips == 3
|
||||
#define N_TLB_ENTRIES 48
|
||||
|
||||
#define TLBHI_VPN2MASK 0xffffe000
|
||||
#define TLBHI_PIDMASK 0x000000ff
|
||||
#define TLBHI_NPID 256
|
||||
|
||||
#define TLBLO_PFNMASK 0x3fffffc0
|
||||
#define TLBLO_PFNSHIFT 6
|
||||
#define TLBLO_D 0x00000004 /* writeable */
|
||||
#define TLBLO_V 0x00000002 /* valid bit */
|
||||
#define TLBLO_G 0x00000001 /* global access bit */
|
||||
#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */
|
||||
#define TLBLO_CSHIFT 3
|
||||
|
||||
#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
|
||||
#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
|
||||
|
||||
#define TLBINX_PROBE 0x80000000
|
||||
#define TLBINX_INXMASK 0x0000003f
|
||||
|
||||
#define TLBRAND_RANDMASK 0x0000003f
|
||||
|
||||
#define TLBCTXT_BASEMASK 0xff800000
|
||||
#define TLBCTXT_BASESHIFT 23
|
||||
|
||||
#define TLBCTXT_VPN2MASK 0x007ffff0
|
||||
#define TLBCTXT_VPN2SHIFT 4
|
||||
|
||||
#define TLBPGMASK_MASK 0x01ffe000
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define N_TLB_ENTRIES 16
|
||||
|
||||
#define TLBHI_VPN2MASK 0xffffe000
|
||||
#define TLBHI_PIDMASK 0x000000ff
|
||||
#define TLBHI_NPID 256
|
||||
|
||||
#define TLBLO_PFNMASK 0x3fffffc0
|
||||
#define TLBLO_PFNSHIFT 6
|
||||
#define TLBLO_D 0x00000004 /* writeable */
|
||||
#define TLBLO_V 0x00000002 /* valid bit */
|
||||
#define TLBLO_G 0x00000001 /* global access bit */
|
||||
#define TLBLO_CMASK 0x00000038 /* cache algorithm mask */
|
||||
#define TLBLO_CSHIFT 3
|
||||
|
||||
#define TLBLO_UNCACHED (CFG_C_UNCACHED<<TLBLO_CSHIFT)
|
||||
#define TLBLO_NONCOHERENT (CFG_C_NONCOHERENT<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTXCL (CFG_C_COHERENTXCL<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTXCLW (CFG_C_COHERENTXCLW<<TLBLO_CSHIFT)
|
||||
#define TLBLO_COHERENTUPD (CFG_C_COHERENTUPD<<TLBLO_CSHIFT)
|
||||
|
||||
#define TLBINX_PROBE 0x80000000
|
||||
#define TLBINX_INXMASK 0x0000003f
|
||||
|
||||
#define TLBRAND_RANDMASK 0x0000003f
|
||||
|
||||
#define TLBCTXT_BASEMASK 0xff800000
|
||||
#define TLBCTXT_BASESHIFT 23
|
||||
|
||||
#define TLBCTXT_VPN2MASK 0x007ffff0
|
||||
#define TLBCTXT_VPN2SHIFT 4
|
||||
|
||||
#define TLBPGMASK_MASK 0x01ffe000
|
||||
#endif
|
||||
|
||||
#if __mips == 1
|
||||
|
||||
|
||||
/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
|
||||
#define DCIC_TR 0x80000000 /* Trap enable */
|
||||
#define DCIC_UD 0x40000000 /* User debug enable */
|
||||
#define DCIC_KD 0x20000000 /* Kernel debug enable */
|
||||
#define DCIC_TE 0x10000000 /* Trace enable */
|
||||
#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */
|
||||
#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */
|
||||
#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */
|
||||
#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */
|
||||
#define DCIC_DE 0x00800000 /* Debug enable */
|
||||
#define DCIC_DL 0x00008000 /* Data cache line invalidate */
|
||||
#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */
|
||||
#define DCIC_D 0x00002000 /* Data cache invalidate enable */
|
||||
#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */
|
||||
#define DCIC_T 0x00000020 /* Trace, set by CPU */
|
||||
#define DCIC_W 0x00000010 /* Write reference, set by CPU */
|
||||
#define DCIC_R 0x00000008 /* Read reference, set by CPU */
|
||||
#define DCIC_DA 0x00000004 /* Data address, set by CPU */
|
||||
#define DCIC_PC 0x00000002 /* Program counter, set by CPU */
|
||||
#define DCIC_DB 0x00000001 /* Debug, set by CPU */
|
||||
|
||||
|
||||
|
||||
|
||||
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
|
||||
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
|
||||
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
|
||||
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
|
||||
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
|
||||
|
||||
#define SR_BEV 0x00400000 /* use boot exception vectors */
|
||||
|
||||
/* Cache control bits */
|
||||
#define SR_TS 0x00200000 /* TLB shutdown */
|
||||
#define SR_PE 0x00100000 /* cache parity error */
|
||||
#define SR_CM 0x00080000 /* cache miss */
|
||||
#define SR_PZ 0x00040000 /* cache parity zero */
|
||||
#define SR_SWC 0x00020000 /* swap cache */
|
||||
#define SR_ISC 0x00010000 /* Isolate data cache */
|
||||
|
||||
/*
|
||||
** status register interrupt masks and bits
|
||||
*/
|
||||
|
||||
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
|
||||
#define SR_IMASK8 0x00000000 /* mask level 8 */
|
||||
#define SR_IMASK7 0x00008000 /* mask level 7 */
|
||||
#define SR_IMASK6 0x0000c000 /* mask level 6 */
|
||||
#define SR_IMASK5 0x0000e000 /* mask level 5 */
|
||||
#define SR_IMASK4 0x0000f000 /* mask level 4 */
|
||||
#define SR_IMASK3 0x0000f800 /* mask level 3 */
|
||||
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
|
||||
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
|
||||
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
|
||||
|
||||
#define SR_IMASKSHIFT 8
|
||||
|
||||
#define SR_IBIT8 0x00008000 /* bit level 8 */
|
||||
#define SR_IBIT7 0x00004000 /* bit level 7 */
|
||||
#define SR_IBIT6 0x00002000 /* bit level 6 */
|
||||
#define SR_IBIT5 0x00001000 /* bit level 5 */
|
||||
#define SR_IBIT4 0x00000800 /* bit level 4 */
|
||||
#define SR_IBIT3 0x00000400 /* bit level 3 */
|
||||
#define SR_IBIT2 0x00000200 /* bit level 2 */
|
||||
#define SR_IBIT1 0x00000100 /* bit level 1 */
|
||||
|
||||
#define SR_KUO 0x00000020 /* old kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEO 0x00000010 /* old interrupt enable, 1 => enable */
|
||||
#define SR_KUP 0x00000008 /* prev kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEP 0x00000004 /* prev interrupt enable, 1 => enable */
|
||||
#define SR_KUC 0x00000002 /* cur kernel/user, 0 => k, 1 => u */
|
||||
#define SR_IEC 0x00000001 /* cur interrupt enable, 1 => enable */
|
||||
#endif
|
||||
|
||||
#if __mips == 3
|
||||
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
|
||||
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
|
||||
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
|
||||
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
|
||||
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
|
||||
|
||||
#define SR_RP 0x08000000 /* Reduced power operation */
|
||||
#define SR_FR 0x04000000 /* Additional floating point registers */
|
||||
#define SR_RE 0x02000000 /* Reverse endian in user mode */
|
||||
|
||||
#define SR_BEV 0x00400000 /* Use boot exception vectors */
|
||||
#define SR_TS 0x00200000 /* TLB shutdown */
|
||||
#define SR_SR 0x00100000 /* Soft reset */
|
||||
#define SR_CH 0x00040000 /* Cache hit */
|
||||
#define SR_CE 0x00020000 /* Use cache ECC */
|
||||
#define SR_DE 0x00010000 /* Disable cache exceptions */
|
||||
|
||||
/*
|
||||
** status register interrupt masks and bits
|
||||
*/
|
||||
|
||||
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
|
||||
#define SR_IMASK8 0x00000000 /* mask level 8 */
|
||||
#define SR_IMASK7 0x00008000 /* mask level 7 */
|
||||
#define SR_IMASK6 0x0000c000 /* mask level 6 */
|
||||
#define SR_IMASK5 0x0000e000 /* mask level 5 */
|
||||
#define SR_IMASK4 0x0000f000 /* mask level 4 */
|
||||
#define SR_IMASK3 0x0000f800 /* mask level 3 */
|
||||
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
|
||||
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
|
||||
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
|
||||
|
||||
#define SR_IMASKSHIFT 8
|
||||
|
||||
#define SR_IBIT8 0x00008000 /* bit level 8 */
|
||||
#define SR_IBIT7 0x00004000 /* bit level 7 */
|
||||
#define SR_IBIT6 0x00002000 /* bit level 6 */
|
||||
#define SR_IBIT5 0x00001000 /* bit level 5 */
|
||||
#define SR_IBIT4 0x00000800 /* bit level 4 */
|
||||
#define SR_IBIT3 0x00000400 /* bit level 3 */
|
||||
#define SR_IBIT2 0x00000200 /* bit level 2 */
|
||||
#define SR_IBIT1 0x00000100 /* bit level 1 */
|
||||
|
||||
#define SR_KSMASK 0x00000018 /* Kernel mode mask */
|
||||
#define SR_KSUSER 0x00000010 /* User mode */
|
||||
#define SR_KSSUPER 0x00000008 /* Supervisor mode */
|
||||
#define SR_KSKERNEL 0x00000000 /* Kernel mode */
|
||||
#define SR_ERL 0x00000004 /* Error level */
|
||||
#define SR_EXL 0x00000002 /* Exception level */
|
||||
#define SR_IE 0x00000001 /* Interrupts enabled */
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define SR_CUMASK 0xf0000000 /* coproc usable bits */
|
||||
#define SR_CU3 0x80000000 /* Coprocessor 3 usable */
|
||||
#define SR_CU2 0x40000000 /* Coprocessor 2 usable */
|
||||
#define SR_CU1 0x20000000 /* Coprocessor 1 usable */
|
||||
#define SR_CU0 0x10000000 /* Coprocessor 0 usable */
|
||||
|
||||
#define SR_RP 0x08000000 /* Reduced power operation */
|
||||
#define SR_FR 0x04000000 /* Additional floating point registers */
|
||||
#define SR_RE 0x02000000 /* Reverse endian in user mode */
|
||||
|
||||
#define SR_BEV 0x00400000 /* Use boot exception vectors */
|
||||
#define SR_TS 0x00200000 /* TLB shutdown */
|
||||
#define SR_SR 0x00100000 /* Soft reset */
|
||||
#define SR_CH 0x00040000 /* Cache hit */
|
||||
#define SR_CE 0x00020000 /* Use cache ECC */
|
||||
#define SR_DE 0x00010000 /* Disable cache exceptions */
|
||||
|
||||
/*
|
||||
** status register interrupt masks and bits
|
||||
*/
|
||||
|
||||
#define SR_IMASK 0x0000ff00 /* Interrupt mask */
|
||||
#define SR_IMASK8 0x00000000 /* mask level 8 */
|
||||
#define SR_IMASK7 0x00008000 /* mask level 7 */
|
||||
#define SR_IMASK6 0x0000c000 /* mask level 6 */
|
||||
#define SR_IMASK5 0x0000e000 /* mask level 5 */
|
||||
#define SR_IMASK4 0x0000f000 /* mask level 4 */
|
||||
#define SR_IMASK3 0x0000f800 /* mask level 3 */
|
||||
#define SR_IMASK2 0x0000fc00 /* mask level 2 */
|
||||
#define SR_IMASK1 0x0000fe00 /* mask level 1 */
|
||||
#define SR_IMASK0 0x0000ff00 /* mask level 0 */
|
||||
|
||||
#define SR_IMASKSHIFT 8
|
||||
|
||||
#define SR_IBIT8 0x00008000 /* bit level 8 */
|
||||
#define SR_IBIT7 0x00004000 /* bit level 7 */
|
||||
#define SR_IBIT6 0x00002000 /* bit level 6 */
|
||||
#define SR_IBIT5 0x00001000 /* bit level 5 */
|
||||
#define SR_IBIT4 0x00000800 /* bit level 4 */
|
||||
#define SR_IBIT3 0x00000400 /* bit level 3 */
|
||||
#define SR_IBIT2 0x00000200 /* bit level 2 */
|
||||
#define SR_IBIT1 0x00000100 /* bit level 1 */
|
||||
|
||||
#define SR_KSMASK 0x00000018 /* Kernel mode mask */
|
||||
#define SR_KSUSER 0x00000010 /* User mode */
|
||||
#define SR_KSSUPER 0x00000008 /* Supervisor mode */
|
||||
#define SR_KSKERNEL 0x00000000 /* Kernel mode */
|
||||
#define SR_ERL 0x00000004 /* Error level */
|
||||
#define SR_EXL 0x00000002 /* Exception level */
|
||||
#define SR_IE 0x00000001 /* Interrupts enabled */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Cause Register
|
||||
*/
|
||||
#define CAUSE_BD 0x80000000 /* Branch delay slot */
|
||||
#define CAUSE_BT 0x40000000 /* Branch Taken */
|
||||
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
|
||||
#define CAUSE_CESHIFT 28
|
||||
|
||||
|
||||
#define CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */
|
||||
#define CAUSE_IPSHIFT 8
|
||||
|
||||
#define CAUSE_EXCMASK 0x0000003C /* Cause code bits */
|
||||
#define CAUSE_EXCSHIFT 2
|
||||
|
||||
#ifndef XDS
|
||||
/*
|
||||
** Coprocessor 0 registers
|
||||
*/
|
||||
#define C0_INX $0 /* tlb index */
|
||||
#define C0_RAND $1 /* tlb random */
|
||||
#if __mips == 1
|
||||
#define C0_TLBLO $2 /* tlb entry low */
|
||||
#endif
|
||||
#if __mips == 3
|
||||
#define C0_TLBLO0 $2 /* tlb entry low 0 */
|
||||
#define C0_TLBLO1 $3 /* tlb entry low 1 */
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define C0_TLBLO0 $2 /* tlb entry low 0 */
|
||||
#define C0_TLBLO1 $3 /* tlb entry low 1 */
|
||||
#endif
|
||||
|
||||
|
||||
#define C0_CTXT $4 /* tlb context */
|
||||
|
||||
#if __mips == 3
|
||||
#define C0_PAGEMASK $5 /* tlb page mask */
|
||||
#define C0_WIRED $6 /* number of wired tlb entries */
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define C0_PAGEMASK $5 /* tlb page mask */
|
||||
#define C0_WIRED $6 /* number of wired tlb entries */
|
||||
#endif
|
||||
|
||||
#if __mips == 1
|
||||
#define C0_TAR $6
|
||||
#endif
|
||||
|
||||
#define C0_BADVADDR $8 /* bad virtual address */
|
||||
|
||||
#if __mips == 3
|
||||
#define C0_COUNT $9 /* cycle count */
|
||||
#endif
|
||||
#if __mips == 32
|
||||
#define C0_COUNT $9 /* cycle count */
|
||||
#endif
|
||||
|
||||
#define C0_TLBHI $10 /* tlb entry hi */
|
||||
|
||||
#if __mips == 3
|
||||
#define C0_COMPARE $11 /* cyccle count comparator */
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define C0_COMPARE $11 /* cyccle count comparator */
|
||||
#endif
|
||||
|
||||
#define C0_SR $12 /* status register */
|
||||
#define C0_CAUSE $13 /* exception cause */
|
||||
#define C0_EPC $14 /* exception pc */
|
||||
#define C0_PRID $15 /* revision identifier */
|
||||
|
||||
#if __mips == 1
|
||||
#define C0_CONFIG $3 /* configuration register R3081*/
|
||||
#endif
|
||||
|
||||
#if __mips == 3
|
||||
#define C0_CONFIG $16 /* configuration register */
|
||||
#define C0_LLADDR $17 /* linked load address */
|
||||
#define C0_WATCHLO $18 /* watchpoint trap register */
|
||||
#define C0_WATCHHI $19 /* watchpoint trap register */
|
||||
#define C0_XCTXT $20 /* extended tlb context */
|
||||
#define C0_ECC $26 /* secondary cache ECC control */
|
||||
#define C0_CACHEERR $27 /* cache error status */
|
||||
#define C0_TAGLO $28 /* cache tag lo */
|
||||
#define C0_TAGHI $29 /* cache tag hi */
|
||||
#define C0_ERRPC $30 /* cache error pc */
|
||||
#endif
|
||||
|
||||
#if __mips == 32
|
||||
#define C0_CONFIG $16 /* configuration register */
|
||||
#define C0_LLADDR $17 /* linked load address */
|
||||
#define C0_WATCHLO $18 /* watchpoint trap register */
|
||||
#define C0_WATCHHI $19 /* watchpoint trap register */
|
||||
#define C0_XCTXT $20 /* extended tlb context */
|
||||
#define C0_ECC $26 /* secondary cache ECC control */
|
||||
#define C0_CACHEERR $27 /* cache error status */
|
||||
#define C0_TAGLO $28 /* cache tag lo */
|
||||
#define C0_TAGHI $29 /* cache tag hi */
|
||||
#define C0_ERRPC $30 /* cache error pc */
|
||||
#endif
|
||||
|
||||
|
||||
#define C1_REVISION $0
|
||||
#define C1_STATUS $31
|
||||
|
||||
#endif /* XDS */
|
||||
|
||||
#ifdef R4650
|
||||
#define IWATCH $18
|
||||
#define DWATCH $19
|
||||
#define IBASE $0
|
||||
#define IBOUND $1
|
||||
#define DBASE $2
|
||||
#define DBOUND $3
|
||||
#define CALG $17
|
||||
#endif
|
||||
|
||||
#endif /* _IDTCPU_H__ */
|
||||
|
||||
@@ -1,332 +0,0 @@
|
||||
/*
|
||||
|
||||
Based upon IDT provided code with the following release:
|
||||
|
||||
This source code has been made available to you by IDT on an AS-IS
|
||||
basis. Anyone receiving this source is licensed under IDT copyrights
|
||||
to use it in any way he or she deems fit, including copying it,
|
||||
modifying it, compiling it, and redistributing it either with or
|
||||
without modifications. No license under IDT patents or patent
|
||||
applications is to be implied by the copyright license.
|
||||
|
||||
Any user of this software should understand that IDT cannot provide
|
||||
technical support for this software and will not be responsible for
|
||||
any consequences resulting from the use of this software.
|
||||
|
||||
Any person who transfers this source code or any derivative work must
|
||||
include the IDT copyright notice, this paragraph, and the preceeding
|
||||
two paragraphs in the transferred software.
|
||||
|
||||
COPYRIGHT IDT CORPORATION 1996
|
||||
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
|
||||
|
||||
$Id$
|
||||
*/
|
||||
|
||||
/*
|
||||
** iregdef.h - IDT R3000 register structure header file
|
||||
**
|
||||
** Copyright 1989 Integrated Device Technology, Inc
|
||||
** All Rights Reserved
|
||||
**
|
||||
*/
|
||||
#ifndef __IREGDEF_H__
|
||||
#define __IREGDEF_H__
|
||||
|
||||
/*
|
||||
* 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
|
||||
* added Register definition for XContext reg.
|
||||
* Look towards end of this file.
|
||||
*/
|
||||
/*
|
||||
** register names
|
||||
*/
|
||||
#define r0 $0
|
||||
#define r1 $1
|
||||
#define r2 $2
|
||||
#define r3 $3
|
||||
#define r4 $4
|
||||
#define r5 $5
|
||||
#define r6 $6
|
||||
#define r7 $7
|
||||
#define r8 $8
|
||||
#define r9 $9
|
||||
#define r10 $10
|
||||
#define r11 $11
|
||||
#define r12 $12
|
||||
#define r13 $13
|
||||
|
||||
#define r14 $14
|
||||
#define r15 $15
|
||||
#define r16 $16
|
||||
#define r17 $17
|
||||
#define r18 $18
|
||||
#define r19 $19
|
||||
#define r20 $20
|
||||
#define r21 $21
|
||||
#define r22 $22
|
||||
#define r23 $23
|
||||
#define r24 $24
|
||||
#define r25 $25
|
||||
#define r26 $26
|
||||
#define r27 $27
|
||||
#define r28 $28
|
||||
#define r29 $29
|
||||
#define r30 $30
|
||||
#define r31 $31
|
||||
|
||||
#define fp0 $f0
|
||||
#define fp1 $f1
|
||||
#define fp2 $f2
|
||||
#define fp3 $f3
|
||||
#define fp4 $f4
|
||||
#define fp5 $f5
|
||||
#define fp6 $f6
|
||||
#define fp7 $f7
|
||||
#define fp8 $f8
|
||||
#define fp9 $f9
|
||||
#define fp10 $f10
|
||||
#define fp11 $f11
|
||||
#define fp12 $f12
|
||||
#define fp13 $f13
|
||||
#define fp14 $f14
|
||||
#define fp15 $f15
|
||||
#define fp16 $f16
|
||||
#define fp17 $f17
|
||||
#define fp18 $f18
|
||||
#define fp19 $f19
|
||||
#define fp20 $f20
|
||||
#define fp21 $f21
|
||||
#define fp22 $f22
|
||||
#define fp23 $f23
|
||||
#define fp24 $f24
|
||||
#define fp25 $f25
|
||||
#define fp26 $f26
|
||||
#define fp27 $f27
|
||||
#define fp28 $f28
|
||||
#define fp29 $f29
|
||||
#define fp30 $f30
|
||||
#define fp31 $f31
|
||||
|
||||
#define fcr0 $0
|
||||
#define fcr30 $30
|
||||
#define fcr31 $31
|
||||
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $at /* assembler temp */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers a0-a3 */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved t0-t9 */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
#define s0 $16 /* callee saved s0-s8 */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define k0 $26 /* kernel usage */
|
||||
#define k1 $27 /* kernel usage */
|
||||
#define gp $28 /* sdata pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define s8 $30 /* yet another saved reg for the callee */
|
||||
#define fp $30 /* frame pointer - this is being phased out by MIPS */
|
||||
#define ra $31 /* return address */
|
||||
|
||||
|
||||
/*
|
||||
** relative position of registers in interrupt/exception frame
|
||||
*/
|
||||
#define R_R0 0
|
||||
#define R_R1 1
|
||||
#define R_R2 2
|
||||
#define R_R3 3
|
||||
#define R_R4 4
|
||||
#define R_R5 5
|
||||
#define R_R6 6
|
||||
#define R_R7 7
|
||||
#define R_R8 8
|
||||
#define R_R9 9
|
||||
#define R_R10 10
|
||||
#define R_R11 11
|
||||
#define R_R12 12
|
||||
#define R_R13 13
|
||||
#define R_R14 14
|
||||
#define R_R15 15
|
||||
#define R_R16 16
|
||||
#define R_R17 17
|
||||
#define R_R18 18
|
||||
#define R_R19 19
|
||||
#define R_R20 20
|
||||
#define R_R21 21
|
||||
#define R_R22 22
|
||||
#define R_R23 23
|
||||
#define R_R24 24
|
||||
#define R_R25 25
|
||||
#define R_R26 26
|
||||
#define R_R27 27
|
||||
#define R_R28 28
|
||||
#define R_R29 29
|
||||
#define R_R30 30
|
||||
#define R_R31 31
|
||||
|
||||
#define R_SR 32
|
||||
#define R_MDLO 33
|
||||
#define R_MDHI 34
|
||||
#define R_BADVADDR 35
|
||||
#define R_CAUSE 36
|
||||
#define R_EPC 37
|
||||
|
||||
#define R_F0 38
|
||||
#define R_F1 39
|
||||
#define R_F2 40
|
||||
#define R_F3 41
|
||||
#define R_F4 42
|
||||
#define R_F5 43
|
||||
#define R_F6 44
|
||||
#define R_F7 45
|
||||
#define R_F8 46
|
||||
#define R_F9 47
|
||||
#define R_F10 48
|
||||
#define R_F11 49
|
||||
#define R_F12 50
|
||||
#define R_F13 41
|
||||
#define R_F14 42
|
||||
#define R_F15 43
|
||||
#define R_F16 44
|
||||
#define R_F17 45
|
||||
#define R_F18 56
|
||||
#define R_F19 57
|
||||
#define R_F20 58
|
||||
#define R_F21 59
|
||||
#define R_F22 60
|
||||
#define R_F23 61
|
||||
#define R_F24 62
|
||||
#define R_F25 63
|
||||
#define R_F26 64
|
||||
#define R_F27 65
|
||||
#define R_F28 66
|
||||
#define R_F29 67
|
||||
#define R_F30 68
|
||||
#define R_F31 69
|
||||
#define R_FCSR 70
|
||||
#define R_FEIR 71
|
||||
#define R_TLBHI 72
|
||||
|
||||
#if __mips == 1
|
||||
#define R_TLBLO 73
|
||||
#endif
|
||||
#if (__mips == 3 ) || ( __mips == 32)
|
||||
#define R_TLBLO0 73
|
||||
#endif
|
||||
|
||||
#define R_INX 74
|
||||
#define R_RAND 75
|
||||
#define R_CTXT 76
|
||||
#define R_EXCTYPE 77
|
||||
#define R_MODE 78
|
||||
#define R_PRID 79
|
||||
#define R_TAR 80
|
||||
#if __mips == 1
|
||||
#define NREGS 81
|
||||
#endif
|
||||
#if (__mips == 3 ) || ( __mips == 32)
|
||||
#define R_TLBLO1 81
|
||||
#define R_PAGEMASK 82
|
||||
#define R_WIRED 83
|
||||
#define R_COUNT 84
|
||||
#define R_COMPARE 85
|
||||
#define R_CONFIG 86
|
||||
#define R_LLADDR 87
|
||||
#define R_WATCHLO 88
|
||||
#define R_WATCHHI 89
|
||||
#define R_ECC 90
|
||||
#define R_CACHEERR 91
|
||||
#define R_TAGLO 92
|
||||
#define R_TAGHI 93
|
||||
#define R_ERRPC 94
|
||||
#define R_XCTXT 95 /* Ketan added from SIM64bit */
|
||||
|
||||
#define NREGS 96
|
||||
#endif
|
||||
|
||||
/*
|
||||
** For those who like to think in terms of the compiler names for the regs
|
||||
*/
|
||||
#define R_ZERO R_R0
|
||||
#define R_AT R_R1
|
||||
#define R_V0 R_R2
|
||||
#define R_V1 R_R3
|
||||
#define R_A0 R_R4
|
||||
#define R_A1 R_R5
|
||||
#define R_A2 R_R6
|
||||
#define R_A3 R_R7
|
||||
#define R_T0 R_R8
|
||||
#define R_T1 R_R9
|
||||
#define R_T2 R_R10
|
||||
#define R_T3 R_R11
|
||||
#define R_T4 R_R12
|
||||
#define R_T5 R_R13
|
||||
#define R_T6 R_R14
|
||||
#define R_T7 R_R15
|
||||
#define R_S0 R_R16
|
||||
#define R_S1 R_R17
|
||||
#define R_S2 R_R18
|
||||
#define R_S3 R_R19
|
||||
#define R_S4 R_R20
|
||||
#define R_S5 R_R21
|
||||
#define R_S6 R_R22
|
||||
#define R_S7 R_R23
|
||||
#define R_T8 R_R24
|
||||
#define R_T9 R_R25
|
||||
#define R_K0 R_R26
|
||||
#define R_K1 R_R27
|
||||
#define R_GP R_R28
|
||||
#define R_SP R_R29
|
||||
#define R_FP R_R30
|
||||
#define R_RA R_R31
|
||||
|
||||
/* disabled for RTEMS */
|
||||
#if 0
|
||||
/* Ketan added the following */
|
||||
#if __mips == 1
|
||||
#define sreg sw
|
||||
#define lreg lw
|
||||
#define rmfc0 mfc0
|
||||
#define rmtc0 mtc0
|
||||
#define R_SZ 4
|
||||
#endif /* __mips == 1 */
|
||||
|
||||
/* #ifdef __mips == 3 */
|
||||
#if __mips < 3
|
||||
#define sreg sw
|
||||
#define lreg lw
|
||||
#define rmfc0 mfc0
|
||||
#define rmtc0 mtc0
|
||||
#define R_SZ 4
|
||||
#else
|
||||
#define sreg sd
|
||||
#define lreg ld
|
||||
#define rmfc0 dmfc0
|
||||
#define rmtc0 dmtc0
|
||||
#define R_SZ 8
|
||||
#endif
|
||||
/* #endif __mips == 3 */
|
||||
/* Ketan till here */
|
||||
#endif
|
||||
|
||||
#endif /* __IREGDEF_H__ */
|
||||
|
||||
Reference in New Issue
Block a user