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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-12-02 09:48:25 +00:00
parent 882b187528
commit 80f77327f3
20 changed files with 190 additions and 190 deletions
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10
cpukit/score/cpu/nios2/cpu.c
View File

@@ -46,7 +46,7 @@ void _CPU_Initialize(void)
*
* XXX document implementation including references if appropriate
*/
uint32_t _CPU_ISR_Get_level( void )
{
/*
@@ -64,7 +64,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -166,10 +166,10 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
/* Differentiate between IRQ off and on (for debugging) */
if(st & 1)
for(;;);
for(;;);
else
for(;;);
for(;;);
/* insert your "halt" instruction here */ ;
}
#endif

24
cpukit/score/cpu/nios2/cpu_asm.S
View File

@@ -89,12 +89,12 @@ _CPU_Context_restore:
_exception_vector:
/*
/*
* First, re-wind so we're pointed to the instruction where the exception
* occurred.
*/
addi ea, ea, -4
addi ea, ea, -4
/*
* Now test to determine the cause of the exception.
@@ -117,7 +117,7 @@ _exception_vector:
br _ISR_Handler
/* =====================================================================
/* =====================================================================
* Exception handler:
* Responsible for unimplemented instructions and other software
* exceptions. Not responsible for hardware interrupts. Currently,
@@ -182,7 +182,7 @@ _Exception_Handler:
addi gp, gp, %lo(_gp)
/*
* Pass a pointer to the stack frame as the input argument of the
* Pass a pointer to the stack frame as the input argument of the
* exception handler (CPU_Exception_frame *).
*/
@@ -198,8 +198,8 @@ _Exception_Handler:
stuck_in_exception:
br stuck_in_exception
/*
* Restore the saved registers, so that all general purpose registers
/*
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/
@@ -252,13 +252,13 @@ stuck_in_exception:
_ISR_Handler:
/*
* Process an external hardware interrupt.
/*
* Process an external hardware interrupt.
*
* First, preserve all callee saved registers on
* First, preserve all callee saved registers on
* the stack. (See the Nios2 ABI documentation for details).
*
* Do we really need to save all?
* Do we really need to save all?
*
* If this is interrupting a task (and not another interrupt),
* everything is saved into the task's stack, thus putting us
@@ -331,13 +331,13 @@ _ISR_Handler:
.extern __ISR_Handler
call __ISR_Handler
/*
/*
* Now that the interrupt processing is complete, prepare to return to
* the interrupted code.
*/
/*
* Restore the saved registers, so that all general purpose registers
* Restore the saved registers, so that all general purpose registers
* have been restored to their state at the time the interrupt occured.
*/

32
cpukit/score/cpu/nios2/rtems/score/cpu.h
View File

@@ -13,7 +13,7 @@
*
* + Anywhere there is an XXX, it should be replaced
* with information about the CPU family being ported to.
*
*
* + At the end of each comment section, there is a heading which
* says "Port Specific Information:". When porting to RTEMS,
* add CPU family specific information in this section
@@ -168,7 +168,7 @@ extern "C" {
/**
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*
* Port Specific Information:
@@ -194,7 +194,7 @@ extern "C" {
* an i387 and wish to leave floating point support out of RTEMS.
*/
/**
/**
* @def CPU_SOFTWARE_FP
*
* Does the CPU have no hardware floating point and GCC provides a
@@ -202,7 +202,7 @@ extern "C" {
* switched?
*
* This feature conditional is used to indicate whether or not there
* is software implemented floating point that must be context
* is software implemented floating point that must be context
* switched. The determination of whether or not this applies
* is very tool specific and the state saved/restored is also
* compiler specific.
@@ -519,7 +519,7 @@ typedef struct {
/**
* @ingroup CPUContext Management
* This defines the set of integer and processor state registers that are
* This defines the set of integer and processor state registers that are
* saved during a software exception.
*/
typedef struct {
@@ -592,14 +592,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
@@ -694,7 +694,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
*
* @note This does not have to be a power of 2 although it should be
* a multiple of 2 greater than or equal to 2. The requirement
* to be a multiple of 2 is because the heap uses the least
* to be a multiple of 2 is because the heap uses the least
* significant field of the front and back flags to indicate
* that a block is in use or free. So you do not want any odd
* length blocks really putting length data in that bit.
@@ -990,7 +990,7 @@ uint32_t _CPU_ISR_Get_level( void );
/**
* @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
*
* This set of routines are used to implement fast searches for
* This set of routines are used to implement fast searches for
* the most important ready task.
*/
@@ -1015,7 +1015,7 @@ uint32_t _CPU_ISR_Get_level( void );
/**
* @ingroup CPUBitfield
* This routine sets @a _output to the bit number of the first bit
* set in @a _value. @a _value is of CPU dependent type
* set in @a _value. @a _value is of CPU dependent type
* @a Priority_Bit_map_control. This type may be either 16 or 32 bits
* wide although only the 16 least significant bits will be used.
*
@@ -1058,14 +1058,14 @@ uint32_t _CPU_ISR_Get_level( void );
if _value > 0x00ff
_value >>=8
_number = 8;
if _value > 0x0000f
_value >=8
_number += 4
_number += bit_set_table[ _value ]
@endverbatim
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*
@@ -1137,7 +1137,7 @@ void _CPU_Initialize(void);
/**
* @ingroup CPUInterrupt
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*
* @param vector (in) is the vector number
@@ -1299,12 +1299,12 @@ static inline uint32_t CPU_swap_u32(
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}

6
cpukit/score/cpu/nios2/rtems/score/nios2.h
View File

@@ -1,6 +1,6 @@
/* nios2.h
*
* This file sets up basic CPU dependency settings based on
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation
* is specific to the NIOS2 port.
@@ -35,7 +35,7 @@ extern "C" {
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
/*
* Define the name of the CPU family and specific model.
*/
@@ -45,7 +45,7 @@ extern "C" {
/*
* See also nios2-rtems-gcc -print-multi-lib for all valid combinations of
*
*
* -mno-hw-mul
* -mhw-mulx
* -mstack-check

2
cpukit/score/cpu/nios2/rtems/score/types.h
View File

@@ -3,7 +3,7 @@
*/
/*
* This include file contains type definitions pertaining to the
* This include file contains type definitions pertaining to the
* Altera Nios II processor family.
*
* COPYRIGHT (c) 1989-1999.

4
cpukit/score/cpu/no_cpu/cpu.c
View File

@@ -47,7 +47,7 @@ void _CPU_Initialize(void)
*
* XXX document implementation including references if appropriate
*/
uint32_t _CPU_ISR_Get_level( void )
{
/*
@@ -65,7 +65,7 @@ uint32_t _CPU_ISR_Get_level( void )
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,

2
cpukit/score/cpu/no_cpu/cpu_asm.c
View File

@@ -173,7 +173,7 @@ void _ISR_Handler(void)
*
* LABEL "exit interrupt (simple case):
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* if outermost interrupt
* if outermost interrupt
* restore stack
* #endif
* prepare to get out of interrupt

38
cpukit/score/cpu/no_cpu/rtems/score/cpu.h
View File

@@ -13,7 +13,7 @@
*
* + Anywhere there is an XXX, it should be replaced
* with information about the CPU family being ported to.
*
*
* + At the end of each comment section, there is a heading which
* says "Port Specific Information:". When porting to RTEMS,
* add CPU family specific information in this section
@@ -168,7 +168,7 @@ extern "C" {
/**
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*
* Port Specific Information:
@@ -195,7 +195,7 @@ extern "C" {
* an i387 and wish to leave floating point support out of RTEMS.
*/
/**
/**
* @def CPU_SOFTWARE_FP
*
* Does the CPU have no hardware floating point and GCC provides a
@@ -203,7 +203,7 @@ extern "C" {
* switched?
*
* This feature conditional is used to indicate whether or not there
* is software implemented floating point that must be context
* is software implemented floating point that must be context
* switched. The determination of whether or not this applies
* is very tool specific and the state saved/restored is also
* compiler specific.
@@ -466,11 +466,11 @@ extern "C" {
* to another.
*/
typedef struct {
/** This field is a hint that a port will have a number of integer
/** This field is a hint that a port will have a number of integer
* registers that need to be saved at a context switch.
*/
uint32_t some_integer_register;
/** This field is a hint that a port will have a number of system
/** This field is a hint that a port will have a number of system
* registers that need to be saved at a context switch.
*/
uint32_t some_system_register;
@@ -487,7 +487,7 @@ typedef struct {
* This macro returns the stack pointer associated with @a _context.
*
* @param[in] _context is the thread context area to access
*
*
* @return This method returns the stack pointer.
*/
#define _CPU_Context_Get_SP( _context ) \
@@ -510,7 +510,7 @@ typedef struct {
* in @ref Context_Control.
*/
typedef struct {
/** This field is a hint that a port will have a number of integer
/** This field is a hint that a port will have a number of integer
* registers that need to be saved when an interrupt occurs or
* when a context switch occurs at the end of an ISR.
*/
@@ -550,14 +550,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_low;
/**
* @ingroup CPUInterrupt
* This variable points to the lowest physical address of the interrupt
* This variable points to the lowest physical address of the interrupt
* stack.
*/
SCORE_EXTERN void *_CPU_Interrupt_stack_high;
@@ -651,7 +651,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high;
*
* @note This does not have to be a power of 2 although it should be
* a multiple of 2 greater than or equal to 2. The requirement
* to be a multiple of 2 is because the heap uses the least
* to be a multiple of 2 is because the heap uses the least
* significant field of the front and back flags to indicate
* that a block is in use or free. So you do not want any odd
* length blocks really putting length data in that bit.
@@ -926,7 +926,7 @@ uint32_t _CPU_ISR_Get_level( void );
/**
* @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
*
* This set of routines are used to implement fast searches for
* This set of routines are used to implement fast searches for
* the most important ready task.
*/
@@ -951,7 +951,7 @@ uint32_t _CPU_ISR_Get_level( void );
/**
* @ingroup CPUBitfield
* This routine sets @a _output to the bit number of the first bit
* set in @a _value. @a _value is of CPU dependent type
* set in @a _value. @a _value is of CPU dependent type
* @a Priority_Bit_map_control. This type may be either 16 or 32 bits
* wide although only the 16 least significant bits will be used.
*
@@ -994,14 +994,14 @@ uint32_t _CPU_ISR_Get_level( void );
if _value > 0x00ff
_value >>=8
_number = 8;
if _value > 0x0000f
_value >=8
_number += 4
_number += bit_set_table[ _value ]
@endverbatim
* where bit_set_table[ 16 ] has values which indicate the first
* bit set
*
@@ -1073,7 +1073,7 @@ void _CPU_Initialize(void);
/**
* @ingroup CPUInterrupt
* This routine installs a "raw" interrupt handler directly into the
* This routine installs a "raw" interrupt handler directly into the
* processor's vector table.
*
* @param[in] vector is the vector number
@@ -1235,12 +1235,12 @@ static inline uint32_t CPU_swap_u32(
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return swapped;
}

16
cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h
View File

@@ -1,6 +1,6 @@
/* no_cpu.h
*
* This file sets up basic CPU dependency settings based on
* This file sets up basic CPU dependency settings based on
* compiler settings. For example, it can determine if
* floating point is available. This particular implementation
* is specified to the NO CPU port.
@@ -35,25 +35,25 @@ extern "C" {
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define NOCPU_HAS_FPU 1
#elif defined(no_cpu)
#define CPU_MODEL_NAME "no_cpu_model"
#define NOCPU_HAS_FPU 1
#else
#error "Unsupported CPU Model"
#endif
/*

38
cpukit/score/cpu/sparc/cpu.c
View File

@@ -16,7 +16,7 @@
#include <rtems/rtems/cache.h>
/*
* This initializes the set of opcodes placed in each trap
* This initializes the set of opcodes placed in each trap
* table entry. The routine which installs a handler is responsible
* for filling in the fields for the _handler address and the _vector
* trap type.
@@ -41,7 +41,7 @@ const CPU_Trap_table_entry _CPU_Trap_slot_template = {
* INPUT PARAMETERS: NONE
*
* Output Parameters: NONE
*
*
* NOTE: There is no need to save the pointer to the thread dispatch routine.
* The SPARC's assembly code can reference it directly with no problems.
*/
@@ -78,13 +78,13 @@ void _CPU_Initialize(void)
* Output Parameters:
* returns the current interrupt level (PIL field of the PSR)
*/
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t level;
sparc_get_interrupt_level( level );
return level;
}
@@ -96,15 +96,15 @@ uint32_t _CPU_ISR_Get_level( void )
* supported trap handler (a.k.a. interrupt service routine).
*
* Input Parameters:
* vector - trap table entry number plus synchronous
* vector - trap table entry number plus synchronous
* vs. asynchronous information
* new_handler - address of the handler to be installed
* old_handler - pointer to an address of the handler previously installed
*
* Output Parameters: NONE
* *new_handler - address of the handler previously installed
*
* NOTE:
*
* NOTE:
*
* On the SPARC, there are really only 256 vectors. However, the executive
* has no easy, fast, reliable way to determine which traps are synchronous
@@ -125,7 +125,7 @@ uint32_t _CPU_ISR_Get_level( void )
* an asynchronous trap. This will avoid the executive changing the return
* address.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -170,7 +170,7 @@ void _CPU_ISR_install_raw_handler(
#define LOW_BITS_MASK 0x000003FF
if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
u32_handler =
u32_handler =
(slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) |
(slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
*old_handler = (proc_ptr) u32_handler;
@@ -186,7 +186,7 @@ void _CPU_ISR_install_raw_handler(
u32_handler = (uint32_t) new_handler;
slot->mov_vector_l3 |= vector;
slot->sethi_of_handler_to_l4 |=
slot->sethi_of_handler_to_l4 |=
(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
@@ -208,7 +208,7 @@ void _CPU_ISR_install_raw_handler(
* new_handler - replacement ISR for this vector number
* old_handler - pointer to former ISR for this vector number
*
* Output parameters:
* Output parameters:
* *old_handler - former ISR for this vector number
*
*/
@@ -279,21 +279,21 @@ void _CPU_Context_Initialize(
uint32_t stack_high; /* highest "stack aligned" address */
uint32_t the_size;
uint32_t tmp_psr;
/*
* On CPUs with stacks which grow down (i.e. SPARC), we build the stack
* based on the stack_high address.
* based on the stack_high address.
*/
stack_high = ((uint32_t)(stack_base) + size);
stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
/*
* See the README in this directory for a diagram of the stack.
*/
the_context->o7 = ((uint32_t) entry_point) - 8;
the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
the_context->i6_fp = 0;
@@ -311,7 +311,7 @@ void _CPU_Context_Initialize(
tmp_psr &= ~SPARC_PSR_PIL_MASK;
tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */
#if (SPARC_HAS_FPU == 1)
/*
* If this bit is not set, then a task gets a fault when it accesses

48
cpukit/score/cpu/sparc/cpu_asm.S
View File

@@ -2,7 +2,7 @@
*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language.
* in assembly language.
*
* COPYRIGHT (c) 1989-2007.
* On-Line Applications Research Corporation (OAR).
@@ -12,10 +12,10 @@
* http://www.rtems.com/license/LICENSE.
*
* Ported to ERC32 implementation of the SPARC by On-Line Applications
* Research Corporation (OAR) under contract to the European Space
* Research Corporation (OAR) under contract to the European Space
* Agency (ESA).
*
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
* European Space Agency.
*
* $Id$
@@ -34,7 +34,7 @@
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* NOTE: See the README in this directory for information on the
* NOTE: See the README in this directory for information on the
* management of the "EF" bit in the PSR.
*/
@@ -46,13 +46,13 @@ SYM(_CPU_Context_save_fp):
/*
* The following enables the floating point unit.
*/
mov %psr, %l0
sethi %hi(SPARC_PSR_EF_MASK), %l1
or %l1, %lo(SPARC_PSR_EF_MASK), %l1
or %l0, %l1, %l0
mov %l0, %psr ! **** ENABLE FLOAT ACCESS ****
nop; nop; nop; ! Need three nops before EF is
nop; nop; nop; ! Need three nops before EF is
ld [%i0], %l0 ! active due to pipeline delay!!!
std %f0, [%l0 + FO_F1_OFFSET]
std %f2, [%l0 + F2_F3_OFFSET]
@@ -83,7 +83,7 @@ SYM(_CPU_Context_save_fp):
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* NOTE: See the README in this directory for information on the
* NOTE: See the README in this directory for information on the
* management of the "EF" bit in the PSR.
*/
@@ -95,13 +95,13 @@ SYM(_CPU_Context_restore_fp):
/*
* The following enables the floating point unit.
*/
mov %psr, %l0
sethi %hi(SPARC_PSR_EF_MASK), %l1
or %l1, %lo(SPARC_PSR_EF_MASK), %l1
or %l0, %l1, %l0
mov %l0, %psr ! **** ENABLE FLOAT ACCESS ****
nop; nop; nop; ! Need three nops before EF is
nop; nop; nop; ! Need three nops before EF is
ld [%i0], %l0 ! active due to pipeline delay!!!
ldd [%l0 + FO_F1_OFFSET], %f0
ldd [%l0 + F2_F3_OFFSET], %f2
@@ -181,9 +181,9 @@ SYM(_CPU_Context_restore_heir):
* Flush all windows with valid contents except the current one.
* In examining the set register windows, one may logically divide
* the windows into sets (some of which may be empty) based on their
* current status:
* current status:
*
* + current (i.e. in use),
* + current (i.e. in use),
* + used (i.e. a restore would not trap)
* + invalid (i.e. 1 in corresponding bit in WIM)
* + unused
@@ -202,9 +202,9 @@ SYM(_CPU_Context_restore_heir):
*
* In this case, we only would save the used windows -- 6 and 7.
*
* Traps are disabled for the same logical period as in a
* Traps are disabled for the same logical period as in a
* flush all windows trap handler.
*
*
* Register Usage while saving the windows:
* g1 = current PSR
* g2 = current wim
@@ -238,17 +238,17 @@ save_frame_loop:
bnz done_flushing ! No, then continue
nop
restore ! back one window
restore ! back one window
/*
* Now save the window just as if we overflowed to it.
*/
std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
@@ -262,7 +262,7 @@ done_flushing:
add %g3, 1, %g3 ! calculate desired WIM
and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
mov 1, %g4
sll %g4, %g3, %g4 ! g4 = new WIM
sll %g4, %g3, %g4 ! g4 = new WIM
mov %g4, %wim
or %g1, SPARC_PSR_ET_MASK, %g1
@@ -559,9 +559,9 @@ fpu_revb:
bne,a dont_fix_pil2
wr %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
ba,a simple_return
enable_irq:
or %g5, SPARC_PSR_PIL_MASK, %g4
or %g5, SPARC_PSR_PIL_MASK, %g4
wr %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
nop; nop; nop
fmovs %f0, %f0
@@ -658,7 +658,7 @@ dont_fix_pil2:
bnz simple_return ! Yes, then do a "simple" exit
! NOTE: Use the delay slot
sethi %hi(SYM(_Context_Switch_necessary)), %l4
/*
* If a context switch is necessary, then do fudge stack to
@@ -685,7 +685,7 @@ dont_fix_pil2:
! use the delay slot to clear the signals
! to the currently executing task flag
st %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
/*
* Invoke interrupt dispatcher.
@@ -707,7 +707,7 @@ SYM(_ISR_Dispatch):
sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
mov %l7, %psr ! **** ENABLE TRAPS ****
nop
nop
@@ -719,7 +719,7 @@ isr_dispatch:
/*
* We invoked _Thread_Dispatch in a state similar to the interrupted
* task. In order to safely be able to tinker with the register
* windows and get the task back to its pre-interrupt state,
* windows and get the task back to its pre-interrupt state,
* we need to disable interrupts disabled so we can safely tinker
* with the register windowing. In particular, the CWP in the PSR
* is fragile during this period. (See PR578.)
@@ -788,7 +788,7 @@ simple_return:
and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
or %l3, %l0, %l0 ! install it later...
andn %l0, SPARC_PSR_ET_MASK, %l0
andn %l0, SPARC_PSR_ET_MASK, %l0
/*
* Restore tasks global and out registers

4
cpukit/score/cpu/sparc/rtems/asm.h
View File

@@ -99,7 +99,7 @@
/*
* Entry for traps which jump to a programmer-specified trap handler.
*/
#define TRAP(_vector, _handler) \
mov %psr, %l0 ; \
sethi %hi(_handler), %l4 ; \
@@ -109,7 +109,7 @@
/*
* Used for the reset trap to avoid a supervisor instruction
*/
#define RTRAP(_vector, _handler) \
mov %g0, %l0 ; \
sethi %hi(_handler), %l4 ; \

52
cpukit/score/cpu/sparc/rtems/score/cpu.h
View File

@@ -3,7 +3,7 @@
*/
/*
* This include file contains information pertaining to the port of
* This include file contains information pertaining to the port of
* the executive to the SPARC processor.
*
* COPYRIGHT (c) 1989-2006.
@@ -103,7 +103,7 @@ extern "C" {
/*
* Does the RTEMS invoke the user's ISR with the vector number and
* a pointer to the saved interrupt frame (1) or just the vector
* a pointer to the saved interrupt frame (1) or just the vector
* number (0)?
*/
@@ -191,7 +191,7 @@ extern "C" {
* the minimum requirements of the compiler in order to have as
* much of the critical data area as possible in a cache line.
*
* The SPARC does not appear to have particularly strict alignment
* The SPARC does not appear to have particularly strict alignment
* requirements. This value was chosen to take advantages of caches.
*/
@@ -216,7 +216,7 @@ extern "C" {
#define CPU_MODES_INTERRUPT_MASK 0x0000000F
/*
* This structure represents the organization of the minimum stack frame
* This structure represents the organization of the minimum stack frame
* for the SPARC. More framing information is required in certain situaions
* such as when there are a large number of out parameters or when the callee
* must save floating point registers.
@@ -306,7 +306,7 @@ typedef struct {
typedef struct {
/*
* Using a double g0_g1 will put everything in this structure on a
* Using a double g0_g1 will put everything in this structure on a
* double word boundary which allows us to use double word loads
* and stores safely in the context switch.
*/
@@ -512,11 +512,11 @@ typedef struct {
#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
#define ISF_TPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
#ifndef ASM
/*
* This variable is contains the initialize context for the FP unit.
* It is filled in by _CPU_Initialize and copied into the task's FP
* It is filled in by _CPU_Initialize and copied into the task's FP
* context area during _CPU_Context_Initialize.
*/
@@ -555,14 +555,14 @@ SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
* long jump. The other instructions load one register with the
* trap type (a.k.a. vector) and another with the psr.
*/
typedef struct {
uint32_t mov_psr_l0; /* mov %psr, %l0 */
uint32_t sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */
uint32_t jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */
uint32_t mov_vector_l3; /* mov _vector, %l3 */
} CPU_Trap_table_entry;
/*
* This is the set of opcodes for the instructions loaded into a trap
* table entry. The routine which installs a handler is responsible
@@ -572,11 +572,11 @@ typedef struct {
* The constants following this structure are masks for the fields which
* must be filled in when the handler is installed.
*/
extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
/*
* The size of the floating point context area.
* The size of the floating point context area.
*/
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
@@ -714,7 +714,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Disable( _level ) \
(_level) = sparc_disable_interrupts()
/*
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
* This indicates the end of a critical section. The parameter
@@ -733,18 +733,18 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
* map onto the CPU in a straight fashion are undefined.
* map onto the CPU in a straight fashion are undefined.
*/
#define _CPU_ISR_Set_level( _newlevel ) \
sparc_enable_interrupts( _newlevel << 8)
uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */
/* Context handler macros */
@@ -780,7 +780,7 @@ void _CPU_Context_Initialize(
* On the SPARC, this is setting the frame pointer so GDB is happy.
* Make GDB stop unwinding at _Thread_Handler, previous register window
* Frame pointer is 0 and calling address must be a function with starting
* with a SAVE instruction. If return address is leaf-function (no SAVE)
* with a SAVE instruction. If return address is leaf-function (no SAVE)
* GDB will not look at prev reg window fp.
*
* _Thread_Handler is known to start with SAVE.
@@ -793,7 +793,7 @@ void _CPU_Context_Initialize(
/*
* This routine is responsible for somehow restarting the currently
* executing task.
* executing task.
*
* On the SPARC, this is is relatively painless but requires a small
* amount of wrapper code before using the regular restore code in
@@ -815,7 +815,7 @@ void _CPU_Context_Initialize(
* This routine initializes the FP context area passed to it to.
*
* The SPARC allows us to use the simple initialization model
* in which an "initial" FP context was saved into _CPU_Null_fp_context
* in which an "initial" FP context was saved into _CPU_Null_fp_context
* at CPU initialization and it is simply copied into the destination
* context.
*/
@@ -891,7 +891,7 @@ void _CPU_Initialize(void);
* This routine installs new_handler to be directly called from the trap
* table.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
@@ -911,14 +911,14 @@ void _CPU_ISR_install_vector(
);
#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
/*
* _CPU_Thread_Idle_body
*
* Some SPARC implementations have low power, sleep, or idle modes. This
* tries to take advantage of those models.
*/
void *_CPU_Thread_Idle_body( uintptr_t ignored );
#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
@@ -972,7 +972,7 @@ void _CPU_Context_restore_fp(
* It must be static because it is referenced indirectly.
*
* This version will work on any processor, but if you come across a better
* way for the SPARC PLEASE use it. The most common way to swap a 32-bit
* way for the SPARC PLEASE use it. The most common way to swap a 32-bit
* entity as shown below is not any more efficient on the SPARC.
*
* swap least significant two bytes with 16-bit rotate
@@ -983,18 +983,18 @@ void _CPU_Context_restore_fp(
* generic code. gcc 2.7.0 only generates about 12 instructions for the
* following code at optimization level four (i.e. -O4).
*/
static inline uint32_t CPU_swap_u32(
uint32_t value
)
{
uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff;
byte2 = (value >> 8) & 0xff;
byte1 = value & 0xff;
swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
return( swapped );
}

22
cpukit/score/cpu/sparc/rtems/score/sparc.h
View File

@@ -3,7 +3,7 @@
*/
/*
* This include file contains information pertaining to the SPARC
* This include file contains information pertaining to the SPARC
* processor family.
*
* COPYRIGHT (c) 1989-1999.
@@ -32,19 +32,19 @@ extern "C" {
*
* Currently recognized feature flags:
*
* + SPARC_HAS_FPU
* + SPARC_HAS_FPU
* 0 - no HW FPU
* 1 - has HW FPU (assumed to be compatible w/90C602)
*
* + SPARC_HAS_BITSCAN
* + SPARC_HAS_BITSCAN
* 0 - does not have scan instructions
* 1 - has scan instruction (not currently implemented)
*
*
* + SPARC_NUMBER_OF_REGISTER_WINDOWS
* 8 is the most common number supported by SPARC implementations.
* SPARC_PSR_CWP_MASK is derived from this value.
*/
/*
* Some higher end SPARCs have a bitscan instructions. It would
* be nice to take advantage of them. Right now, there is no
@@ -62,9 +62,9 @@ extern "C" {
*/
#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
/*
* This should be determined based on some soft float derived
* This should be determined based on some soft float derived
* cpp predefine but gcc does not currently give us that information.
*/
@@ -192,24 +192,24 @@ extern "C" {
/*
* Get and set the Y
*/
#define sparc_get_y( _y ) \
do { \
asm volatile( "rd %%y, %0" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
#define sparc_set_y( _y ) \
do { \
asm volatile( "wr %0, %%y" : "=r" (_y) : "0" (_y) ); \
} while ( 0 )
/*
* Manipulate the interrupt level in the psr
* Manipulate the interrupt level in the psr
*/
uint32_t sparc_disable_interrupts(void);
void sparc_enable_interrupts(uint32_t);
#define sparc_flash_interrupts( _level ) \
do { \
register uint32_t _ignored = 0; \

2
cpukit/score/cpu/sparc/rtems/score/types.h
View File

@@ -3,7 +3,7 @@
*/
/*
* This include file contains type definitions pertaining to the
* This include file contains type definitions pertaining to the
* SPARC processor family.
*
* COPYRIGHT (c) 1989-1999.

10
cpukit/telnetd/des.c
View File

@@ -71,7 +71,7 @@
#include <stdlib.h>
#define REENTRANT
/* Re-entrantify me -- all this junk needs to be in
/* Re-entrantify me -- all this junk needs to be in
* struct crypt_data to make this really reentrant... */
/* TS; not really - only the stuff in Des_Context */
@@ -127,8 +127,8 @@ static struct Des_Context single;
#define old_rawkey0 des_ctx->old_rawkey0
#define old_rawkey1 des_ctx->old_rawkey1
/* Static stuff that stays resident and doesn't change after
* being initialized, and therefore doesn't need to be made
/* Static stuff that stays resident and doesn't change after
* being initialized, and therefore doesn't need to be made
* reentrant. */
static u_char init_perm[64], final_perm[64];
static u_char m_sbox[4][4096];
@@ -241,7 +241,7 @@ static const u_char bits8[8] = { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01
static const u_int32_t *bits28, *bits24;
static int
static int
ascii_to_bin(char ch)
{
if (ch > 'z')
@@ -773,7 +773,7 @@ __des_crypt_r(const char *key, const char *setting, char *output, int sz)
*/
output[9] = '\0';
p = (u_char *)output + strlen(output);
} else
} else
#endif
{
/*

18
cpukit/telnetd/genpw.c
View File

@@ -2,19 +2,19 @@
#include <stdio.h>
#include <unistd.h>
/*
/*
* Authorship
* ----------
* This software was created by
* Till Straumann <strauman@slac.stanford.edu>, 2003-2007
* Stanford Linear Accelerator Center, Stanford University.
*
*
* Acknowledgement of sponsorship
* ------------------------------
* This software was produced by
* the Stanford Linear Accelerator Center, Stanford University,
* under Contract DE-AC03-76SFO0515 with the Department of Energy.
*
*
* Government disclaimer of liability
* ----------------------------------
* Neither the United States nor the United States Department of Energy,
@@ -23,18 +23,18 @@
* completeness, or usefulness of any data, apparatus, product, or process
* disclosed, or represents that its use would not infringe privately owned
* rights.
*
*
* Stanford disclaimer of liability
* --------------------------------
* Stanford University makes no representations or warranties, express or
* implied, nor assumes any liability for the use of this software.
*
*
* Stanford disclaimer of copyright
* --------------------------------
* Stanford University, owner of the copyright, hereby disclaims its
* copyright and all other rights in this software. Hence, anyone may
* freely use it for any purpose without restriction.
*
* freely use it for any purpose without restriction.
*
* Maintenance of notices
* ----------------------
* In the interest of clarity regarding the origin and status of this
@@ -43,9 +43,9 @@
* or distributed by the recipient and are to be affixed to any copy of
* software made or distributed by the recipient that contains a copy or
* derivative of this software.
*
*
* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
*/
*/
static void
usage(char *nm)
{

14
cpukit/telnetd/icmds.c
View File

@@ -54,11 +54,11 @@ static int main_udp(int argc,char * argv[]) {
/*+++++++++++++++++++++++++++++++++++++++++++++*/
void _rtems_telnetd_register_icmds(void) {
rtems_shell_add_cmd("inet" ,"net","inet routes" ,main_inet);
rtems_shell_add_cmd("mbuf" ,"net","mbuf stats" ,main_mbuf);
rtems_shell_add_cmd("if" ,"net","if stats" ,main_if );
rtems_shell_add_cmd("ip" ,"net","ip stats" ,main_ip );
rtems_shell_add_cmd("icmp" ,"net","icmp stats" ,main_icmp);
rtems_shell_add_cmd("tcp" ,"net","tcp stats" ,main_tcp );
rtems_shell_add_cmd("udp" ,"net","udp stats" ,main_udp );
rtems_shell_add_cmd("inet" ,"net","inet routes" ,main_inet);
rtems_shell_add_cmd("mbuf" ,"net","mbuf stats" ,main_mbuf);
rtems_shell_add_cmd("if" ,"net","if stats" ,main_if );
rtems_shell_add_cmd("ip" ,"net","ip stats" ,main_ip );
rtems_shell_add_cmd("icmp" ,"net","icmp stats" ,main_icmp);
rtems_shell_add_cmd("tcp" ,"net","tcp stats" ,main_tcp );
rtems_shell_add_cmd("udp" ,"net","udp stats" ,main_udp );
}

34
cpukit/telnetd/pty.c
View File

@@ -17,7 +17,7 @@
* is closed. Rather let 'read()' return a 0 count so
* they may cleanup. Some magic hack works around termios
* limitation.
*
*
* $Id$
*/
@@ -77,8 +77,8 @@ struct pty_tt {
int opened;
int socket;
int last_cr;
unsigned iac_mode;
unsigned char sb_buf[SB_MAX];
unsigned iac_mode;
unsigned char sb_buf[SB_MAX];
int sb_ind;
int width;
int height;
@@ -92,7 +92,7 @@ static rtems_device_major_number pty_major;
/* This procedure returns the devname for a pty slot free.
* If not slot availiable (field socket>=0)
* If not slot availiable (field socket>=0)
* then the socket argument is closed
*/
@@ -110,7 +110,7 @@ char * telnet_get_pty(int socket)
if ( !telnet_ptys ) {
return NULL;
}
for (ndx=0;ndx<rtems_telnetd_maximum_ptys;ndx++) {
if (telnet_ptys[ndx].socket<0) {
@@ -132,9 +132,9 @@ char * telnet_get_pty(int socket)
/*-----------------------------------------------------------*/
/*
* The NVT terminal is negociated in PollRead and PollWrite
* with every BYTE sendded or received.
* A litle status machine in the pty_read_byte(int minor)
*
* with every BYTE sendded or received.
* A litle status machine in the pty_read_byte(int minor)
*
*/
static const char IAC_AYT_RSP[]="\r\nAYT? Yes, RTEMS-SHELL is here\r\n";
static const char IAC_BRK_RSP[]="<*Break*>";
@@ -269,7 +269,7 @@ static int read_pty(int minor)
case IAC_WILL:
if (value==34){
send_iac(minor,IAC_DONT, 34); /*LINEMODE*/
send_iac(minor,IAC_DONT, 34); /*LINEMODE*/
send_iac(minor,IAC_DO , 1); /*ECHO */
} else if (value==31) {
send_iac(minor,IAC_DO , 31); /*NAWS */
@@ -285,7 +285,7 @@ static int read_pty(int minor)
case IAC_DO :
if (value==3) {
send_iac(minor,IAC_WILL, 3); /* GO AHEAD*/
} else if (value==1) {
} else if (value==1) {
/* ECHO */
} else {
send_iac(minor,IAC_WONT,value);
@@ -303,7 +303,7 @@ static int read_pty(int minor)
pty->iac_mode=value;
return -1;
} else {
result=value;
result=value;
if ( 0
#if 0 /* pass CRLF through - they should use termios to handle it */
|| ((value=='\n') && (pty->last_cr))
@@ -327,7 +327,7 @@ static int ptyPollWrite(int minor, const char * buf,int len) ;
static int ptyPollRead(int minor) ;
static const rtems_termios_callbacks * pty_get_termios_handlers(int polled) ;
/*-----------------------------------------------------------*/
/* Set the 'Hardware' */
/* Set the 'Hardware' */
/*-----------------------------------------------------------*/
static int
ptySetAttributes(int minor,const struct termios *t) {
@@ -339,7 +339,7 @@ ptySetAttributes(int minor,const struct termios *t) {
return 0;
}
/*-----------------------------------------------------------*/
static int
static int
ptyPollInitialize(int major,int minor,void * arg) {
rtems_libio_open_close_args_t * args = (rtems_libio_open_close_args_t*)arg;
struct termios t;
@@ -358,7 +358,7 @@ ptyPollInitialize(int major,int minor,void * arg) {
}
}
/*-----------------------------------------------------------*/
static int
static int
ptyShutdown(int major,int minor,void * arg) {
if (minor<rtems_telnetd_maximum_ptys) {
telnet_ptys[minor].opened=FALSE;
@@ -371,7 +371,7 @@ ptyShutdown(int major,int minor,void * arg) {
return 0;
}
/*-----------------------------------------------------------*/
/* Write Characters into pty device */
/* Write Characters into pty device */
/*-----------------------------------------------------------*/
static int
ptyPollWrite(int minor, const char * buf,int len) {
@@ -425,7 +425,7 @@ rtems_device_driver my_pty_initialize(
telnet_ptys = malloc( rtems_telnetd_maximum_ptys * sizeof (pty_t) );
/*
/*
* Set up ptys
*/
@@ -510,7 +510,7 @@ rtems_device_driver my_pty_open(
sc = rtems_termios_open(major,minor,arg,pty_get_termios_handlers(FALSE));
return sc;
}
/*
* Close entry point
*/

4
cpukit/telnetd/pty.h
View File

@@ -7,7 +7,7 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*
*
* $Id$
*/
@@ -24,7 +24,7 @@ extern "C" {
extern size_t rtems_pty_maximum_ptys;
/* Return the devname for a free pty slot.
* If no slot available (socket>=0)
* If no slot available (socket>=0)
* then the socket argument is closed
*/
char * rtems_pty_get(int socket);