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Switched to read/write register routines and added some basic debug

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This commit is contained in:
Joel Sherrill
1998-08-03 21:01:21 +00:00
parent 832e33c5ec
commit 7fc5d54e27
2 changed files with 463 additions and 322 deletions
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293
c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.c
View File

@@ -1,3 +1,4 @@
#define SONIC_DEBUG
/*
*******************************************************************
*******************************************************************
@@ -27,6 +28,7 @@
* 3) SVME/DMV-171 Single Board Computer Documentation Package, #805905,
* DY 4 Systems Inc., Kanata, Ontario, September, 1996.
*/
#include "sonic.h"
#include <rtems/error.h>
@@ -45,6 +47,13 @@
#include <dmv170.h>
/*
* Use the top line if you want more symbols.
*/
#define SONIC_STATIC
/* #define SONIC_STATIC static */
/*
* Number of devices supported by this driver
*/
@@ -87,6 +96,7 @@
* Packet compress output unused
* No reject on CAM match
*/
#define SONIC_DCR (DCR_DW | DCR_SBUS | DCR_TFT1 | DCR_TFT0)
#ifndef SONIC_DCR
# define SONIC_DCR (DCR_DW | DCR_TFT1 | DCR_TFT0)
#endif
@@ -146,7 +156,7 @@ struct sonic {
* ===CACHE===
* This area must be non-cacheable, guarded.
*/
volatile struct SonicRegisters *sonic;
void *sonic;
/*
* Interrupt vector
@@ -194,7 +204,7 @@ struct sonic {
unsigned long txLostCarrier;
unsigned long txRawWait;
};
static struct sonic sonic[NSONIC];
SONIC_STATIC struct sonic sonic[NSONIC];
/*
******************************************************************
@@ -204,12 +214,22 @@ static struct sonic sonic[NSONIC];
******************************************************************
*/
void sonic_write_register(
void *base,
unsigned32 regno,
unsigned32 value
);
unsigned32 sonic_read_register(
void *base,
unsigned32 regno
);
/*
* Allocate non-cacheable memory on a single 64k page.
* Very simple minded -- just keeps trying till the memory is on a single page.
*/
static void *
sonic_allocate (unsigned int nbytes)
SONIC_STATIC void * sonic_allocate (unsigned int nbytes)
{
void *p;
unsigned long a1, a2;
@@ -235,24 +255,24 @@ sonic_allocate (unsigned int nbytes)
* This is a pretty simple-minded routine. It doesn't worry
* about cleaning up mbufs, shutting down daemons, etc.
*/
static int
sonic_stop (struct iface *iface)
SONIC_STATIC int sonic_stop (struct iface *iface)
{
int i;
struct sonic *dp = &sonic[iface->dev];
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
/*
* Stop the transmitter and receiver.
*/
rp->cr = CR_HTX | CR_RXDIS;
sonic_write_register( rp, SONIC_REG_CR, CR_HTX | CR_RXDIS );
/*
* Wait for things to stop.
* For safety's sake, there is an alternate exit.
*/
i = 0;
while (rp->cr & (CR_RXEN | CR_TXP)) {
while (sonic_read_register( rp, SONIC_REG_CR ) & (CR_RXEN | CR_TXP)) {
if (++i == 10000)
break;
}
@@ -260,16 +280,16 @@ sonic_stop (struct iface *iface)
/*
* Reset the device
*/
rp->cr = CR_RST;
rp->imr = 0;
sonic_write_register( rp, SONIC_REG_CR, CR_RST );
sonic_write_register( rp, SONIC_REG_IMR, 0 );
return 0;
}
/*
* Show interface statistics
*/
static void
sonic_show (struct iface *iface)
SONIC_STATIC void sonic_show (struct iface *iface)
{
struct sonic *dp = &sonic[iface->dev];
@@ -299,11 +319,11 @@ sonic_show (struct iface *iface)
* *
******************************************************************
*/
static rtems_isr
sonic_interrupt_handler (rtems_vector_number v)
SONIC_STATIC rtems_isr sonic_interrupt_handler (rtems_vector_number v)
{
struct sonic *dp = sonic;
volatile struct SonicRegisters *rp;
void *rp;
#if (NSONIC > 1)
/*
@@ -325,9 +345,13 @@ sonic_interrupt_handler (rtems_vector_number v)
/*
* Packet received or receive buffer area exceeded?
*/
if ((rp->imr & (IMR_PRXEN | IMR_RBAEEN))
&& (rp->isr & (ISR_PKTRX | ISR_RBAE))) {
rp->imr &= ~(IMR_PRXEN | IMR_RBAEEN);
if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PRXEN | IMR_RBAEEN)) &&
(sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PKTRX | ISR_RBAE))) {
sonic_write_register(
rp,
SONIC_REG_IMR,
sonic_read_register( rp, SONIC_REG_IMR) & ~(IMR_PRXEN | IMR_RBAEEN)
);
dp->rxInterrupts++;
rtems_event_send (dp->iface->rxproc, INTERRUPT_EVENT);
}
@@ -335,9 +359,15 @@ sonic_interrupt_handler (rtems_vector_number v)
/*
* Packet started, transmitter done or transmitter error?
*/
if ((rp->imr & (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN))
&& (rp->isr & (ISR_PINT | ISR_TXDN | ISR_TXER))) {
rp->imr &= ~(IMR_PINTEN | IMR_PTXEN | IMR_TXEREN);
if ((sonic_read_register( rp, SONIC_REG_IMR ) & (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN))
&& (sonic_read_register( rp, SONIC_REG_ISR ) & (ISR_PINT | ISR_TXDN | ISR_TXER))) {
sonic_write_register(
rp,
SONIC_REG_IMR,
sonic_read_register( rp, SONIC_REG_IMR) &
~(IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
);
dp->rxInterrupts++;
dp->txInterrupts++;
rtems_event_send (dp->txWaitTid, INTERRUPT_EVENT);
}
@@ -354,8 +384,8 @@ sonic_interrupt_handler (rtems_vector_number v)
/*
* Soak up transmit descriptors that have been sent.
*/
static void
sonic_retire_tda (struct sonic *dp)
SONIC_STATIC void sonic_retire_tda (struct sonic *dp)
{
rtems_unsigned16 status;
unsigned int collisions;
@@ -380,10 +410,10 @@ sonic_retire_tda (struct sonic *dp)
link = *(dp->tdaTail->linkp);
if ((link & TDA_LINK_EOL) == 0) {
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
rp->ctda = link;
rp->cr = CR_TXP;
sonic_write_register( rp, SONIC_REG_CTDA, link );
sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
}
}
@@ -430,11 +460,11 @@ sonic_retire_tda (struct sonic *dp)
* task (most packets) or in the context of the network
* task (for ARP requests).
*/
static int
sonic_raw (struct iface *iface, struct mbuf **bpp)
SONIC_STATIC int sonic_raw (struct iface *iface, struct mbuf **bpp)
{
struct sonic *dp = &sonic[iface->dev];
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
struct mbuf *bp;
TransmitDescriptorPointer_t tdp;
volatile struct TransmitDescriptorFragLink *fp;
@@ -486,7 +516,7 @@ sonic_raw (struct iface *iface, struct mbuf **bpp)
/*
* Clear old events.
*/
rp->isr = ISR_PINT | ISR_TXDN | ISR_TXER;
sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
/*
* Wait for transmit descriptor to become available.
@@ -501,7 +531,12 @@ sonic_raw (struct iface *iface, struct mbuf **bpp)
/*
* Enable transmitter interrupts.
*/
rp->imr |= (IMR_PINTEN | IMR_PTXEN | IMR_TXEREN);
sonic_write_register(
rp,
SONIC_REG_IMR,
sonic_read_register( rp, SONIC_REG_IMR) |
(IMR_PINTEN | IMR_PTXEN | IMR_TXEREN)
);
/*
* Wait for interrupt
@@ -509,7 +544,7 @@ sonic_raw (struct iface *iface, struct mbuf **bpp)
rtems_ka9q_event_receive (INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT);
rp->isr = ISR_PINT | ISR_TXDN | ISR_TXER;
sonic_write_register( rp, SONIC_REG_ISR, ISR_PINT | ISR_TXDN | ISR_TXER );
sonic_retire_tda (dp);
}
}
@@ -568,7 +603,7 @@ sonic_raw (struct iface *iface, struct mbuf **bpp)
tdp->linkp = &fp->frag_link;
*tdp->linkp = LSW(tdp->next) | TDA_LINK_EOL;
*dp->tdaHead->linkp &= ~TDA_LINK_EOL;
rp->cr = CR_TXP;
sonic_write_register( rp, SONIC_REG_CR, CR_TXP );
dp->tdaActiveCount++;
dp->tdaHead = tdp;
@@ -591,11 +626,14 @@ sonic_raw (struct iface *iface, struct mbuf **bpp)
/*
* Wait for SONIC to hand over a Receive Descriptor.
*/
static void
sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
SONIC_STATIC void sonic_rda_wait(
struct sonic *dp,
ReceiveDescriptorPointer_t rdp
)
{
int i;
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
/*
* Wait for Receive Descriptor.
@@ -625,7 +663,7 @@ sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
* that only reception of the current packet is aborted.
* This would be more difficult to recover from....
*/
if (rp->isr & ISR_RBAE) {
if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBAE) {
/*
* One more check to soak up any Receive Descriptors
* that may already have been handed back to the driver.
@@ -636,7 +674,7 @@ sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
/*
* Check my interpretation of the SONIC manual.
*/
if (rp->cr & CR_RXEN)
if (sonic_read_register( rp, SONIC_REG_CR ) & CR_RXEN)
rtems_panic ("SONIC RBAE/RXEN");
/*
@@ -656,22 +694,30 @@ sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
* reuse the receive buffer holding the giant packet.
*/
for (i = 0 ; i < 2 ; i++) {
if (rp->rrp == rp->rsa)
rp->rrp = rp->rea;
rp->rrp -= sizeof (ReceiveResource_t);
if (sonic_read_register( rp, SONIC_REG_RRP ) == sonic_read_register( rp, SONIC_REG_RSA ))
sonic_write_register(
rp,
SONIC_REG_RRP,
sonic_read_register( rp, SONIC_REG_REA )
);
sonic_write_register(
rp,
SONIC_REG_RRP,
sonic_read_register(rp, SONIC_REG_RRP) - sizeof(ReceiveResource_t)
);
}
/*
* Restart reception
*/
rp->isr = ISR_RBAE;
rp->cr = CR_RXEN;
sonic_write_register( rp, SONIC_REG_ISR, ISR_RBAE );
sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
}
/*
* Clear old packet-received events.
*/
rp->isr = ISR_PKTRX;
sonic_write_register( rp, SONIC_REG_ISR, ISR_PKTRX );
/*
* Has Receive Descriptor become available?
@@ -682,7 +728,11 @@ sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
/*
* Enable interrupts.
*/
rp->imr |= IMR_PRXEN | IMR_RBAEEN;
sonic_write_register(
rp,
SONIC_REG_IMR,
sonic_read_register( rp, SONIC_REG_IMR) | (IMR_PRXEN | IMR_RBAEEN)
);
/*
* Wait for interrupt.
@@ -696,12 +746,12 @@ sonic_rda_wait (struct sonic *dp, ReceiveDescriptorPointer_t rdp)
/*
* SCC reader task
*/
static void
sonic_rx (int dev, void *p1, void *p2)
SONIC_STATIC void sonic_rx (int dev, void *p1, void *p2)
{
struct iface *iface = (struct iface *)p1;
struct sonic *dp = (struct sonic *)p2;
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
struct mbuf *bp;
rtems_unsigned16 status;
ReceiveDescriptor_t *rda;
@@ -743,16 +793,16 @@ sonic_rx (int dev, void *p1, void *p2)
/*
* Set up remaining Receive Resource Area pointers
*/
rp->rsa = LSW(dp->rsa);
rp->rrp = LSW(dp->rsa);
rp->rea = LSW(rea);
rp->rwp = LSW(rea);
sonic_write_register( rp, SONIC_REG_RSA, LSW(dp->rsa) );
sonic_write_register( rp, SONIC_REG_RRP, LSW(dp->rsa) );
sonic_write_register( rp, SONIC_REG_REA, LSW(rea) );
sonic_write_register( rp, SONIC_REG_RWP, LSW(rea) );
/*
* Set End Of Buffer Count register to the value recommended
* in Note 1 of Section 3.4.4.4 of the SONIC data sheet.
*/
rp->eobc = RBUF_WC - 2;
sonic_write_register( rp, SONIC_REG_EOBC, RBUF_WC - 2 );
/*
* Set up circular linked list in Receive Descriptor Area.
@@ -775,15 +825,15 @@ sonic_rx (int dev, void *p1, void *p2)
ordp->link = LSW(rdp);
}
ordp->link |= RDA_LINK_EOL;
rp->urda = MSW(rdp);
rp->crda = LSW(rdp);
sonic_write_register( rp, SONIC_REG_URDA, MSW(rdp) );
sonic_write_register( rp, SONIC_REG_CRDA, LSW(rdp) );
/*
* Start the receiver
*/
oldMissedTally = rp->mpt;
rp->cr = CR_RRRA;
rp->cr = CR_RXEN;
oldMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
sonic_write_register( rp, SONIC_REG_CR, CR_RRRA );
sonic_write_register( rp, SONIC_REG_CR, CR_RXEN );
/*
* Input packet handling loop
@@ -860,13 +910,13 @@ sonic_rx (int dev, void *p1, void *p2)
rwp++;
if (rwp == rea)
rwp = dp->rsa;
rp->rwp = LSW(rwp);
sonic_write_register( rp, SONIC_REG_RWP , LSW(rwp) );
/*
* Tell the SONIC to reread the RRA.
*/
if (rp->isr & ISR_RBE)
rp->isr = ISR_RBE;
if (sonic_read_register( rp, SONIC_REG_ISR ) & ISR_RBE)
sonic_write_register( rp, SONIC_REG_ISR, ISR_RBE );
}
else {
if (status & RDA_STATUS_COL)
@@ -880,7 +930,7 @@ sonic_rx (int dev, void *p1, void *p2)
/*
* Count missed packets
*/
newMissedTally = rp->mpt;
newMissedTally = sonic_read_register( rp, SONIC_REG_MPT );
if (newMissedTally != oldMissedTally) {
dp->rxMissed += (newMissedTally - oldMissedTally) & 0xFFFF;
newMissedTally = oldMissedTally;
@@ -908,20 +958,22 @@ sonic_rx (int dev, void *p1, void *p2)
/*
* Initialize the SONIC hardware
*/
static void
sonic_initialize_hardware (struct sonic *dp, int broadcastFlag)
SONIC_STATIC void sonic_initialize_hardware(
struct sonic *dp,
int broadcastFlag
)
{
volatile struct SonicRegisters *rp = dp->sonic;
void *rp = dp->sonic;
int i;
unsigned char *hwaddr;
rtems_status_code sc;
rtems_isr_entry old_handler;
TransmitDescriptorPointer_t otdp, tdp;
struct CamDescriptor{
rtems_unsigned32 cep;
rtems_unsigned32 cap0;
rtems_unsigned32 cap1;
rtems_unsigned32 cap2;
rtems_unsigned32 cep; /* CAM Entry Pointer */
rtems_unsigned32 cap2; /* CAM Address Port 0 xx-xx-xx-xx-YY-YY */
rtems_unsigned32 cap1; /* CAM Address Port 1 xx-xx-YY-YY-xxxx */
rtems_unsigned32 cap0; /* CAM Address Port 2 YY-YY-xx-xx-xx-xx */
rtems_unsigned32 ce;
};
volatile struct CamDescriptor *cdp;
@@ -929,25 +981,32 @@ sonic_initialize_hardware (struct sonic *dp, int broadcastFlag)
/*
* Issue a software reset if necessary.
*/
if ((rp->cr & CR_RST) == 0)
rp->cr = CR_RST;
if ((sonic_read_register( rp, SONIC_REG_CR ) & CR_RST) == 0)
sonic_write_register( rp, SONIC_REG_CR, CR_RST );
/*
* Set up data configuration registers.
*/
rp->dcr = SONIC_DCR;
rp->dcr2 = SONIC_DC2;
sonic_write_register( rp, SONIC_REG_DCR, SONIC_DCR );
/* XXX can not find documentation with this register
sonic_write_register( rp, SONIC_REG_DCR2, SONIC_DC2 );
*/
/*
* Mask all interrupts
*/
sonic_write_register( rp, SONIC_REG_IMR, 0x3fff );
/*
* Clear outstanding interrupts.
*/
sonic_write_register( rp, SONIC_REG_ISR, 0x7FFF );
/*
* Remove device reset
*/
rp->cr = 0;
sonic_write_register( rp, SONIC_REG_CR, 0 );
/*
* Clear outstanding interrupts.
*/
rp->isr = 0x7FFF;
/*
* Allocate the receive resource area.
* In accordance with National Application Note 746, make the
@@ -956,7 +1015,10 @@ sonic_initialize_hardware (struct sonic *dp, int broadcastFlag)
* area big enough to hold the CAM descriptor area.
*/
dp->rsa = sonic_allocate ((dp->rdaCount + RRA_EXTRA_COUNT) * sizeof *dp->rsa);
rp->urra = MSW(dp->rsa);
#ifdef SONIC_DEBUG
printf( "rsa area = %p\n", dp->rsa );
#endif
sonic_write_register( rp, SONIC_REG_URRA , MSW(dp->rsa) );
/*
* Set up the SONIC CAM with our hardware address.
@@ -969,25 +1031,28 @@ sonic_initialize_hardware (struct sonic *dp, int broadcastFlag)
cdp->cap1 = hwaddr[2] << 8 | hwaddr[3];
cdp->cap0 = hwaddr[4] << 8 | hwaddr[5];
cdp->ce = 0x0001; /* Enable first entry in CAM */
rp->cdc = 1; /* One entry in CDA */
rp->cdp = LSW(cdp);
rp->cr = CR_LCAM; /* Load the CAM */
while (rp->cr & CR_LCAM)
sonic_write_register( rp, SONIC_REG_CDC, 1 ); /* One entry in CDA */
sonic_write_register( rp, SONIC_REG_CDP, LSW(cdp) );
sonic_write_register( rp, SONIC_REG_CR, CR_LCAM ); /* Load the CAM */
while (sonic_read_register( rp, SONIC_REG_CR ) & CR_LCAM)
continue;
/*
* Verify that CAM was properly loaded.
*/
rp->cep = 0; /* Select first entry in CAM */
if ((rp->cap2 != cdp->cap2)
|| (rp->cap1 != cdp->cap1)
|| (rp->cap0 != cdp->cap0)
|| (rp->ce != cdp->ce)) {
sonic_write_register( rp, SONIC_REG_CEP, 0 ); /* Select first entry in CAM */
if ((sonic_read_register( rp, SONIC_REG_CAP2 ) != cdp->cap2)
|| (sonic_read_register( rp, SONIC_REG_CAP1 ) != cdp->cap1)
|| (sonic_read_register( rp, SONIC_REG_CAP0 ) != cdp->cap0)
|| (sonic_read_register( rp, SONIC_REG_CE ) != cdp->ce)) {
printf ("Failed to load Ethernet address into SONIC CAM.\n"
" Wrote %04x%04x%04x - %#x\n"
" Read %04x%04x%04x - %#x\n",
cdp->cap2, cdp->cap1, cdp->cap0, cdp->ce,
rp->cap2, rp->cap1, rp->cap0, rp->ce);
sonic_read_register( rp, SONIC_REG_CAP2 ),
sonic_read_register( rp, SONIC_REG_CAP1 ),
sonic_read_register( rp, SONIC_REG_CAP0 ),
sonic_read_register( rp, SONIC_REG_CE ));
rtems_panic ("SONIC LCAM");
}
@@ -1013,21 +1078,21 @@ sonic_initialize_hardware (struct sonic *dp, int broadcastFlag)
}
dp->tdaHead = otdp;
dp->tdaHead->linkp = &dp->tdaHead->frag[0].frag_link;
rp->utda = MSW(dp->tdaTail);
rp->ctda = LSW(dp->tdaTail);
sonic_write_register( rp, SONIC_REG_UTDA, MSW(dp->tdaTail) );
sonic_write_register( rp, SONIC_REG_CTDA, LSW(dp->tdaTail) );
/*
* Enable/disable reception of broadcast packets
*/
if (broadcastFlag)
rp->rcr = RCR_BRD;
sonic_write_register( rp, SONIC_REG_RCR, RCR_BRD );
else
rp->rcr = 0;
sonic_write_register( rp, SONIC_REG_RCR, 0 );
/*
* Attach SONIC interrupt handler
*/
rp->imr = 0;
sonic_write_register( rp, SONIC_REG_IMR, 0 );
sc = rtems_interrupt_catch (sonic_interrupt_handler, dp->vector, &old_handler);
if (sc != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach SONIC interrupt handler: %s\n",
@@ -1180,3 +1245,39 @@ rtems_ka9q_driver_attach (int argc, char *argv[], void *p)
free (cp);
return 0;
}
#ifdef SONIC_DEBUG
#include <stdio.h>
#endif
void sonic_write_register(
void *base,
unsigned32 regno,
unsigned32 value
)
{
volatile unsigned32 *p = base;
#ifdef SONIC_DEBUG
printf( "Write 0x%04x to 0x%02x\n", value, regno );
fflush( stdout );
#endif
p[regno] = value;
}
unsigned32 sonic_read_register(
void *base,
unsigned32 regno
)
{
volatile unsigned32 *p = base;
unsigned32 value;
value = p[regno];
#ifdef SONIC_DEBUG
printf( "Read 0x%04x from 0x%02x\n", value, regno );
fflush( stdout );
#endif
return value;
}

492
c/src/lib/libbsp/powerpc/dmv177/sonic/sonic.h
View File

@@ -26,198 +26,238 @@
* *
******************************************************************
*/
#define SONIC_REG_CR 0x00 /* Command */
#define SONIC_REG_DCR 0x01 /* Data configuration */
#define SONIC_REG_RCR 0x02 /* Receive control */
#define SONIC_REG_TCR 0x03 /* Transmit control */
#define SONIC_REG_IMR 0x04 /* Interrupt mask */
#define SONIC_REG_ISR 0x05 /* Interrupt status */
#define SONIC_REG_UTDA 0x06 /* Upper transmit descriptor address */
#define SONIC_REG_CTDA 0x07 /* Current transmit descriptor address */
#define SONIC_REG_URDA 0x0D /* Upper receive descriptor address */
#define SONIC_REG_CRDA 0x0E /* Current receive descriptor address */
#define SONIC_REG_EOBC 0x13 /* End of buffer word count */
#define SONIC_REG_URRA 0x14 /* Upper receive resource */
#define SONIC_REG_RSA 0x15 /* Resource start address */
#define SONIC_REG_REA 0x16 /* Resource end address */
#define SONIC_REG_RRP 0x17 /* Resouce read pointer */
#define SONIC_REG_RWP 0x18 /* Resouce write pointer */
#define SONIC_REG_CEP 0x21 /* CAM entry pointer */
#define SONIC_REG_CAP2 0x22 /* CAM address port 2 */
#define SONIC_REG_CAP1 0x23 /* CAM address port 1 */
#define SONIC_REG_CAP0 0x24 /* CAM address port 0 */
#define SONIC_REG_CE 0x25 /* CAM enable */
#define SONIC_REG_CDP 0x26 /* CAM descriptor pointer */
#define SONIC_REG_CDC 0x27 /* CAM descriptor count */
#define SONIC_REG_SR 0x28 /* Silicon revision */
#define SONIC_REG_WT0 0x29 /* Watchdog timer 0 */
#define SONIC_REG_WT1 0x2A /* Watchdog timer 1 */
#define SONIC_REG_RSC 0x2B /* Receive sequence counter */
#define SONIC_REG_CRCT 0x2C /* CRC error tally */
#define SONIC_REG_FAET 0x2D /* FAE tally */
#define SONIC_REG_MPT 0x2E /* Missed packet tally */
#define SONIC_REG_MDT 0x2F /* TX Maximum Deferral */
#define SONIC_REG_DCR2 0x3F /* Data configuration 2 */
#if 0
struct SonicRegisters {
/*
* Command and status registers
*/
rtems_unsigned32 cr; /* Command */
rtems_unsigned32 dcr; /* Data configuration */
rtems_unsigned32 rcr; /* Receive control */
rtems_unsigned32 tcr; /* Transmit control */
rtems_unsigned32 imr; /* Interrupt mask */
rtems_unsigned32 isr; /* Interrupt status */
/*
* Command and status registers
*/
rtems_unsigned32 cr; /* 0x00 - Command */
rtems_unsigned32 dcr; /* 0x01 - Data configuration */
rtems_unsigned32 rcr; /* 0x02 - Receive control */
rtems_unsigned32 tcr; /* 0x03 - Transmit control */
rtems_unsigned32 imr; /* 0x04 - Interrupt mask */
rtems_unsigned32 isr; /* 0x05 - Interrupt status */
/*
* Transmit registers
*/
rtems_unsigned32 utda; /* Upper transmit descriptor address */
rtems_unsigned32 ctda; /* Current transmit descriptor address */
/*
* Transmit registers
*/
rtems_unsigned32 utda; /* 0x06 - Upper transmit descriptor address */
rtems_unsigned32 ctda; /* 0x07 - Current transmit descriptor address */
/*
* Receive registers
*/
rtems_unsigned32 pad0[5];
rtems_unsigned32 urda; /* Upper receive descriptor address */
rtems_unsigned32 crda; /* Current receive descriptor address */
rtems_unsigned32 pad1[4];
rtems_unsigned32 eobc; /* End of buffer word count */
rtems_unsigned32 urra; /* Upper receive resource */
rtems_unsigned32 rsa; /* Resource start address */
rtems_unsigned32 rea; /* Resource end address */
rtems_unsigned32 rrp; /* Resouce read pointer */
rtems_unsigned32 rwp; /* Resouce read pointer */
/*
* Receive registers
*/
rtems_unsigned32 pad0[5]; /* 0x08 - 0x0C */
rtems_unsigned32 urda; /* 0x0D - Upper receive descriptor address */
rtems_unsigned32 crda; /* 0x0E - Current receive descriptor address */
rtems_unsigned32 pad1[4]; /* 0x0F - 0x12 */
rtems_unsigned32 eobc; /* 0x13 - End of buffer word count */
rtems_unsigned32 urra; /* 0x14 - Upper receive resource */
rtems_unsigned32 rsa; /* 0x15 - Resource start address */
rtems_unsigned32 rea; /* 0x16 - Resource end address */
rtems_unsigned32 rrp; /* 0x17 - Resouce read pointer */
rtems_unsigned32 rwp; /* 0x18 - Resouce write pointer */
/*
* Content-addressable memory registers
*/
rtems_unsigned32 pad2[8];
rtems_unsigned32 cep; /* CAM entry pointer */
rtems_unsigned32 cap2; /* CAM address port 2 */
rtems_unsigned32 cap1; /* CAM address port 1 */
rtems_unsigned32 cap0; /* CAM address port 0 */
rtems_unsigned32 ce; /* CAM enable */
rtems_unsigned32 cdp; /* CAM descriptor pointer */
rtems_unsigned32 cdc; /* CAM descriptor count */
/*
* Content-addressable memory registers
*/
rtems_unsigned32 pad2[8]; /* 0x19 - 0x20 */
rtems_unsigned32 cep; /* 0x21 - CAM entry pointer */
rtems_unsigned32 cap2; /* 0x22 - CAM address port 2 */
rtems_unsigned32 cap1; /* 0x23 - CAM address port 1 */
rtems_unsigned32 cap0; /* 0x24 - CAM address port 0 */
rtems_unsigned32 ce; /* 0x25 - CAM enable */
rtems_unsigned32 cdp; /* 0x26 - CAM descriptor pointer */
rtems_unsigned32 cdc; /* 0x27 - CAM descriptor count */
/*
* Silicon revision
*/
rtems_unsigned32 sr; /* Silicon revision */
/*
* Silicon revision
*/
rtems_unsigned32 sr; /* 0x28 - Silicon revision */
/*
* Watchdog counters
*/
rtems_unsigned32 wt0; /* Watchdog timer 0 */
rtems_unsigned32 wt1; /* Watchdog timer 1 */
/*
* Watchdog counters
*/
rtems_unsigned32 wt0; /* 0x29 - Watchdog timer 0 */
rtems_unsigned32 wt1; /* 0x2A - Watchdog timer 1 */
/*
* Another receive register
*/
rtems_unsigned32 rsc; /* Receive sequence counter */
/*
* Another receive register
*/
rtems_unsigned32 rsc; /* 0x2B - Receive sequence counter */
/*
* Tally counters
*/
rtems_unsigned32 crct; /* CRC error tally */
rtems_unsigned32 faet; /* FAE tally */
rtems_unsigned32 mpt; /* Missed packet tally */
/*
* Tally counters
*/
rtems_unsigned32 crct; /* 0x2C - CRC error tally */
rtems_unsigned32 faet; /* 0x2D - FAE tally */
rtems_unsigned32 mpt; /* 0x2E - Missed packet tally */
/*
* Another command and status register
*/
rtems_unsigned32 pad3[16];
rtems_unsigned32 dcr2; /* Data configuration 2 */
/*
* Another Transmitter register
*/
rtems_unsigned32 mdt; /* 0x2F - TX Maximum Deferral */
/*
* Another command and status register
*/
rtems_unsigned32 pad3[15]; /* 0x30 - 0x3E */
rtems_unsigned32 dcr2; /* 0x3F - Data configuration 2 */
};
#endif
/*
* Command register
*/
#define CR_LCAM 0x0200
#define CR_RRRA 0x0100
#define CR_RST 0x0080
#define CR_ST 0x0020
#define CR_STP 0x0010
#define CR_RXEN 0x0008
#define CR_RXDIS 0x0004
#define CR_TXP 0x0002
#define CR_HTX 0x0001
#define CR_LCAM 0x0200
#define CR_RRRA 0x0100
#define CR_RST 0x0080
#define CR_ST 0x0020
#define CR_STP 0x0010
#define CR_RXEN 0x0008
#define CR_RXDIS 0x0004
#define CR_TXP 0x0002
#define CR_HTX 0x0001
/*
* Data configuration register
*/
#define DCR_EXBUS 0x8000
#define DCR_LBR 0x2000
#define DCR_PO1 0x1000
#define DCR_PO0 0x0800
#define DCR_SBUS 0x0400
#define DCR_USR1 0x0200
#define DCR_USR0 0x0100
#define DCR_WC1 0x0080
#define DCR_WC0 0x0040
#define DCR_DW 0x0020
#define DCR_BMS 0x0010
#define DCR_RFT1 0x0008
#define DCR_RFT0 0x0004
#define DCR_TFT1 0x0002
#define DCR_TFT0 0x0001
#define DCR_EXBUS 0x8000
#define DCR_LBR 0x2000
#define DCR_PO1 0x1000
#define DCR_PO0 0x0800
#define DCR_SBUS 0x0400
#define DCR_USR1 0x0200
#define DCR_USR0 0x0100
#define DCR_WC1 0x0080
#define DCR_WC0 0x0040
#define DCR_DW 0x0020
#define DCR_BMS 0x0010
#define DCR_RFT1 0x0008
#define DCR_RFT0 0x0004
#define DCR_TFT1 0x0002
#define DCR_TFT0 0x0001
/*
* Receive control register
*/
#define RCR_ERR 0x8000
#define RCR_RNT 0x4000
#define RCR_BRD 0x2000
#define RCR_PRO 0x1000
#define RCR_AMC 0x0800
#define RCR_LB1 0x0400
#define RCR_LB0 0x0200
#define RCR_MC 0x0100
#define RCR_BC 0x0080
#define RCR_LPKT 0x0040
#define RCR_CRS 0x0020
#define RCR_COL 0x0010
#define RCR_CRCR 0x0008
#define RCR_FAER 0x0004
#define RCR_LBK 0x0002
#define RCR_PRX 0x0001
#define RCR_ERR 0x8000
#define RCR_RNT 0x4000
#define RCR_BRD 0x2000
#define RCR_PRO 0x1000
#define RCR_AMC 0x0800
#define RCR_LB1 0x0400
#define RCR_LB0 0x0200
#define RCR_MC 0x0100
#define RCR_BC 0x0080
#define RCR_LPKT 0x0040
#define RCR_CRS 0x0020
#define RCR_COL 0x0010
#define RCR_CRCR 0x0008
#define RCR_FAER 0x0004
#define RCR_LBK 0x0002
#define RCR_PRX 0x0001
/*
* Transmit control register
*/
#define TCR_PINT 0x8000
#define TCR_POWC 0x4000
#define TCR_CRCI 0x2000
#define TCR_EXDIS 0x1000
#define TCR_EXD 0x0400
#define TCR_DEF 0x0200
#define TCR_NCRS 0x0100
#define TCR_CRSL 0x0080
#define TCR_EXC 0x0040
#define TCR_OWC 0x0020
#define TCR_PMB 0x0008
#define TCR_FU 0x0004
#define TCR_BCM 0x0002
#define TCR_PTX 0x0001
#define TCR_PINT 0x8000
#define TCR_POWC 0x4000
#define TCR_CRCI 0x2000
#define TCR_EXDIS 0x1000
#define TCR_EXD 0x0400
#define TCR_DEF 0x0200
#define TCR_NCRS 0x0100
#define TCR_CRSL 0x0080
#define TCR_EXC 0x0040
#define TCR_OWC 0x0020
#define TCR_PMB 0x0008
#define TCR_FU 0x0004
#define TCR_BCM 0x0002
#define TCR_PTX 0x0001
/*
* Interrupt mask register
*/
#define IMR_BREN 0x4000
#define IMR_HBLEN 0x2000
#define IMR_LCDEN 0x1000
#define IMR_PINTEN 0x0800
#define IMR_PRXEN 0x0400
#define IMR_PTXEN 0x0200
#define IMR_TXEREN 0x0100
#define IMR_TCEN 0x0080
#define IMR_RDEEN 0x0040
#define IMR_RBEEN 0x0020
#define IMR_RBAEEN 0x0010
#define IMR_CRCEN 0x0008
#define IMR_FAEEN 0x0004
#define IMR_MPEN 0x0002
#define IMR_RFOEN 0x0001
#define IMR_BREN 0x4000
#define IMR_HBLEN 0x2000
#define IMR_LCDEN 0x1000
#define IMR_PINTEN 0x0800
#define IMR_PRXEN 0x0400
#define IMR_PTXEN 0x0200
#define IMR_TXEREN 0x0100
#define IMR_TCEN 0x0080
#define IMR_RDEEN 0x0040
#define IMR_RBEEN 0x0020
#define IMR_RBAEEN 0x0010
#define IMR_CRCEN 0x0008
#define IMR_FAEEN 0x0004
#define IMR_MPEN 0x0002
#define IMR_RFOEN 0x0001
/*
* Interrupt status register
*/
#define ISR_BR 0x4000
#define ISR_HBL 0x2000
#define ISR_LCD 0x1000
#define ISR_PINT 0x0800
#define ISR_PKTRX 0x0400
#define ISR_TXDN 0x0200
#define ISR_TXER 0x0100
#define ISR_TC 0x0080
#define ISR_RDE 0x0040
#define ISR_RBE 0x0020
#define ISR_RBAE 0x0010
#define ISR_CRC 0x0008
#define ISR_FAE 0x0004
#define ISR_MP 0x0002
#define ISR_RFO 0x0001
#define ISR_BR 0x4000
#define ISR_HBL 0x2000
#define ISR_LCD 0x1000
#define ISR_PINT 0x0800
#define ISR_PKTRX 0x0400
#define ISR_TXDN 0x0200
#define ISR_TXER 0x0100
#define ISR_TC 0x0080
#define ISR_RDE 0x0040
#define ISR_RBE 0x0020
#define ISR_RBAE 0x0010
#define ISR_CRC 0x0008
#define ISR_FAE 0x0004
#define ISR_MP 0x0002
#define ISR_RFO 0x0001
/*
* Data configuration register 2
*/
#define DCR2_EXPO3 0x8000
#define DCR2_EXPO2 0x4000
#define DCR2_EXPO1 0x2000
#define DCR2_EXPO0 0x1000
#define DCR2_PH 0x0010
#define DCR2_PCM 0x0004
#define DCR2_PCNM 0x0002
#define DCR2_RJCM 0x0001
#define DCR2_EXPO3 0x8000
#define DCR2_EXPO2 0x4000
#define DCR2_EXPO1 0x2000
#define DCR2_EXPO0 0x1000
#define DCR2_PH 0x0010
#define DCR2_PCM 0x0004
#define DCR2_PCNM 0x0002
#define DCR2_RJCM 0x0001
/*
******************************************************************
@@ -233,34 +273,34 @@ struct SonicRegisters {
* Statically reserve space for up to MAXIMUM_FRAGS_PER_PACKET fragments
* per descriptor.
*/
#define MAXIMUM_FRAGS_PER_DESCRIPTOR 6
#define MAXIMUM_FRAGS_PER_DESCRIPTOR 6
struct TransmitDescriptor {
rtems_unsigned32 status;
rtems_unsigned32 pkt_config;
rtems_unsigned32 pkt_size;
rtems_unsigned32 frag_count;
rtems_unsigned32 status;
rtems_unsigned32 pkt_config;
rtems_unsigned32 pkt_size;
rtems_unsigned32 frag_count;
/*
* Packet fragment pointers
*/
struct TransmitDescriptorFragLink {
rtems_unsigned32 frag_lsw; /* LSW of fragment address */
#define frag_link frag_lsw
rtems_unsigned32 frag_msw; /* MSW of fragment address */
rtems_unsigned32 frag_size;
} frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
/*
* Packet fragment pointers
*/
struct TransmitDescriptorFragLink {
rtems_unsigned32 frag_lsw; /* LSW of fragment address */
#define frag_link frag_lsw
rtems_unsigned32 frag_msw; /* MSW of fragment address */
rtems_unsigned32 frag_size;
} frag[MAXIMUM_FRAGS_PER_DESCRIPTOR];
/*
* Space for link if all fragment pointers are used.
*/
rtems_unsigned32 link_pad;
/*
* Space for link if all fragment pointers are used.
*/
rtems_unsigned32 link_pad;
/*
* Extra RTEMS/KA9Q stuff
*/
struct TransmitDescriptor *next; /* Circularly-linked list */
struct mbuf *mbufp; /* First mbuf in packet */
volatile rtems_unsigned32 *linkp; /* Pointer to un[xxx].link */
/*
* Extra RTEMS/KA9Q stuff
*/
struct TransmitDescriptor *next; /* Circularly-linked list */
struct mbuf *mbufp; /* First mbuf in packet */
volatile rtems_unsigned32 *linkp; /* Pointer to un[xxx].link */
};
typedef struct TransmitDescriptor TransmitDescriptor_t;
typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
@@ -270,26 +310,26 @@ typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
* For standard Ethernet transmission, all bits in the transmit
* configuration field are set to 0.
*/
#define TDA_CONFIG_PINT 0x8000
#define TDA_CONFIG_POWC 0x4000
#define TDA_CONFIG_CRCI 0x2000
#define TDA_CONFIG_EXDIS 0x1000
#define TDA_CONFIG_PINT 0x8000
#define TDA_CONFIG_POWC 0x4000
#define TDA_CONFIG_CRCI 0x2000
#define TDA_CONFIG_EXDIS 0x1000
/*
* Transmit status
*/
#define TDA_STATUS_COLLISION_MASK 0xF800
#define TDA_STATUS_COLLISION_SHIFT 11
#define TDA_STATUS_EXD 0x0400
#define TDA_STATUS_DEF 0x0200
#define TDA_STATUS_NCRS 0x0100
#define TDA_STATUS_CRSL 0x0080
#define TDA_STATUS_EXC 0x0040
#define TDA_STATUS_OWC 0x0020
#define TDA_STATUS_PMB 0x0008
#define TDA_STATUS_FU 0x0004
#define TDA_STATUS_BCM 0x0002
#define TDA_STATUS_PTX 0x0001
#define TDA_STATUS_COLLISION_MASK 0xF800
#define TDA_STATUS_COLLISION_SHIFT 11
#define TDA_STATUS_EXD 0x0400
#define TDA_STATUS_DEF 0x0200
#define TDA_STATUS_NCRS 0x0100
#define TDA_STATUS_CRSL 0x0080
#define TDA_STATUS_EXC 0x0040
#define TDA_STATUS_OWC 0x0020
#define TDA_STATUS_PMB 0x0008
#define TDA_STATUS_FU 0x0004
#define TDA_STATUS_BCM 0x0002
#define TDA_STATUS_PTX 0x0001
#define TDA_LINK_EOL 0x1
@@ -310,10 +350,10 @@ typedef volatile TransmitDescriptor_t *TransmitDescriptorPointer_t;
* receive resource entry corresponds to one correctly-received packet.
*/
struct ReceiveResource {
rtems_unsigned32 buff_ptr_lsw; /* LSW of RBA address */
rtems_unsigned32 buff_ptr_msw; /* MSW of RBA address */
rtems_unsigned32 buff_wc_lsw; /* LSW of RBA size (16-bit words) */
rtems_unsigned32 buff_wc_msw; /* MSW of RBA size (16-bit words) */
rtems_unsigned32 buff_ptr_lsw; /* LSW of RBA address */
rtems_unsigned32 buff_ptr_msw; /* MSW of RBA address */
rtems_unsigned32 buff_wc_lsw; /* LSW of RBA size (16-bit words) */
rtems_unsigned32 buff_wc_msw; /* MSW of RBA size (16-bit words) */
};
typedef struct ReceiveResource ReceiveResource_t;
typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
@@ -323,18 +363,18 @@ typedef volatile ReceiveResource_t *ReceiveResourcePointer_t;
* There is one receive descriptor for each packet received.
*/
struct ReceiveDescriptor {
rtems_unsigned32 status;
rtems_unsigned32 byte_count;
rtems_unsigned32 pkt_lsw; /* LSW of packet address */
rtems_unsigned32 pkt_msw; /* MSW of packet address */
rtems_unsigned32 seq_no;
rtems_unsigned32 link;
rtems_unsigned32 in_use;
rtems_unsigned32 status;
rtems_unsigned32 byte_count;
rtems_unsigned32 pkt_lsw; /* LSW of packet address */
rtems_unsigned32 pkt_msw; /* MSW of packet address */
rtems_unsigned32 seq_no;
rtems_unsigned32 link;
rtems_unsigned32 in_use;
/*
* Extra RTEMS/KA9Q stuff
*/
struct ReceiveDescriptor *next; /* Circularly-linked list */
/*
* Extra RTEMS/KA9Q stuff
*/
struct ReceiveDescriptor *next; /* Circularly-linked list */
};
typedef struct ReceiveDescriptor ReceiveDescriptor_t;
typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
@@ -342,23 +382,23 @@ typedef volatile ReceiveDescriptor_t *ReceiveDescriptorPointer_t;
/*
* Receive status
*/
#define RDA_STATUS_ERR 0x8800
#define RDA_STATUS_RNT 0x4000
#define RDA_STATUS_BRD 0x2000
#define RDA_STATUS_PRO 0x1000
#define RDA_STATUS_AMC 0x0800
#define RDA_STATUS_LB1 0x0400
#define RDA_STATUS_LB0 0x0200
#define RDA_STATUS_MC 0x0100
#define RDA_STATUS_BC 0x0080
#define RDA_STATUS_LPKT 0x0040
#define RDA_STATUS_CRS 0x0020
#define RDA_STATUS_COL 0x0010
#define RDA_STATUS_CRCR 0x0008
#define RDA_STATUS_FAER 0x0004
#define RDA_STATUS_LBK 0x0002
#define RDA_STATUS_PRX 0x0001
#define RDA_STATUS_ERR 0x8800
#define RDA_STATUS_RNT 0x4000
#define RDA_STATUS_BRD 0x2000
#define RDA_STATUS_PRO 0x1000
#define RDA_STATUS_AMC 0x0800
#define RDA_STATUS_LB1 0x0400
#define RDA_STATUS_LB0 0x0200
#define RDA_STATUS_MC 0x0100
#define RDA_STATUS_BC 0x0080
#define RDA_STATUS_LPKT 0x0040
#define RDA_STATUS_CRS 0x0020
#define RDA_STATUS_COL 0x0010
#define RDA_STATUS_CRCR 0x0008
#define RDA_STATUS_FAER 0x0004
#define RDA_STATUS_LBK 0x0002
#define RDA_STATUS_PRX 0x0001
#define RDA_LINK_EOL 0x1
#endif /* _SONIC_DP83932_ */