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2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* shared/bootloader/exception.S, shared/bootloader/misc.c,
	shared/bootloader/mm.c, shared/console/polled_io.c,
	shared/startup/probeMemEnd.c: Update due to API changes.
This commit is contained in:
Sebastian Huber
2011-08-24 09:48:56 +00:00
parent 1d367a49df
commit 7e85bfbef4
6 changed files with 18 additions and 16 deletions
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6
c/src/lib/libbsp/powerpc/ChangeLog
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@@ -1,3 +1,9 @@
2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* shared/bootloader/exception.S, shared/bootloader/misc.c,
shared/bootloader/mm.c, shared/console/polled_io.c,
shared/startup/probeMemEnd.c: Update due to API changes.
2011-07-27 Till Straumann <strauman@slac.stanford.edu> 2011-07-27 Till Straumann <strauman@slac.stanford.edu>
* shared/start/start.S, shared/start/preload.S: * shared/start/start.S, shared/start/preload.S:

10
c/src/lib/libbsp/powerpc/shared/bootloader/exception.S
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@@ -151,7 +151,7 @@ tlb_handlers:
#ifdef ASSUME_REF_SET #ifdef ASSUME_REF_SET
andi. r3,r1,8 # check for guarded memory andi. r3,r1,8 # check for guarded memory
bne- 5f bne- 5f
mtspr RPA,r1 mtspr PPC_RPA,r1
mfsrr1 r3 mfsrr1 r3
tlbli r0 tlbli r0
#else #else
@@ -167,7 +167,7 @@ both tests are combined and there is a single CR rename buffer */
blt- 5f # Negative means guarded, zero R not set. blt- 5f # Negative means guarded, zero R not set.
mfsrr1 r3 # get saved cr0 bits now to dual issue mfsrr1 r3 # get saved cr0 bits now to dual issue
ori r1,r1,0x100 ori r1,r1,0x100
mtspr RPA,r1 mtspr PPC_RPA,r1
tlbli r0 tlbli r0
/* Do not update PTE if R bit already set, this will save one cache line /* Do not update PTE if R bit already set, this will save one cache line
writeback at a later time, and avoid even more bus traffic in writeback at a later time, and avoid even more bus traffic in
@@ -246,14 +246,14 @@ inserted for complex cases or for statistics recording. */
2: lwz r1,4(r2) # Found: load second word of PTE 2: lwz r1,4(r2) # Found: load second word of PTE
mfspr r0,DMISS # get miss address during load delay mfspr r0,DMISS # get miss address during load delay
#ifdef ASSUME_REF_SET #ifdef ASSUME_REF_SET
mtspr RPA,r1 mtspr PPC_RPA,r1
mfsrr1 r3 mfsrr1 r3
tlbld r0 tlbld r0
#else #else
andi. r3,r1,0x100 # check R bit ahead to help folding andi. r3,r1,0x100 # check R bit ahead to help folding
mfsrr1 r3 # get saved cr0 bits now to dual issue mfsrr1 r3 # get saved cr0 bits now to dual issue
ori r1,r1,0x100 ori r1,r1,0x100
mtspr RPA,r1 mtspr PPC_RPA,r1
tlbld r0 tlbld r0
/* Do not update PTE if R bit already set, this will save one cache line /* Do not update PTE if R bit already set, this will save one cache line
writeback at a later time, and avoid even more bus traffic in writeback at a later time, and avoid even more bus traffic in
@@ -323,7 +323,7 @@ write schemes. So the protection check is ABSOLUTELY necessary. */
andi. r3,r1,0x80 # check C bit andi. r3,r1,0x80 # check C bit
beq- 5f # if (C==0) go to check protection beq- 5f # if (C==0) go to check protection
3: mfsrr1 r3 # get the saved cr0 bits 3: mfsrr1 r3 # get the saved cr0 bits
mtspr RPA,r1 # set the pte mtspr PPC_RPA,r1 # set the pte
tlbld r0 # load the dtlb tlbld r0 # load the dtlb
mtcrf 0x80,r3 # restore CR0 mtcrf 0x80,r3 # restore CR0
rfi # return to executing program rfi # return to executing program

5
c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
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@@ -26,8 +26,7 @@
#include <rtems/bspIo.h> #include <rtems/bspIo.h>
#include <bsp.h> #include <bsp.h>
SPR_RW(DEC) SPR_RO(PPC_PVR)
SPR_RO(PVR)
struct inode; struct inode;
struct wait_queue; struct wait_queue;
@@ -264,7 +263,7 @@ setup_hw(void)
default_vga_cmd = 0; default_vga_cmd = 0;
#define vpd res->VitalProductData #define vpd res->VitalProductData
if (_read_PVR()>>16 != 1) { if (_read_PPC_PVR()>>16 != 1) {
if ( res && vpd.ProcessorBusHz ) { if ( res && vpd.ProcessorBusHz ) {
ticks_per_ms = vpd.ProcessorBusHz/ ticks_per_ms = vpd.ProcessorBusHz/
(vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000); (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000);

4
c/src/lib/libbsp/powerpc/shared/bootloader/mm.c
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@@ -95,7 +95,7 @@ typedef struct _map {
SPR_RW(SDR1); SPR_RW(SDR1);
SPR_RO(DSISR); SPR_RO(DSISR);
SPR_RO(DAR); SPR_RO(PPC_DAR);
/* We need a few statically allocated free maps to bootstrap the /* We need a few statically allocated free maps to bootstrap the
* memory managment */ * memory managment */
@@ -140,7 +140,7 @@ void _handler(int vec, ctxt *p) {
vaddr = p->nip; vaddr = p->nip;
cause = p->msr; cause = p->msr;
} else { /* Valid for DSI and alignment exceptions */ } else { /* Valid for DSI and alignment exceptions */
vaddr = _read_DAR(); vaddr = _read_PPC_DAR();
cause = _read_DSISR(); cause = _read_DSISR();
} }

3
c/src/lib/libbsp/powerpc/shared/console/polled_io.c
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@@ -373,9 +373,6 @@ unsigned int accent_table_size = 68;
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */ #define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80 #define KBD_MODE_RFU 0x80
SPR_RW(DEC)
SPR_RO(PVR)
#endif /* USE_KBD_SUPPORT */ #endif /* USE_KBD_SUPPORT */
/* Early messages after mm init but before console init are kept in log /* Early messages after mm init but before console init are kept in log

6
c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c
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@@ -110,7 +110,7 @@ extern uint32_t __rtems_end[];
SPR_RW(L2CR) SPR_RW(L2CR)
SPR_RW(L3CR) SPR_RW(L3CR)
SPR_RO(PVR) SPR_RO(PPC_PVR)
SPR_RW(HID0) SPR_RW(HID0)
@@ -127,8 +127,8 @@ register uint32_t v, x;
#undef DSSALL #undef DSSALL
} }
asm volatile("sync"); asm volatile("sync");
switch ( _read_PVR()>>16 ) { switch ( _read_PPC_PVR()>>16 ) {
default: printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PVR()); default: printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PPC_PVR());
return -1; return -1;
case PPC_750: printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n"); case PPC_750: printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n");
return -2; /* cannot lock L2 :-( */ return -2; /* cannot lock L2 :-( */