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Remove (Obsolete).

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Ralf Corsepius
2005-04-23 04:56:01 +00:00
parent 0b789b62a7
commit 6a88b80664
11 changed files with 0 additions and 2525 deletions
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2
cpukit/score/cpu/or32/.cvsignore
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Makefile
Makefile.in

304
cpukit/score/cpu/or32/ChangeLog
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2005-04-23 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/types.h, rtems/score/cpu.h,
rtems/score/cpu_asm.h, rtems/score/or32.h,
rtems/asm.h, Makefile.am, cpu.c, cpu_asm.c,
preinstall.am: Remove.
2005-02-08 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Split out preinstallation rules.
* preinstall.am: New (Split out from Makefile.am).
2005-02-04 Ralf Corsepius <ralf.corsepius@rtems.org>
PR 754/rtems
* rtems/asm.h: New (relocated from .).
* asm.h: Remove (moved to rtems/asm.h).
* Makefile.am: Reflect changes above.
2004-01-28 Ralf Corsepius <ralf.corsepiu@rtems.org>
* asm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h,
rtems/score/or32.h, rtems/score/types.h: New header guards.
2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Remove signed8, signed16, signed32,
unsigned8, unsigned16, unsigned32.
2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/cpu.h: *_swap_u32( uint32_t ).
2005-01-24 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/types.h: #include <rtems/stdint.h>.
2005-01-07 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
2005-01-01 Ralf Corsepius <ralf.corsepius@rtems.org>
* Makefile.am: Remove build-variant support.
2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/score/types.h: Use __rtems_score_types_h as preprocessor
guard.
2004-11-21 Ralf Corsepius <ralf.corsepius@rtems.org>
* asm.h: Add doxygen preamble.
2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org>
* rtems/score/cpu.h: Add doxygen preamble.
* rtems/score/cpu_asm.h: Add doxygen preamble.
* rtems/score/or32.h: Add doxygen preamble.
* rtems/score/types.h: Add doxygen preamble.
2004-09-29 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: i960 obsoleted and all references removed.
2004-04-06 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: Remove (Merged into$(top_srcdir)/configure.ac).
* Makefile.am: Don't include multilib.am.
Reflect merging configure.ac into $(top_srcdir)/configure.ac.
2004-04-01 Ralf Corsepius <ralf_corsepius@rtems.org>
* Makefile.am: Install asm.h to $(includedir)/rtems.
2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
* cpu.c, cpu_asm.c, rtems/score/cpu.h: Convert to using c99 fixed
size types.
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]).
2004-01-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Move RTEMS_TOP one subdir down.
2004-01-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add PREINSTALL_DIRS.
2004-01-14 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
Add PREINSTALL_FILES to CLEANFILES.
2004-01-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Requires automake >= 1.8.1.
2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Include compile.am, again.
2004-01-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Convert to using automake compilation rules.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
2003-12-12 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Require automake >= 1.8, autoconf >= 2.59.
2003-12-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Remove TMPINSTALL_FILES.
2003-11-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add $(dirstamp) to preinstallation rules.
2003-11-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Don't use gmake rules for preinstallation.
2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove RTEMS_CANONICAL_HOST.
2003-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove RTEMS_CHECK_CPU.
2003-09-26 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
references.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* cpu.c, cpu_asm.c, rtems/score/cpu.h, rtems/score/cpu_asm.h,
rtems/score/or32.h, rtems/score/types.h: URL for license changed.
2003-08-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Use rtems-bugs@rtems.com as bug report email address.
2003-03-06 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove AC_CONFIG_AUX_DIR.
2002-12-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Require autoconf-2.57 + automake-1.7.2.
* Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
2002-11-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Fix package name.
2002-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
2002-10-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Reformat.
Add autom4te*cache.
Remove autom4te.cache.
2002-09-14 Ivan Guzvinec <ivang@opencores.org>
* rtems/score/cpu.h (_CPU_Initialize_vectors) Define to NULL
since it is not used.
2002-08-06 Joel Sherrill <joel@OARcorp.com>
* asm.h, rtems/score/cpu.h: Correct items that have changed since
RTEMS version or32 port was based upon.
2002-08-05 Chris Ziomkowski <chris@asics.ws>
* asm.h, cpu.c, cpu_asm.c, rtems/score/cpu.h, rtems/score/or32.h,
rtems/score/types.h: Merged from OpenCores CVS repository.
2002-07-26 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Build libscorecpu.a instead of rtems-cpu.rel.
2002-07-22 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use .$(OBJEXT) instead of .o.
2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: RTEMS_TOP(../../../..).
2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems.c: Remove.
* Makefile.am: Reflect changes above.
2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Remove RTEMS_PROJECT_ROOT.
2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Add RTEMS_PROG_CCAS
2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
Add AC_PROG_RANLIB.
2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
Use ../../../aclocal.
2001-04-03 Joel Sherrill <joel@OARcorp.com>
* Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
* rtems/score/or32types.h: Removed.
* rtems/score/types.h: New file via CVS magic.
* Makefile.am, rtems/score/cpu.h: Account for name change.
2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* configure.ac:
AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
AM_INIT_AUTOMAKE([no-define foreign 1.6]).
* Makefile.am: Remove AUTOMAKE_OPTIONS.
2001-02-27 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Fix conditional to match current GCC.
2001-02-05 Joel Sherrill <joel@OARcorp.com>
* rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
2002-01-28 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/Makefile.am: Removed.
* rtems/score/Makefile.am: Removed.
* configure.ac: Reflect changes above.
* Makefile.am: Reflect changes above.
2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Add multilib support.
2001-11-28 Joel Sherrill <joel@OARcorp.com>,
This was tracked as PR91.
* rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
is used to specify if the port uses the standard macro for this (FALSE).
A TRUE setting indicates the port provides its own implementation.
2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* .cvsignore: Add autom4te.cache for autoconf > 2.52.
* configure.in: Remove.
* configure.ac: New file, generated from configure.in by autoupdate.
2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
* Makefile.am: Use 'PREINSTALL_FILES ='.
2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am, rtems/score/Makefile.am:
Apply include_*HEADERS instead of H_FILES.
2001-01-03 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: Added _CPU_Initialize_vectors().
2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
Switch to GNU canonicalization.
2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* Makefile.am: Include compile.am.
2000-08-11 Joel Sherrill <joel@OARcorp.com>
* Shell added for or32 port based on no_cpu port with names replaced.

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cpukit/score/cpu/or32/Makefile.am
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##
## $Id$
##
include $(top_srcdir)/automake/compile.am
CLEANFILES =
DISTCLEANFILES =
include_rtemsdir = $(includedir)/rtems
include_rtems_HEADERS= rtems/asm.h
include_rtems_scoredir = $(includedir)/rtems/score
include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/types.h \
rtems/score/or32.h rtems/score/cpu_asm.h
noinst_LIBRARIES = libscorecpu.a
libscorecpu_a_SOURCES = cpu.c cpu_asm.c
libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
all-local: $(PREINSTALL_FILES)
include $(srcdir)/preinstall.am
include $(top_srcdir)/automake/local.am

192
cpukit/score/cpu/or32/cpu.c
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/*
* Opencore Or1k CPU Dependent Source
*
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* This file adapted from no_bsp board library of the RTEMS distribution.
* The body has been modified for the Bender Or1k implementation by
* Chris Ziomkowski. <chris@asics.ws>
*/
#include <rtems/system.h>
#include <rtems/score/isr.h>
#include <rtems/score/wkspace.h>
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS:
* cpu_table - CPU table to initialize
* thread_dispatch - address of disptaching routine
*
*/
void _CPU_Initialize(
rtems_cpu_table *cpu_table,
void (*thread_dispatch)
)
{
/*
* The thread_dispatch argument is the address of the entry point
* for the routine called at the end of an ISR once it has been
* decided a context switch is necessary. On some compilation
* systems it is difficult to call a high-level language routine
* from assembly. This allows us to trick these systems.
*
* If you encounter this problem save the entry point in a CPU
* dependent variable.
*/
_CPU_Thread_dispatch_pointer = thread_dispatch;
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
_CPU_Table = *cpu_table;
}
/*PAGE
*
* _CPU_ISR_Get_level
*
* or1k Specific Information:
*
* There are only 2 interrupt levels for the or1k architecture.
* Either interrupts are enabled or disabled. They are considered
* enabled if both exceptions are enabled (SR_EXR) and interrupts
* are enabled (SR_EIR). If either of these conditions are not
* met, interrupts are disabled, and a level of 1 is returned.
*/
inline uint32_t _CPU_ISR_Get_level( void )
{
register uint32_t sr;
asm("l.mfspr %0,r0,0x17" : "=r" (sr));
return !((sr & SR_EXR) && (sr & SR_EIR));
}
/*PAGE
*
* _CPU_ISR_install_raw_handler
*
* or1k Specific Information:
*
* As a general rule the following is done for interrupts:
*
* For normal exceptions, exceptions are immediately reenabled
* by setting the SR_EXR bit. For interrupt exceptions, the
* SR_EIR bit is first cleared, and then exceptions are reenabled.
*/
void _CPU_ISR_install_raw_handler(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
register uint32_t sr;
register uint32_t tmp;
extern uint32_t Or1k_Interrupt_Vectors[];
asm volatile ("l.mfspr %0,r0,0x11\n\t"
"l.addi %1,r0,-5\n\t"
"l.and %1,%1,%0\n\t": "=r" (sr) : "r" (tmp));
*old_handler = *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]);
*((proc_ptr*)&Or1k_Interrupt_Vectors[vector]) = new_handler;
asm volatile ("l.mtspr r0,%0,0x11\n\t":: "r" (sr));
}
/*PAGE
*
* _CPU_ISR_install_vector
*
* This kernel routine installs the RTEMS handler for the
* specified vector.
*
* Input parameters:
* vector - interrupt vector number
* old_handler - former ISR for this vector number
* new_handler - replacement ISR for this vector number
*
* Output parameters: NONE
*
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_ISR_install_vector(
uint32_t vector,
proc_ptr new_handler,
proc_ptr *old_handler
)
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* If the interrupt vector table is a table of pointer to isr entry
* points, then we need to install the appropriate RTEMS interrupt
* handler for this vector number.
*/
_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
/*
* We put the actual user ISR address in '_ISR_vector_table'. This will
* be used by the _ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
/*PAGE
*
* _CPU_Install_interrupt_stack
*
* We don't use a separate interrupt stack.
*
*/
void _CPU_Install_interrupt_stack( void )
{
}
/*PAGE
*
* _CPU_Thread_Idle_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*
*/
void _CPU_Thread_Idle_body( void )
{
for( ; ; )
/* insert your "halt" instruction here */ ;
}

578
cpukit/score/cpu/or32/cpu_asm.c
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/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
*
* This file contains the basic algorithms for all assembly code used
* in an specific CPU port of RTEMS. These algorithms must be implemented
* in assembly language
*
* NOTE: This is supposed to be a .S or .s file NOT a C file.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* This file adapted from no_bsp board library of the RTEMS distribution.
* The body has been modified for the Bender Or1k implementation by
* Chris Ziomkowski. <chris@asics.ws>
*/
/*
* This is supposed to be an assembly file. This means that system.h
* and cpu.h should not be included in a "real" cpu_asm file. An
* implementation in assembly should include "cpu_asm.h>
*/
#include <rtems/system.h>
#include <rtems/score/cpu.h>
/* #include "cpu_asm.h> */
/*
* _CPU_Context_save_fp_context
*
* This routine is responsible for saving the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
* Sometimes a macro implementation of this is in cpu.h which dereferences
* the ** and a similarly named routine in this file is passed something
* like a (Context_Control_fp *). The general rule on making this decision
* is to avoid writing assembly language.
*
* or1k specific Information:
*
* This implementation of RTEMS considers the concept of
* "fast context switching", as defined in the or1k architecture
* specification. Whether or not this makes a significant
* impact on speed is dubious, however it is not a significant
* impediment to include it. It probably wastes a few cycles on
* every floating point context switch.
*
* This implementation will currently not work on a processor where
* the integer unit and floating point unit are not the same size. I
* am waiting on an architecture change to make this feasible. It
* should work fine on 64 bit architectures, except for the fact that
* the variables are declared as 32 bits. This shouldn't really make
* a difference, as the fact that they must be registers should force
* them into a 64 bit word anyway.
*
* The decision as to whether to do 32 or 64 bit saves is performed
* at run time based on the configuration of the CPUCFGR register. This
* takes a performance hit of a few cycles, but this should be a very
* small percentage of the total number of cycles necessary to do the
* save, and doesn't require special code for 32 or 64 bit versions.
*
* ADDITIONAL INFORMATION:
*
* It has been unanimously agreed that floating point will not be
* included in the initial releases of the Or1k chips, and that
* significant changes to the floating point architecture may
* occur before any such release will ever be implemented. The code
* below is therefore never called and never used.
*/
void _CPU_Context_save_fp(
void **fp_context_ptr
)
{
register uint32_t temp;
register uint32_t address = (uint32_t )(*fp_context_ptr);
register uint32_t xfer;
register uint32_t loop;
/* %0 is a temporary register which is used for several
values throughout the code. %3 contains the address
to save the context, and is modified during the course
of the context save. %1 is a second dummy register
which is used during transfer of the floating point
value to memory. %2 is an end of loop marker which
is compared against the pointer %3. */
asm volatile ("l.mfspr %0,r0,0x02 \n\t" /* CPUCFGR */
"l.andi %0,%0,0x380 \n\t" /* OF32S or OV64S or OF64S */
"l.sfnei %0,0x0 \n\t"
"l.bf _L_nofps \n\t" /* exit if no floating point */
"l.sfeqi %0,0x080 \n\t" /* (DELAY) single precision? */
"l.mfspr %0,r0,0x11 \n\t" /* Load Status Register */
"l.srli %0,%0,58 \n\t" /* Move CID into low byte*32 */
"l.bnf _L_spfp_loops \n\t" /* Branch on single precision */
"l.addi %2,%0,0x20 \n" /* Terminating condition */
/**** Double Precision Floating Point Section ****/
"_L_dpfp_loops: \n\t"
"l.mfspr %1,%0,0x600 \n\t" /* Load VFRx */
"l.sd 0(%3),%1 \n\t" /* Save VFRx */
"l.addi %0,%0,0x01 \n\t" /* Increment counter */
"l.sfeq %0,%2 \n\t" /* Branch if incomplete */
"l.bf _L_dpfp_loops \n\t"
"l.addi %3,%3,0x08 \n\t" /* (DELAY) update pointer */
"l.bnf _L_nofps \n\t" /* exit */
"l.nop \n"
/**** Single Precision Floating Point Section ****/
"_L_spfp_loops: \n\t"
"l.mfspr %1,%0,0x600 \n\t" /* Load VFRx */
"l.sw 0(%3),%1 \n\t" /* Save VFRx */
"l.addi %0,%0,0x01 \n\t" /* Increment counter */
"l.sfeq %0,%2 \n\t" /* Branch if incomplete */
"l.bf _L_spfp_loops \n\t"
"l.addi %3,%3,0x04 \n" /* (DELAY) update pointer */
"_L_nofps: \n\t" /* End of context save */
: "=&r" (temp), "=r" (xfer), "=&r" (loop), "+r" (address));
}
/*
* _CPU_Context_restore_fp_context
*
* This routine is responsible for restoring the FP context
* at *fp_context_ptr. If the point to load the FP context
* from is changed then the pointer is modified by this routine.
*
*
*/
void _CPU_Context_restore_fp(
void **fp_context_ptr
)
{
register uint32_t temp;
register uint32_t address = (uint32_t )(*fp_context_ptr);
register uint32_t xfer;
register uint32_t loop;
/* The reverse of Context_save_fp */
/* %0 is a temporary register which is used for several
values throughout the code. %1 contains the address
to save the context, and is modified during the course
of the context save. %2 is a second dummy register
which is used during transfer of the floating point
value to memory. %3 is an end of loop marker which
is compared against the pointer %1. */
asm volatile ("l.mfspr %0,r0,0x02 \n\t" /* CPUCFGR */
"l.andi %0,%0,0x380 \n\t" /* OF32S or OV64S or OF64S */
"l.sfnei %0,0x0 \n\t"
"l.bf _L_nofpr \n\t" /* exit if no floating point */
"l.sfeqi %0,0x080 \n\t" /* (DELAY) single precision? */
"l.mfspr %0,r0,0x11 \n\t" /* Load Status Register */
"l.srli %0,%0,58 \n\t" /* Move CID into low byte*32 */
"l.bnf _L_spfp_loopr \n\t" /* Branch on single precision */
"l.addi %3,%0,0x20 \n" /* Terminating condition */
/**** Double Precision Floating Point Section ****/
"_L_dpfp_loopr: \n\t"
"l.mfspr %2,%0,0x600 \n\t" /* Load VFRx */
"l.sd 0(%1),%2 \n\t" /* Save VFRx */
"l.addi %0,%0,0x01 \n\t" /* Increment counter */
"l.sfeq %0,%3 \n\t" /* Branch if incomplete */
"l.bf _L_dpfp_loopr \n\t"
"l.addi %1,%1,0x08 \n\t" /* (DELAY) update pointer */
"l.bnf _L_nofpr \n\t" /* exit */
"l.nop \n"
/**** Single Precision Floating Point Section ****/
"_L_spfp_loopr: \n\t"
"l.mfspr %2,%0,0x600 \n\t" /* Load VFRx */
"l.sw 0(%1),%2 \n\t" /* Save VFRx */
"l.addi %0,%0,0x01 \n\t" /* Increment counter */
"l.sfeq %0,%3 \n\t" /* Branch if incomplete */
"l.bf _L_spfp_loopr \n\t"
"l.addi %1,%1,0x04 \n" /* (DELAY) update pointer */
"_L_nofpr: \n\t" /* End of context save */
: "=&r" (temp), "+r" (address), "=r" (xfer), "=&r" (loop));
}
/* _CPU_Context_switch
*
* This routine performs a normal non-FP context switch.
*
* NO_CPU Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_Context_switch(
Context_Control *run,
Context_Control *heir
)
{
register uint32_t temp1 = 0;
register uint32_t temp2 = 0;
/* This function is really tricky. When this function is called,
we should save our state as we need it, and then grab the
new state from the pointer. We then do a longjump to this
code, replacing the current stack pointer with the new
environment. This function never returns. Instead, at some
later time, another person will call context switch with
our pointer in the heir variable, and they will longjump
to us. We will then continue. Let's see how this works... */
/* Technically, we could probably not worry about saving r3
and r4, since these are parameters guaranteed to be saved
by the calling function. We could also probably get away
without saving r11, as that is filled in by the return
statement. But as a first cut I'm in favor of just saving
everything.... */
/* We could be more efficient and use compile time directives
for 32 or 64 bit, but this will allow the code to run on
everything without modification. Feel free to comment the
relevant sections out if you don't need it. */
/* We should probably write this whole routine in assembly
so that we can have seperate entry points for self restore
or context switch. You can't jump to local labels from
inline assembly across function calls, and I don't feel
like embedding all the .global directives here...it really
screws up the debugger. Oh well, what's 2 more instructions
and a branch really cost... */
/* One thing which we should do is check for 32 or 64 bit models
first, and then do one branch to the appropriate code section.
Currently, we check the architecture bit in CPUCFGR twice. Once
during the load section and again during restore. That is inefficient,
and considering this code is huge anyway, saving the few bytes
simply doesn't make any practical sense. FIX THIS LATER. */
/* Note that this routine assumes software context switches are
done with the same CID. In other words, it will not manage
the CIDs and assign a new one as necessary. If you tell it
to restore a context at CID 2, and the current one is at CID
4, it will do what it is told. It will overwrite the registers
for context ID 2, meaning they are irretrievably lost. I hope
you saved them earlier.... */
/* Note that you can have a context jump anywhere you want, although
by default we will jump to the L_restore label. If you then modify
the location in the Context_Control structure, it will continue
whereever you told it to go. Note however that you had better
also have cleaned up the stack and frame pointers though, because
they are probably still set with the values obtained from
entering this function... */
asm volatile ("l.sfeqi %3,0x0 \n\t" /* Is this a self restore? */
"l.bf _L_restore \n\t" /* Yes it is...go there */
"l.nop \n\t"
"l.lwz %0,0(%3) \n\t" /* Prefetch new context */
"l.mfspr %2,r0,0x11 \n\t" /* Status Register */
"l.sw 0(%1),%2 \n\t" /* Save it */
"l.srli %2,%2,28 \n\t" /* Move CID into low byte */
"l.mfspr %0,%2,0x20 \n\t" /* Offset from EPCR */
"l.sw 4(%1),%0 \n\t" /* Store it */
"l.mfspr %0,%2,0x30 \n\t" /* Offset from EEAR */
"l.sw 8(%1),%0 \n\t" /* Store it */
"l.mfspr %0,%2,0x40 \n\t" /* Offset from ESR */
"l.sw 12(%1),%0 \n\t" /* Store it */
"l.mfspr %0,r0,0x02 \n\t" /* CPUCFGR */
"l.andi %0,%0,0x40 \n\t" /* OB64S */
"l.sfnei %0,0x0 \n\t"
"l.bf _L_64bit \n\t" /* 64 bit architecture */
"l.movhi %0,hi(_L_restore)\n\t"
/**** 32 bit implementation ****/
"l.ori %0,%0,lo(_L_restore)\n\t"
"l.sw 140(%1),%0 \n\t" /* Save the PC */
"l.lwz %0,140(%3) \n\t" /* New PC. Expect cache miss */
"l.sw 16(%1),r1 \n\t"
"l.sw 20(%1),r2 \n\t"
"l.sw 24(%1),r3 \n\t"
"l.sw 28(%1),r4 \n\t"
"l.sw 32(%1),r5 \n\t"
"l.sw 36(%1),r6 \n\t"
"l.sw 40(%1),r7 \n\t"
"l.sw 44(%1),r8 \n\t"
"l.sw 48(%1),r9 \n\t"
"l.sw 52(%1),r10 \n\t"
"l.sw 56(%1),r11 \n\t"
"l.sw 60(%1),r12 \n\t"
"l.sw 64(%1),r13 \n\t"
"l.sw 68(%1),r14 \n\t"
"l.sw 72(%1),r15 \n\t"
"l.sw 76(%1),r16 \n\t"
"l.sw 80(%1),r17 \n\t"
"l.sw 84(%1),r18 \n\t"
"l.sw 88(%1),r19 \n\t"
"l.sw 92(%1),r20 \n\t"
"l.sw 96(%1),r21 \n\t"
"l.sw 100(%1),r22 \n\t"
"l.sw 104(%1),r23 \n\t"
"l.sw 108(%1),r24 \n\t"
"l.sw 112(%1),r25 \n\t"
"l.sw 116(%1),r26 \n\t"
"l.sw 120(%1),r27 \n\t"
"l.sw 124(%1),r28 \n\t"
"l.sw 128(%1),r29 \n\t"
"l.sw 132(%1),r30 \n\t"
"l.jr %0 \n\t" /* Go there */
"l.sw 136(%1),r31 \n" /* Store the last reg */
/**** 64 bit implementation ****/
"_L_64bit: \n\t"
"l.ori %0,%0,lo(_L_restore)\n\t"
"l.sw 264(%1),%0 \n\t"
"l.sd 16(%1),r1 \n\t"
"l.sd 24(%1),r2 \n\t"
"l.sd 32(%1),r3 \n\t"
"l.sd 40(%1),r4 \n\t"
"l.sd 48(%1),r5 \n\t"
"l.sd 56(%1),r6 \n\t"
"l.sd 64(%1),r7 \n\t"
"l.sd 72(%1),r8 \n\t"
"l.sd 80(%1),r9 \n\t"
"l.sd 88(%1),r10 \n\t"
"l.sd 96(%1),r11 \n\t"
"l.sd 104(%1),r12 \n\t"
"l.sd 112(%1),r13 \n\t"
"l.sd 120(%1),r14 \n\t"
"l.sd 128(%1),r15 \n\t"
"l.sd 136(%1),r16 \n\t"
"l.sd 144(%1),r17 \n\t"
"l.sd 152(%1),r18 \n\t"
"l.sd 160(%1),r19 \n\t"
"l.sd 168(%1),r20 \n\t"
"l.sd 176(%1),r21 \n\t"
"l.sd 184(%1),r22 \n\t"
"l.sd 192(%1),r23 \n\t"
"l.sd 200(%1),r24 \n\t"
"l.sd 208(%1),r25 \n\t"
"l.sd 216(%1),r26 \n\t"
"l.sd 224(%1),r27 \n\t"
"l.sd 232(%1),r28 \n\t"
"l.sd 240(%1),r29 \n\t"
"l.sd 248(%1),r30 \n\t"
"l.jr %0 \n\t" /* Go to the new PC */
"l.sd 256(%1),r31 \n" /* Store the last reg */
/**** The restoration routine. ****/
/* Note that when we return from this function,
we will actually be returning to a different
context than when we left. The debugger might
have conniptions over this, but we'll have to
reengineer that later. The stack and status
registers will all be changed, however we
will not touch the global interrupt mask. */
/* Also note, when doing any restore, the most
important registers are r1, r2, and r9. These
will be accessed immediately upon exiting the
routine, and so we want to make sure we load
them as early as possible in case they are
not in cache */
"_L_restore: \n\t" /* Restore "heir" */
"l.mfspr %2,r0,0x11 \n\t" /* Status Register */
"l.movhi %0,0x07FF \n\t" /* ~SR mask */
"l.ori %0,%0,0xD1FF \n\t"
"l.and %2,%0,%2 \n\t" /* save the global bits */
"l.movhi %0,0xF800 \n\t" /* SR mask */
"l.ori %0,%0,0x2E00 \n\t"
"l.lwz %1,0(%3) \n\t" /* Get the previous SR */
"l.and %0,%1,%0 \n\t" /* Mask out the global bits */
"l.or %2,%2,%0 \n\t" /* Combine local/global */
"l.mtspr r0,%2,0x11 \n\t" /* Restore the status register */
"l.mfspr %0,r0,0x02 \n\t" /* CPUCFGR */
"l.andi %0,%0,0x40 \n\t" /* OB64S */
"l.sfnei %0,0x0 \n\t" /* Save the 64 bit flag */
"l.srli %2,%2,28 \n\t" /* Move CID into low byte */
"l.lwz %0,4(%3) \n\t"
"l.mtspr %2,%0,0x20 \n\t" /* Offset from EPCR */
"l.lwz %0,8(%3) \n\t"
"l.mtspr %2,%0,0x30 \n\t" /* Offset from EEAR */
"l.lwz %0,12(%3) \n\t"
"l.bf _L_r64bit \n\t" /* 64 bit architecture */
"l.mtspr %2,%0,0x30 \n\t" /* Offset from EEAR (DELAY) */
/**** 32 bit restore ****/
"l.lwz r1,16(%3) \n\t"
"l.lwz r2,20(%3) \n\t"
"l.lwz r9,48(%3) \n\t"
"l.lwz r3,24(%3) \n\t"
"l.lwz r4,28(%3) \n\t"
"l.lwz r5,32(%3) \n\t"
"l.lwz r6,36(%3) \n\t"
"l.lwz r7,40(%3) \n\t"
"l.lwz r8,44(%3) \n\t"
"l.lwz r10,52(%3) \n\t"
"l.lwz r11,56(%3) \n\t"
"l.lwz r12,60(%3) \n\t"
"l.lwz r13,64(%3) \n\t"
"l.lwz r14,68(%3) \n\t"
"l.lwz r15,72(%3) \n\t"
"l.lwz r16,76(%3) \n\t"
"l.lwz r17,80(%3) \n\t"
"l.lwz r18,84(%3) \n\t"
"l.lwz r19,88(%3) \n\t"
"l.lwz r20,92(%3) \n\t"
"l.lwz r21,96(%3) \n\t"
"l.lwz r22,100(%3) \n\t"
"l.lwz r23,104(%3) \n\t"
"l.lwz r24,108(%3) \n\t"
"l.lwz r25,112(%3) \n\t"
"l.lwz r26,116(%3) \n\t"
"l.lwz r27,120(%3) \n\t"
"l.lwz r28,124(%3) \n\t"
"l.lwz r29,128(%3) \n\t"
"l.lwz r30,132(%3) \n\t"
"l.j _L_return \n\t"
"l.lwz r31,136(%3) \n"
/**** 64 bit restore ****/
"_L_r64bit: \n\t"
"l.ld r1,16(%3) \n\t"
"l.ld r2,24(%3) \n\t"
"l.ld r9,80(%3) \n\t"
"l.ld r3,32(%3) \n\t"
"l.ld r4,40(%3) \n\t"
"l.ld r5,48(%3) \n\t"
"l.ld r6,56(%3) \n\t"
"l.ld r7,64(%3) \n\t"
"l.ld r8,72(%3) \n\t"
"l.ld r10,88(%3) \n\t"
"l.ld r11,96(%3) \n\t"
"l.ld r12,104(%3) \n\t"
"l.ld r13,112(%3) \n\t"
"l.ld r14,120(%3) \n\t"
"l.ld r15,128(%3) \n\t"
"l.ld r16,136(%3) \n\t"
"l.ld r17,144(%3) \n\t"
"l.ld r18,152(%3) \n\t"
"l.ld r19,160(%3) \n\t"
"l.ld r20,168(%3) \n\t"
"l.ld r21,176(%3) \n\t"
"l.ld r22,184(%3) \n\t"
"l.ld r23,192(%3) \n\t"
"l.ld r24,200(%3) \n\t"
"l.ld r25,208(%3) \n\t"
"l.ld r26,216(%3) \n\t"
"l.ld r27,224(%3) \n\t"
"l.ld r28,232(%3) \n\t"
"l.ld r29,240(%3) \n\t"
"l.ld r30,248(%3) \n\t"
"l.ld r31,256(%3) \n"
"_L_return: \n\t" /* End of routine */
: "=&r" (temp1), "+r" (run), "=&r" (temp2)
: "r" (heir));
/* Note that some registers were used for parameter passing and
temporary registeres (temp1 and temp2). These values were
saved and restored across context calls, but the values that
the caller needs should have been stored on the stack. The
C code should now restore these from the stack, since r1 and
r2 have been restored, and return to the location specified
by r9. Then, all should be happy in the world. */
}
/*
* _CPU_Context_restore
*
* This routine is generally used only to restart self in an
* efficient manner. It may simply be a label in _CPU_Context_switch.
*
* NOTE: May be unnecessary to reload some registers.
*
* Or1k Specific Information:
*
* In our implementation, this simply redirects to swich context
*/
void _CPU_Context_restore(
Context_Control *run
)
{
_CPU_Context_switch(run,NULL);
}
/* void __ISR_Handler()
*
* This routine provides the RTEMS interrupt management.
*
* Or1k Specific Information:
*
* Based on the Or1k interrupt architecture described in chapter 16
* and the exception architecture described in chapter 9
*/
void _ISR_Handler(uint32_t vector,uint32_t ProgramCounter,
uint32_t EffectiveAddress,uint32_t StatusRegister)
{
/*
* This discussion ignores a lot of the ugly details in a real
* implementation such as saving enough registers/state to be
* able to do something real. Keep in mind that the goal is
* to invoke a user's ISR handler which is written in C and
* uses a certain set of registers.
*
* Also note that the exact order is to a large extent flexible.
* Hardware will dictate a sequence for a certain subset of
* _ISR_Handler while requirements for setting
*/
/*
* At entry to "common" _ISR_Handler, the vector number must be
* available. On some CPUs the hardware puts either the vector
* number or the offset into the vector table for this ISR in a
* known place. If the hardware does not give us this information,
* then the assembly portion of RTEMS for this port will contain
* a set of distinct interrupt entry points which somehow place
* the vector number in a known place (which is safe if another
* interrupt nests this one) and branches to _ISR_Handler.
*
* save some or all context on stack
* may need to save some special interrupt information for exit
*
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* if ( _ISR_Nest_level == 0 )
* switch to software interrupt stack
* #endif
*
* _ISR_Nest_level++;
*
* _Thread_Dispatch_disable_level++;
*
* (*_ISR_Vector_table[ vector ])( vector );
*
* --_ISR_Nest_level;
*
* if ( _ISR_Nest_level )
* goto the label "exit interrupt (simple case)"
*
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* restore stack
* #endif
*
* if ( !_Context_Switch_necessary )
* goto the label "exit interrupt (simple case)"
*
* if ( !_ISR_Signals_to_thread_executing )
* _ISR_Signals_to_thread_executing = FALSE;
* goto the label "exit interrupt (simple case)"
*
* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
*
* prepare to get out of interrupt
* return from interrupt (maybe to _ISR_Dispatch)
*
* LABEL "exit interrupt (simple case):
* prepare to get out of interrupt
* return from interrupt
*/
/* In the Or1k architecture, exceptions are handled in the
startup code of the board support package. Thus, this
routine is never called. Or1k exception routines are called
with the following prototype:
function(int vector#, int PC, int Address, int StatusRegister);
These parameters are snapshots of the system when the exception
was encountered. If virtual memory is active, things like the
PC and Address may have little meaning, as they are referenced
in physical space, not the virtual space of the process.
*/
}

43
cpukit/score/cpu/or32/preinstall.am
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@@ -1,43 +0,0 @@
## Automatically generated by ampolish3 - Do not edit
if AMPOLISH3
$(srcdir)/preinstall.am: Makefile.am
$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
endif
PREINSTALL_DIRS =
DISTCLEANFILES += $(PREINSTALL_DIRS)
PREINSTALL_FILES =
CLEANFILES += $(PREINSTALL_FILES)
$(PROJECT_INCLUDE)/rtems/$(dirstamp):
@$(mkdir_p) $(PROJECT_INCLUDE)/rtems
@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
@$(mkdir_p) $(PROJECT_INCLUDE)/rtems/score
@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
$(PROJECT_INCLUDE)/rtems/score/or32.h: rtems/score/or32.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/or32.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/or32.h
$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h

100
cpukit/score/cpu/or32/rtems/asm.h
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@@ -1,100 +0,0 @@
/**
* @file rtems/asm.h
*
* This include file attempts to address the problems
* caused by incompatible flavors of assemblers and
* toolsets. It primarily addresses variations in the
* use of leading underscores on symbols and the requirement
* that register names be preceded by a %.
*/
/*
* NOTE: The spacing in the use of these macros
* is critical to them working as advertised.
*
* COPYRIGHT:
*
* This file is based on similar code found in newlib available
* from ftp.cygnus.com. The file which was used had no copyright
* notice. This file is freely distributable as long as the source
* of the file is noted. This file is:
*
* COPYRIGHT (c) 1994-1997.
* On-Line Applications Research Corporation (OAR).
*
* $Id$
*/
#ifndef _RTEMS_ASM_H
#define _RTEMS_ASM_H
/*
* Indicate we are in an assembly file and get the basic CPU definitions.
*/
#ifndef ASM
#define ASM
#endif
#include <rtems/score/targopts.h>
#include <rtems/score/or32.h>
/*
* Recent versions of GNU cpp define variables which indicate the
* need for underscores and percents. If not using GNU cpp or
* the version does not support this, then you will obviously
* have to define these as appropriate.
*/
#ifndef __USER_LABEL_PREFIX__
#define __USER_LABEL_PREFIX__ _
#endif
#ifndef __REGISTER_PREFIX__
#define __REGISTER_PREFIX__
#endif
/* ANSI concatenation macros. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
/* Use the right prefix for global labels. */
#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
/* Use the right prefix for registers. */
#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
/*
* define macros for all of the registers on this CPU
*
* EXAMPLE: #define d0 REG (d0)
*/
/*
* Define macros to handle section beginning and ends.
*/
#define BEGIN_CODE_DCL .text
#define END_CODE_DCL
#define BEGIN_DATA_DCL .data
#define END_DATA_DCL
#define BEGIN_CODE .text
#define END_CODE
#define BEGIN_DATA
#define END_DATA
#define BEGIN_BSS
#define END_BSS
#define END
/*
* Following must be tailor for a particular flavor of the C compiler.
* They may need to put underscores in front of the symbols.
*/
#define PUBLIC(sym) .global SYM (sym)
#define EXTERN(sym) .global SYM (sym)
#endif

1070
cpukit/score/cpu/or32/rtems/score/cpu.h
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File diff suppressed because it is too large Load Diff

72
cpukit/score/cpu/or32/rtems/score/cpu_asm.h
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@@ -1,72 +0,0 @@
/**
* @file rtems/score/cpu_asm.h
*/
/*
* Very loose template for an include file for the cpu_asm.? file
* if it is implemented as a ".S" file (preprocessed by cpp) instead
* of a ".s" file (preprocessed by gm4 or gasp).
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*
*/
#ifndef _RTEMS_SCORE_CPU_ASM_H
#define _RTEMS_SCORE_CPU_ASM_H
/* pull in the generated offsets */
#include <rtems/score/offsets.h>
/*
* Hardware General Registers
*/
/* put something here */
/*
* Hardware Floating Point Registers
*/
/* put something here */
/*
* Hardware Control Registers
*/
/* put something here */
/*
* Calling Convention
*/
/* put something here */
/*
* Temporary registers
*/
/* put something here */
/*
* Floating Point Registers - SW Conventions
*/
/* put something here */
/*
* Temporary floating point registers
*/
/* put something here */
#endif
/* end of file */

72
cpukit/score/cpu/or32/rtems/score/or32.h
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@@ -1,72 +0,0 @@
/**
* @file rtems/score/or32.h
*/
/*
* This include file contains Or1k definitions pertaining to the Opencores
* or1k processor family.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* This file adapted from no_cpu example of the RTEMS distribution.
* The body has been modified for the Opencores Or1k implementation by
* Chris Ziomkowski. <chris@asics.ws>
*
*/
#ifndef _RTEMS_SCORE_OR32_H
#define _RTEMS_SCORE_OR32_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* This file contains the information required to build
* RTEMS for a particular member of the or1k CPU family.
* It does this by setting variables to indicate which
* implementation dependent features are present in a particular
* member of the family.
*
* This is a good place to list all the known CPU models
* that this port supports and which RTEMS CPU model they correspond
* to.
*/
#if defined(rtems_multilib)
/*
* Figure out all CPU Model Feature Flags based upon compiler
* predefines.
*/
#define CPU_MODEL_NAME "rtems_multilib"
#define OR1K_HAS_FPU 1
#elif defined(or1200)
#define CPU_MODEL_NAME "OR1200"
#define OR1K_HAS_FPU 0
#else
#define CPU_MODEL_NAME "Generic Or1k Compatible"
#define OR1K_HAS_FPU 0
#endif
/*
* Define the name of the CPU family.
*/
#define CPU_NAME "OpenRisc 1000"
#ifdef __cplusplus
}
#endif
#endif /* _RTEMS_SCORE_OR32_H */

67
cpukit/score/cpu/or32/rtems/score/types.h
View File

@@ -1,67 +0,0 @@
/**
* @file rtems/score/types.h
*/
/*
* This include file contains type definitions pertaining to the Opencores
* or1k processor family.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* This file adapted from no_cpu example of the RTEMS distribution.
* The body has been modified for the Opencores Or1k implementation by
* Chris Ziomkowski. <chris@asics.ws>
*/
#ifndef _RTEMS_SCORE_TYPES_H
#define _RTEMS_SCORE_TYPES_H
#ifndef ASM
#include <rtems/stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* This section defines the basic types for this processor.
*/
typedef unsigned long long unsigned64; /* unsigned 64-bit integer */
typedef unsigned16 Priority_Bit_map_control;
typedef signed long long signed64; /* 64 bit signed integer */
typedef unsigned32 boolean; /* Boolean value */
typedef float single_precision; /* single precision float */
typedef double double_precision; /* double precision float */
typedef void no_cpu_isr;
typedef void ( *no_cpu_isr_entry )( void );
/*
* Turns out the that the disable POSIX option doesn't work
* too well. Specifically, the libc library still wants to know
* these POSIX values. We'll go ahead and include them here
* until such time as someone like OAR who is familiar with this
* can figure out what should really be done.
*/
#define NAME_MAX 255
#define LINK_MAX 8
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif