forked from Imagelibrary/rtems
2008-07-04 Matthew Riek <matthew.riek@ibiscomputer.com.au>
* Makefile.am, README, include/coverhd.h, network/network.c, startup/bspstart.c, startup/cfinit.c, startup/linkcmdsflash: Add cache support for 5329. Fix bug in network driver. Enable the cache in copyback and write-through so we can assume that in BSP.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,10 @@
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2008-07-04 Matthew Riek <matthew.riek@ibiscomputer.com.au>
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* Makefile.am, README, include/coverhd.h, network/network.c,
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startup/bspstart.c, startup/cfinit.c, startup/linkcmdsflash: Add
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cache support for 5329. Fix bug in network driver. Enable the cache
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in copyback and write-through so we can assume that in BSP.
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2008-06-23 Joel Sherrill <joel.sherrill@OARcorp.com>
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* .cvsignore: New file.
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@@ -52,7 +52,9 @@ libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
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libbsp_a_LIBADD = \
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../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
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../../../libcpu/@RTEMS_CPU@/shared/misc.rel
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../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
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../../../libcpu/@RTEMS_CPU@/mcf532x/cachepd.rel
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if HAS_NETWORKING
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libbsp_a_LIBADD += network.rel
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endif
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@@ -25,27 +25,337 @@ TODO:
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Add other drivers for can, i2c, lcd (fb), qspi etc.
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============================================================================
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Interrupt map
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+-----+-----------------------------------------------------------------------+
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| | PRIORITY |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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|LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 7 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 6 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 5 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 4 | FEC RX | FEC TX | | | | | | PIT |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 3 | UART 0 | UART 1 | UART 2 | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 2 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 1 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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+-----+
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| |
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+-----+
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|LEVEL|
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+-----+
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| 7 |
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+-----+
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| 6 |
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+-----+
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| 5 |
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+-----+
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| 4 | FEC RX, FEC TX, PIT
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+-----+
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| 3 | UART 0, UART 1, UART 2
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+-----+
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| 2 |
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+-----+
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| 1 |
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+-----+
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============================================================================
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Timings
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*** TIME TEST 1 ***
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rtems_semaphore_create 11
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rtems_semaphore_delete 9
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rtems_semaphore_obtain: available 0
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rtems_semaphore_obtain: not available -- NO_WAIT 0
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rtems_semaphore_release: no waiting tasks 2
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*** END OF TEST 1 ***
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*** TIME TEST 2 ***
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rtems_semaphore_obtain: not available -- caller blocks 14
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*** END OF TEST 2 ***
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*** TIME TEST 3 ***
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rtems_semaphore_release: task readied -- preempts caller 11
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*** END OF TEST 3 ***
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*** TIME TEST 4 ***
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rtems_task_restart: blocked task -- preempts caller 24
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rtems_task_restart: ready task -- preempts caller 15
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rtems_semaphore_release: task readied -- returns to caller 3
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rtems_task_create 40
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rtems_task_start 7
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rtems_task_restart: suspended task -- returns to caller 8
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rtems_task_delete: suspended task 18
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rtems_task_restart: ready task -- returns to caller 9
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rtems_task_restart: blocked task -- returns to caller 10
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rtems_task_delete: blocked task 19
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*** END OF TEST 4 ***
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*** TIME TEST 5 ***
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rtems_task_suspend: calling task 11
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rtems_task_resume: task readied -- preempts caller 9
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*** END OF TEST 5 ***
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*** TIME TEST 6 ***
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rtems_task_restart: calling task 4
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rtems_task_suspend: returns to caller 2
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rtems_task_resume: task readied -- returns to caller 2
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rtems_task_delete: ready task 19
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*** END OF TEST 6 ***
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*** TIME TEST 7 ***
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rtems_task_restart: suspended task -- preempts caller 15
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*** END OF TEST 7 ***
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*** TIME TEST 8 ***
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rtems_task_set_priority: obtain current priority 1
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rtems_task_set_priority: returns to caller 2
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rtems_task_mode: obtain current mode 0
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rtems_task_mode: no reschedule 0
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rtems_task_mode: reschedule -- returns to caller 1
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rtems_task_mode: reschedule -- preempts caller 13
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rtems_task_set_note 1
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rtems_task_get_note 1
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rtems_clock_set 1
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rtems_clock_get 4
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*** END OF TEST 8 ***
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*** TIME TEST 9 ***
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rtems_message_queue_create 45
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rtems_message_queue_send: no waiting tasks 2
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rtems_message_queue_urgent: no waiting tasks 2
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rtems_message_queue_receive: available 3
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rtems_message_queue_flush: no messages flushed 1
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rtems_message_queue_flush: messages flushed 1
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rtems_message_queue_delete 12
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*** END OF TEST 9 ***
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*** TIME TEST 10 ***
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rtems_message_queue_receive: not available -- NO_WAIT 1
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rtems_message_queue_receive: not available -- caller blocks 14
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*** END OF TEST 10 ***
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*** TIME TEST 11 ***
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rtems_message_queue_send: task readied -- preempts caller 13
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*** END OF TEST 11 ***
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*** TIME TEST 12 ***
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rtems_message_queue_send: task readied -- returns to caller 5
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*** END OF TEST 12 ***
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*** TIME TEST 13 ***
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rtems_message_queue_urgent: task readied -- preempts caller 13
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*** END OF TEST 13 ***
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*** TIME TEST 14 ***
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rtems_message_queue_urgent: task readied -- returns to caller 5
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*** END OF TEST 14 ***
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*** TIME TEST 15 ***
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rtems_event_receive: obtain current events 0
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rtems_event_receive: not available -- NO_WAIT 1
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rtems_event_receive: not available -- caller blocks 12
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rtems_event_send: no task readied 1
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rtems_event_receive: available 3
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rtems_event_send: task readied -- returns to caller 4
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*** END OF TEST 15 ***
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*** TIME TEST 16 ***
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rtems_event_send: task readied -- preempts caller 13
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*** END OF TEST 16 ***
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*** TIME TEST 17 ***
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rtems_task_set_priority: preempts caller 13
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*** END OF TEST 17 ***
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*** TIME TEST 18 ***
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rtems_task_delete: calling task 30
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*** END OF TEST 18 ***
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*** TIME TEST 19 ***
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rtems_signal_catch 2
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rtems_signal_send: returns to caller 5
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rtems_signal_send: signal to self 11
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exit ASR overhead: returns to calling task 6
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exit ASR overhead: returns to preempting task 11
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*** END OF TEST 19 ***
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*** TIME TEST 20 ***
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rtems_partition_create 15
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rtems_region_create 20
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rtems_partition_get_buffer: available 4
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rtems_partition_get_buffer: not available 1
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rtems_partition_return_buffer 4
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rtems_partition_delete 6
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rtems_region_get_segment: available 6
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rtems_region_get_segment: not available -- NO_WAIT 5
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rtems_region_return_segment: no waiting tasks 5
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rtems_region_get_segment: not available -- caller blocks 29
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rtems_region_return_segment: task readied -- preempts caller 29
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rtems_region_return_segment: task readied -- returns to caller 11
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rtems_region_delete 6
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rtems_io_initialize 0
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rtems_io_open 0
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rtems_io_close 0
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rtems_io_read 0
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rtems_io_write 0
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rtems_io_control 0
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*** END OF TEST 20 ***
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*** TIME TEST 21 ***
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rtems_task_ident 4
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rtems_message_queue_ident 3
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rtems_semaphore_ident 4
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rtems_partition_ident 3
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rtems_region_ident 3
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rtems_port_ident 3
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rtems_timer_ident 3
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rtems_rate_monotonic_ident 3
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*** END OF TEST 21 ***
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*** TIME TEST 22 ***
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rtems_message_queue_broadcast: task readied -- returns to caller 16
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rtems_message_queue_broadcast: no waiting tasks 2
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rtems_message_queue_broadcast: task readied -- preempts caller 12
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*** END OF TEST 22 ***
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*** TIME TEST 23 ***
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rtems_timer_create 2
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rtems_timer_fire_after: inactive 2
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rtems_timer_fire_after: active 1
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rtems_timer_cancel: active 1
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rtems_timer_cancel: inactive 1
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rtems_timer_reset: inactive 2
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rtems_timer_reset: active 2
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rtems_timer_fire_when: inactive 2
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rtems_timer_fire_when: active 2
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rtems_timer_delete: active 2
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rtems_timer_delete: inactive 2
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rtems_task_wake_when 13
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*** END OF TEST 23 ***
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*** TIME TEST 24 ***
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rtems_task_wake_after: yield -- returns to caller 0
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rtems_task_wake_after: yields -- preempts caller 9
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*** END OF TEST 24 ***
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*** TIME TEST 25 ***
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rtems_clock_tick 10
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*** END OF TEST 25 ***
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*** TIME TEST 26 ***
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_ISR_Disable 1
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_ISR_Flash 0
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_ISR_Enable 0
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_Thread_Disable_dispatch 0
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_Thread_Enable_dispatch 1
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_Thread_Set_state 4
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_Thread_Disptach (NO FP) 11
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context switch: no floating point contexts 5
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context switch: self 0
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context switch: to another task 1
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fp context switch: restore 1st FP task 5
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fp context switch: save idle, restore initialized 1
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fp context switch: save idle, restore idle 6
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fp context switch: save initialized, restore initialized 1
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_Thread_Resume 5
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_Thread_Unblock 3
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_Thread_Ready 2
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_Thread_Get 0
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_Semaphore_Get 0
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_Thread_Get: invalid id 0
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*** END OF TEST 26 ***
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*** TIME TEST 27 ***
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interrupt entry overhead: returns to interrupted task 1
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interrupt exit overhead: returns to interrupted task 1
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interrupt entry overhead: returns to nested interrupt 0
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interrupt exit overhead: returns to nested interrupt 0
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interrupt entry overhead: returns to preempting task 1
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interrupt exit overhead: returns to preempting task 9
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*** END OF TEST 27 ***
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*** TIME TEST 28 ***
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rtems_port_create 5
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rtems_port_external_to_internal 1
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rtems_port_internal_to_external 1
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rtems_port_delete 4
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*** END OF TEST 28 ***
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*** TIME TEST 29 ***
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rtems_rate_monotonic_create 8
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rtems_rate_monotonic_period: initiate period -- returns to caller 14
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rtems_rate_monotonic_period: obtain status 3
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rtems_rate_monotonic_cancel 6
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rtems_rate_monotonic_delete: inactive 7
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rtems_rate_monotonic_delete: active 3
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rtems_rate_monotonic_period: conclude periods -- caller blocks 15
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*** END OF TEST 29 ***
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*** TIME TEST OVERHEAD ***
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rtems_shutdown_executive 0
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rtems_task_create 0
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rtems_task_ident 0
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rtems_task_start 0
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rtems_task_restart 0
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rtems_task_delete 0
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rtems_task_suspend 0
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rtems_task_resume 0
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rtems_task_set_priority 0
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rtems_task_mode 0
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rtems_task_get_note 0
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rtems_task_set_note 0
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rtems_task_wake_when 0
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rtems_task_wake_after 0
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rtems_interrupt_catch 0
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rtems_clock_get 0
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rtems_clock_set 0
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rtems_clock_tick 0
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<pause>
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rtems_timer_create 0
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rtems_timer_delete 0
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rtems_timer_ident 0
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rtems_timer_fire_after 0
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rtems_timer_fire_when 0
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rtems_timer_reset 0
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rtems_timer_cancel 0
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rtems_semaphore_create 0
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rtems_semaphore_delete 0
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rtems_semaphore_ident 0
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rtems_semaphore_obtain 0
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rtems_semaphore_release 0
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rtems_message_queue_create 0
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rtems_message_queue_ident 0
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rtems_message_queue_delete 0
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rtems_message_queue_send 0
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rtems_message_queue_urgent 0
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rtems_message_queue_broadcast 0
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rtems_message_queue_receive 0
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rtems_message_queue_flush 0
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<pause>
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||||
rtems_event_send 0
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rtems_event_receive 0
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rtems_signal_catch 0
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rtems_signal_send 0
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rtems_partition_create 0
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rtems_partition_ident 0
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rtems_partition_delete 0
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rtems_partition_get_buffer 0
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rtems_partition_return_buffer 0
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rtems_region_create 0
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rtems_region_ident 0
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rtems_region_delete 0
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rtems_region_get_segment 0
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rtems_region_return_segment 0
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rtems_port_create 0
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||||
rtems_port_ident 0
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||||
rtems_port_delete 0
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||||
rtems_port_external_to_internal 0
|
||||
rtems_port_internal_to_external 0
|
||||
<pause>
|
||||
rtems_io_initialize 0
|
||||
rtems_io_open 0
|
||||
rtems_io_close 0
|
||||
rtems_io_read 0
|
||||
rtems_io_write 0
|
||||
rtems_io_control 0
|
||||
rtems_fatal_error_occurred 0
|
||||
rtems_rate_monotonic_create 0
|
||||
rtems_rate_monotonic_ident 0
|
||||
rtems_rate_monotonic_delete 0
|
||||
rtems_rate_monotonic_cancel 0
|
||||
rtems_rate_monotonic_period 0
|
||||
rtems_multiprocessing_announce 0
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*** END OF TIME OVERHEAD ***
|
||||
|
||||
|
||||
|
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@@ -40,18 +40,18 @@
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||||
#define CALLING_OVERHEAD_TASK_MODE 0
|
||||
#define CALLING_OVERHEAD_TASK_GET_NOTE 0
|
||||
#define CALLING_OVERHEAD_TASK_SET_NOTE 0
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0
|
||||
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
|
||||
#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
|
||||
#define CALLING_OVERHEAD_CLOCK_GET 1
|
||||
#define CALLING_OVERHEAD_CLOCK_SET 1
|
||||
#define CALLING_OVERHEAD_CLOCK_GET 0
|
||||
#define CALLING_OVERHEAD_CLOCK_SET 0
|
||||
#define CALLING_OVERHEAD_CLOCK_TICK 0
|
||||
|
||||
#define CALLING_OVERHEAD_TIMER_CREATE 0
|
||||
#define CALLING_OVERHEAD_TIMER_IDENT 0
|
||||
#define CALLING_OVERHEAD_TIMER_DELETE 0
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0
|
||||
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0
|
||||
#define CALLING_OVERHEAD_TIMER_RESET 0
|
||||
#define CALLING_OVERHEAD_TIMER_CANCEL 0
|
||||
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0
|
||||
|
||||
@@ -417,16 +417,10 @@ static void fec_rxDaemon(void *arg)
|
||||
struct ether_header *eh;
|
||||
int len = rxBd->length - sizeof(uint32_t);;
|
||||
|
||||
/*
|
||||
* Invalidate the cache and push the packet up.
|
||||
* The cache is so small that it's more efficient to just
|
||||
* invalidate the whole thing unless the packet is very small.
|
||||
*/
|
||||
m = sc->rxMbuf[rxBdIndex];
|
||||
if (len < 128)
|
||||
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
|
||||
else
|
||||
rtems_cache_invalidate_entire_data();
|
||||
|
||||
rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
|
||||
|
||||
m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
|
||||
eh = mtod(m, struct ether_header *);
|
||||
m->m_data += sizeof(struct ether_header);
|
||||
@@ -542,8 +536,12 @@ static void fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
|
||||
p = dest;
|
||||
sc->txRealign++;
|
||||
}
|
||||
|
||||
txBd->buffer = p;
|
||||
txBd->length = m->m_len;
|
||||
|
||||
rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
|
||||
|
||||
sc->txMbuf[sc->txBdHead] = m;
|
||||
nAdded++;
|
||||
if (++sc->txBdHead == sc->txBdCount) {
|
||||
|
||||
@@ -22,60 +22,7 @@
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <rtems/libio.h>
|
||||
#include <rtems/libcsupport.h>
|
||||
|
||||
/*
|
||||
* Cannot be frozen
|
||||
*/
|
||||
void _CPU_cache_freeze_data(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_unfreeze_data(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_freeze_instruction(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_unfreeze_instruction(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* Write-through data cache -- flushes are unnecessary
|
||||
*/
|
||||
void _CPU_cache_flush_1_data_line(const void *d_addr)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_flush_entire_data(void)
|
||||
{
|
||||
}
|
||||
|
||||
void _CPU_cache_enable_instruction(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_disable_instruction(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_invalidate_entire_instruction(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_invalidate_1_instruction_line(const void *addr)
|
||||
{
|
||||
}
|
||||
|
||||
void _CPU_cache_enable_data(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_disable_data(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_invalidate_entire_data(void)
|
||||
{
|
||||
}
|
||||
void _CPU_cache_invalidate_1_data_line(const void *addr)
|
||||
{
|
||||
}
|
||||
#include <rtems/rtems/cache.h>
|
||||
|
||||
/*
|
||||
* bsp_start
|
||||
@@ -84,6 +31,13 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
|
||||
*/
|
||||
void bsp_start(void)
|
||||
{
|
||||
/* cfinit invalidates cache and sets acr registers */
|
||||
|
||||
/*
|
||||
* Enable the cache, we only need to enable the instruction cache as the
|
||||
* 532x has a unified data and instruction cache.
|
||||
*/
|
||||
rtems_cache_enable_instruction();
|
||||
}
|
||||
|
||||
uint32_t bsp_get_CPU_clock_speed(void)
|
||||
|
||||
@@ -3,15 +3,16 @@
|
||||
* Initialisation Code for ColdFire MCF5329 Processor *
|
||||
**********************************************************************
|
||||
Generated by ColdFire Initialisation Utility 2.10.8
|
||||
Mon Jun 16 10:41:41 2008
|
||||
Wed Jul 02 14:26:25 2008
|
||||
|
||||
MicroAPL Ltd makes no warranties in respect of the suitability
|
||||
of this code for any particular purpose, and accepts
|
||||
no liability for any loss arising out of its use. The person or
|
||||
persons making use of this file must make the final evaluation
|
||||
as to its suitability and correctness for a particular application.
|
||||
|
||||
|
||||
$Id$
|
||||
|
||||
*/
|
||||
|
||||
/* External reference frequency is 16.0000 MHz
|
||||
@@ -37,19 +38,27 @@ static void disable_interrupts(void);
|
||||
static void disable_watchdog_timer(void);
|
||||
static void disable_cache(void);
|
||||
extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
|
||||
static void init_vbr(void);
|
||||
static void init_cache(void);
|
||||
static void init_crossbar(void);
|
||||
extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
|
||||
static void init_eport(void);
|
||||
static void init_flexcan(void);
|
||||
static void init_dma_timers(void);
|
||||
static void init_interrupt_timers(void);
|
||||
static void init_real_time_clock(void);
|
||||
static void init_watchdog_timers(void);
|
||||
static void init_edma(void);
|
||||
static void init_pin_assignments(void);
|
||||
extern void init_sdram_controller(void)
|
||||
extern void init_sdram_controller(void)
|
||||
__attribute__ ((section(".ram_code")));
|
||||
static void init_interrupt_controller(void);
|
||||
|
||||
/*********************************************************************
|
||||
* init_main - Main entry point for initialisation code *
|
||||
**********************************************************************/
|
||||
void init_main(void)
|
||||
{
|
||||
/* Mask all interrupts */
|
||||
init_clock_config();
|
||||
|
||||
/* Disable interrupts, watchdog timer, cache */
|
||||
@@ -58,13 +67,23 @@ void init_main(void)
|
||||
disable_cache();
|
||||
|
||||
/* Initialise individual modules */
|
||||
init_cache();
|
||||
init_crossbar();
|
||||
init_chip_selects();
|
||||
init_eport();
|
||||
init_flexcan();
|
||||
init_dma_timers();
|
||||
init_interrupt_timers();
|
||||
init_real_time_clock();
|
||||
init_watchdog_timers();
|
||||
init_edma();
|
||||
init_pin_assignments();
|
||||
|
||||
/* Initialise SDRAM controller (must be done after pin assignments) */
|
||||
init_sdram_controller();
|
||||
|
||||
/* Initialise interrupt controller */
|
||||
init_interrupt_controller();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
@@ -107,7 +126,6 @@ static void disable_cache(void)
|
||||
/*********************************************************************
|
||||
* init_clock_config - Clock Module *
|
||||
**********************************************************************/
|
||||
|
||||
void init_clock_config(void)
|
||||
{
|
||||
/* Clock module uses normal PLL mode with 16.0000 MHz external reference
|
||||
@@ -153,22 +171,124 @@ void init_clock_config(void)
|
||||
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_cache - Unified (Instruction and Data) Cache *
|
||||
**********************************************************************/
|
||||
static void init_cache(void)
|
||||
{
|
||||
/* ACR0: Cache accesses to 32 MB memory region at address $40000000
|
||||
CACR: Don't cache accesses to the rest of memory
|
||||
*/
|
||||
/*
|
||||
* Cache is enabled in bspstart.c
|
||||
*/
|
||||
#if 0
|
||||
asm("move.l #0xa0000600,%d0");
|
||||
asm("movec %d0,%CACR");
|
||||
#endif
|
||||
asm("move.l #0x4001c020,%d0");
|
||||
asm("movec %d0,%ACR0");
|
||||
asm("move.l #0x00000000,%d0");
|
||||
asm("movec %d0,%ACR1");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_crossbar - Cross-Bar Switch (XBS) Module *
|
||||
**********************************************************************/
|
||||
static void init_crossbar(void)
|
||||
{
|
||||
/* XBS settings for FlexBus/SDRAM Controller slave:
|
||||
Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
|
||||
*/
|
||||
MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
|
||||
MCF_XBS_PRS_M5(0x4) |
|
||||
MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
|
||||
MCF_XBS_CRS1 = 0;
|
||||
|
||||
/* XBS settings for SRAM Backdoor slave:
|
||||
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
|
||||
*/
|
||||
MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
|
||||
MCF_XBS_PRS_M5(0x4) |
|
||||
MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
|
||||
MCF_XBS_CRS4 = 0;
|
||||
|
||||
/* XBS settings for Cryptography Modules slave:
|
||||
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
|
||||
*/
|
||||
MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
|
||||
MCF_XBS_PRS_M5(0x4) |
|
||||
MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
|
||||
MCF_XBS_CRS6 = 0;
|
||||
|
||||
/* XBS settings for On-chip Peripherals slave:
|
||||
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
|
||||
*/
|
||||
MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
|
||||
MCF_XBS_PRS_M5(0x4) |
|
||||
MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
|
||||
MCF_XBS_CRS7 = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_chip_selects - Chip Select Module (FlexBus) *
|
||||
**********************************************************************/
|
||||
void init_chip_selects(void)
|
||||
{
|
||||
/* Chip Select 1 disabled (CSMR1[V] = 0) */
|
||||
MCF_FBCS1_CSMR = 0;
|
||||
|
||||
/* Chip Select 2 disabled (CSMR2[V] = 0) */
|
||||
MCF_FBCS2_CSMR = 0;
|
||||
|
||||
/* Chip Select 3 disabled (CSMR3[V] = 0) */
|
||||
MCF_FBCS3_CSMR = 0;
|
||||
|
||||
/* Chip Select 4 disabled (CSMR4[V] = 0) */
|
||||
MCF_FBCS4_CSMR = 0;
|
||||
|
||||
/* Chip Select 5 disabled (CSMR5[V] = 0) */
|
||||
MCF_FBCS5_CSMR = 0;
|
||||
|
||||
/* Chip Select 0: 2 MB of Flash at base address $00000000
|
||||
Port size = 16 bits
|
||||
Assert chip select on first rising clock edge after address is asserted
|
||||
Generate internal transfer acknowledge after 7 wait states
|
||||
Address is held for 1 clock at end of read and write cycles
|
||||
*/
|
||||
MCF_FBCS0_CSAR = 0;
|
||||
MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
|
||||
(0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
|
||||
MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_eport - Edge Port Module (EPORT) *
|
||||
**********************************************************************/
|
||||
static void init_eport(void)
|
||||
{
|
||||
/* Pins 1-7 configured as GPIO inputs */
|
||||
MCF_EPORT_EPPAR = 0;
|
||||
MCF_EPORT_EPDDR = 0;
|
||||
MCF_EPORT_EPIER = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_flexcan - FlexCAN Module *
|
||||
**********************************************************************/
|
||||
static void init_flexcan(void)
|
||||
{
|
||||
/* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
|
||||
MCF_CAN_IMASK = 0;
|
||||
MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
|
||||
MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
|
||||
MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
|
||||
MCF_CAN_CANCTRL = 0;
|
||||
MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
|
||||
MCF_CAN_CANMCR_FRZ |
|
||||
MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_sdram_controller - SDRAM Controller *
|
||||
**********************************************************************/
|
||||
@@ -259,6 +379,50 @@ void init_sdram_controller(void)
|
||||
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_dma_timers - DMA Timers *
|
||||
**********************************************************************/
|
||||
static void init_dma_timers(void)
|
||||
{
|
||||
/* DMA Timer 0 disabled (DTMR0[RST] = 0) */
|
||||
MCF_DTIM0_DTMR = 0;
|
||||
MCF_DTIM0_DTXMR = 0;
|
||||
MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
|
||||
|
||||
/* DMA Timer 1 disabled (DTMR1[RST] = 0) */
|
||||
MCF_DTIM1_DTMR = 0;
|
||||
MCF_DTIM1_DTXMR = 0;
|
||||
MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
|
||||
|
||||
/* DMA Timer 2 disabled (DTMR2[RST] = 0) */
|
||||
MCF_DTIM2_DTMR = 0;
|
||||
MCF_DTIM2_DTXMR = 0;
|
||||
MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
|
||||
|
||||
/* DMA Timer 3 disabled (DTMR3[RST] = 0) */
|
||||
MCF_DTIM3_DTMR = 0;
|
||||
MCF_DTIM3_DTXMR = 0;
|
||||
MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_interrupt_timers - Programmable Interrupt Timers (PIT) *
|
||||
**********************************************************************/
|
||||
static void init_interrupt_timers(void)
|
||||
{
|
||||
/* PIT0 disabled (PCSR0[EN]=0) */
|
||||
MCF_PIT0_PCSR = 0;
|
||||
|
||||
/* PIT1 disabled (PCSR1[EN]=0) */
|
||||
MCF_PIT1_PCSR = 0;
|
||||
|
||||
/* PIT2 disabled (PCSR2[EN]=0) */
|
||||
MCF_PIT2_PCSR = 0;
|
||||
|
||||
/* PIT3 disabled (PCSR3[EN]=0) */
|
||||
MCF_PIT3_PCSR = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_real_time_clock - Real-Time Clock (RTC) *
|
||||
**********************************************************************/
|
||||
@@ -278,11 +442,123 @@ static void init_watchdog_timers(void)
|
||||
processor is reset.
|
||||
*/
|
||||
MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
|
||||
MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
|
||||
|
||||
/* Core watchdog timer disabled */
|
||||
MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_edma - eDMA Controller *
|
||||
**********************************************************************/
|
||||
static void init_edma(void)
|
||||
{
|
||||
/* Associate eDMA channels 9-12 with SSI signals */
|
||||
MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
|
||||
|
||||
/* Configured for round-robin arbitration mode */
|
||||
MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
|
||||
|
||||
/* All error interrupts are disabled */
|
||||
MCF_EDMA_EEI = 0;
|
||||
|
||||
/* All DMA requests from peripherals are masked */
|
||||
MCF_EDMA_ERQ = 0;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_interrupt_controller - Interrupt Controller *
|
||||
**********************************************************************/
|
||||
static void init_interrupt_controller(void)
|
||||
{
|
||||
/* No interrupt sources configured */
|
||||
MCF_INTC1_ICR0 = 0;
|
||||
MCF_INTC1_ICR1 = 0;
|
||||
MCF_INTC1_ICR3 = 0;
|
||||
MCF_INTC1_ICR4 = 0;
|
||||
MCF_INTC1_ICR5 = 0;
|
||||
MCF_INTC1_ICR6 = 0;
|
||||
MCF_INTC1_ICR7 = 0;
|
||||
MCF_INTC1_ICR8 = 0;
|
||||
MCF_INTC1_ICR9 = 0;
|
||||
MCF_INTC1_ICR10 = 0;
|
||||
MCF_INTC1_ICR11 = 0;
|
||||
MCF_INTC1_ICR12 = 0;
|
||||
MCF_INTC1_ICR13 = 0;
|
||||
MCF_INTC1_ICR14 = 0;
|
||||
MCF_INTC1_ICR15 = 0;
|
||||
MCF_INTC1_ICR16 = 0;
|
||||
MCF_INTC1_ICR17 = 0;
|
||||
MCF_INTC1_ICR18 = 0;
|
||||
MCF_INTC1_ICR19 = 0;
|
||||
MCF_INTC1_ICR40 = 0;
|
||||
MCF_INTC1_ICR41 = 0;
|
||||
MCF_INTC1_ICR42 = 0;
|
||||
MCF_INTC1_ICR43 = 0;
|
||||
MCF_INTC1_ICR44 = 0;
|
||||
MCF_INTC1_ICR45 = 0;
|
||||
MCF_INTC1_ICR46 = 0;
|
||||
MCF_INTC1_ICR47 = 0;
|
||||
MCF_INTC1_ICR48 = 0;
|
||||
MCF_INTC1_ICR49 = 0;
|
||||
MCF_INTC1_ICR50 = 0;
|
||||
MCF_INTC1_ICR51 = 0;
|
||||
MCF_INTC1_ICR52 = 0;
|
||||
MCF_INTC1_ICR53 = 0;
|
||||
MCF_INTC0_ICR1 = 0;
|
||||
MCF_INTC0_ICR2 = 0;
|
||||
MCF_INTC0_ICR3 = 0;
|
||||
MCF_INTC0_ICR4 = 0;
|
||||
MCF_INTC0_ICR5 = 0;
|
||||
MCF_INTC0_ICR6 = 0;
|
||||
MCF_INTC0_ICR7 = 0;
|
||||
MCF_INTC0_ICR8 = 0;
|
||||
MCF_INTC0_ICR9 = 0;
|
||||
MCF_INTC0_ICR10 = 0;
|
||||
MCF_INTC0_ICR11 = 0;
|
||||
MCF_INTC0_ICR12 = 0;
|
||||
MCF_INTC0_ICR13 = 0;
|
||||
MCF_INTC0_ICR14 = 0;
|
||||
MCF_INTC0_ICR15 = 0;
|
||||
MCF_INTC0_ICR16 = 0;
|
||||
MCF_INTC0_ICR17 = 0;
|
||||
MCF_INTC0_ICR18 = 0;
|
||||
MCF_INTC0_ICR19 = 0;
|
||||
MCF_INTC0_ICR20 = 0;
|
||||
MCF_INTC0_ICR21 = 0;
|
||||
MCF_INTC0_ICR22 = 0;
|
||||
MCF_INTC0_ICR23 = 0;
|
||||
MCF_INTC0_ICR24 = 0;
|
||||
MCF_INTC0_ICR25 = 0;
|
||||
MCF_INTC0_ICR26 = 0;
|
||||
MCF_INTC0_ICR27 = 0;
|
||||
MCF_INTC0_ICR28 = 0;
|
||||
MCF_INTC0_ICR30 = 0;
|
||||
MCF_INTC0_ICR31 = 0;
|
||||
MCF_INTC0_ICR32 = 0;
|
||||
MCF_INTC0_ICR33 = 0;
|
||||
MCF_INTC0_ICR34 = 0;
|
||||
MCF_INTC0_ICR35 = 0;
|
||||
MCF_INTC0_ICR36 = 0;
|
||||
MCF_INTC0_ICR37 = 0;
|
||||
MCF_INTC0_ICR38 = 0;
|
||||
MCF_INTC0_ICR39 = 0;
|
||||
MCF_INTC0_ICR40 = 0;
|
||||
MCF_INTC0_ICR41 = 0;
|
||||
MCF_INTC0_ICR42 = 0;
|
||||
MCF_INTC0_ICR43 = 0;
|
||||
MCF_INTC0_ICR44 = 0;
|
||||
MCF_INTC0_ICR45 = 0;
|
||||
MCF_INTC0_ICR46 = 0;
|
||||
MCF_INTC0_ICR47 = 0;
|
||||
MCF_INTC0_ICR48 = 0;
|
||||
MCF_INTC0_ICR62 = 0;
|
||||
MCF_INTC0_IMRH = 0xffffffff;
|
||||
MCF_INTC0_IMRL = 0xffffffff;
|
||||
MCF_INTC1_IMRH = 0xffffffff;
|
||||
MCF_INTC1_IMRL = 0xffffffff;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* init_pin_assignments - Pin Assignment and General Purpose I/O *
|
||||
**********************************************************************/
|
||||
|
||||
@@ -134,7 +134,7 @@ SECTIONS
|
||||
{
|
||||
PROVIDE( _data_dest_start = . );
|
||||
PROVIDE( _copy_start = .);
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.gnu.linkonce.d*)
|
||||
*(.gcc_except_table*)
|
||||
*(.jcr)
|
||||
|
||||
Reference in New Issue
Block a user