Merged patch from David Fiddes <D.J.Fiddes@hw.ac.uk> to add ColdFire

specific register macros and correct code in rtems.s.
1998-08-01 14:40:51 +00:00
parent f177865318
commit 5ef4fae650
4 changed files with 33 additions and 3 deletions
--- a/c/src/exec/score/cpu/m68k/asm.h
+++ b/c/src/exec/score/cpu/m68k/asm.h
@@ -88,7 +88,15 @@
 #define sr  REG (sr)
 #define vbr REG (vbr)
 #define dfc REG (dfc)
-#define sfc REG(sfc)
+#define sfc REG (sfc)
+
+/* mcf52xx special regs */
+#define cacr    REG (cacr)
+#define acr0    REG (acr0)
+#define acr1    REG (acr1)
+#define rambar0 REG (rambar0)
+#define mbar    REG (mbar)
+

 #define fp0 REG (fp0)
 #define fp1 REG (fp1)
--- a/c/src/exec/score/cpu/m68k/rtems.s
+++ b/c/src/exec/score/cpu/m68k/rtems.s
@@ -39,8 +39,14 @@ SYM (RTEMS):
        moveal    SYM (_Entry_points), a0
        lsll      #2, d0
        addal     d0, a0
+
+#if (M68K_COLDFIRE_ARCH == 0)
        moveal    @(a0),a0
        jmpl      @(a0)
+#else
+        moveal    (a0),a0
+        jmpl      (a0)
+#endif

        END_CODE
 END
--- a/cpukit/score/cpu/m68k/asm.h
+++ b/cpukit/score/cpu/m68k/asm.h
@@ -88,7 +88,15 @@
 #define sr  REG (sr)
 #define vbr REG (vbr)
 #define dfc REG (dfc)
-#define sfc REG(sfc)
+#define sfc REG (sfc)
+
+/* mcf52xx special regs */
+#define cacr    REG (cacr)
+#define acr0    REG (acr0)
+#define acr1    REG (acr1)
+#define rambar0 REG (rambar0)
+#define mbar    REG (mbar)
+

 #define fp0 REG (fp0)
 #define fp1 REG (fp1)
--- a/cpukit/score/cpu/m68k/rtems/asm.h
+++ b/cpukit/score/cpu/m68k/rtems/asm.h
@@ -88,7 +88,15 @@
 #define sr  REG (sr)
 #define vbr REG (vbr)
 #define dfc REG (dfc)
-#define sfc REG(sfc)
+#define sfc REG (sfc)
+
+/* mcf52xx special regs */
+#define cacr    REG (cacr)
+#define acr0    REG (acr0)
+#define acr1    REG (acr1)
+#define rambar0 REG (rambar0)
+#define mbar    REG (mbar)
+

 #define fp0 REG (fp0)
 #define fp1 REG (fp1)