m68k/csb360: Fix warnings

This commit is contained in:
Joel Sherrill
2014-10-19 21:27:09 -05:00
parent 3d4898f74e
commit 4f21badbb9
3 changed files with 74 additions and 75 deletions

View File

@@ -178,6 +178,11 @@ rtems_isr_entry set_vector(
int type
);
/*
* Prototypes for BSP methods which cross file boundaries
*/
void init5272(void);
#ifdef __cplusplus
}
#endif

View File

@@ -5,7 +5,9 @@
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
*/
/*
* Copyright (C) 2004 Cogent Computer Systems
* Author: Jay Monkman <jtm@lopingdog.com>
*

View File

@@ -8,7 +8,9 @@
* This initialization code based on hardware settings of dBUG
* monitor. This must be changed if you like to run it immediately
* after reset.
*
*/
/*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
@@ -25,7 +27,6 @@
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems.h>
#include <bsp.h>
#include <mcf5272/mcf5272.h>
@@ -71,17 +72,10 @@ usb_regs_t *g_usb_regs = (void *) MCF5272_USB_BASE(BSP_MBAR);
"nop\n\t" \
: : "d" (MCF5272_CACR_CINV) )
/* init5272 --
/*
* Initialize MCF5272 on-chip modules
*
* PARAMETERS:
* none
*
* RETURNS:
* none
*/
void
init5272(void)
void init5272(void)
{
/* Invalidate the cache - WARNING: It won't complete for 64 clocks */
m68k_set_cacr(MCF5272_CACR_CINV);
@@ -113,8 +107,7 @@ init5272(void)
uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
uint32_t *intvec = (uint32_t *)BSP_RAMBAR;
register int i;
for (i = 0; i < 256; i++)
{
for (i = 0; i < 256; i++) {
*(intvec++) = *(inttab++);
}
}
@@ -125,7 +118,6 @@ init5272(void)
* Setup ACRs so that if cache turned on, periphal accesses
* are not messed up. (Non-cacheable, serialized)
*/
m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM) |
MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM) |
MCF5272_ACR_EN |