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m68k/av5282: Fix warning

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This commit is contained in:
Joel Sherrill
2014-10-19 21:21:06 -05:00
parent 8566e1fce5
commit 3d4898f74e
3 changed files with 58 additions and 49 deletions
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24
c/src/lib/libbsp/m68k/av5282/include/bsp.h
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@@ -10,9 +10,19 @@
* av5282 BSP header file
*/
/**
* @defgroup m68k_av5282 AV5282 Support
*
* @ingroup bsp_m68k
*
* @brief AV5282 support.
*/
#ifndef __SBav5282_BSP_H
#define __SBav5282_BSP_H
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
@@ -78,16 +88,14 @@ rtems_isr_entry set_vector(
#define UART2_IRQ_LEVEL 3
#define UART2_IRQ_PRIORITY 5
/*
* Prototypes for methods called from .S to alow dependency tracking
*/
void Init5282(void);
#ifdef __cplusplus
}
#endif
#endif /* !ASM */
#endif
/**
* @defgroup m68k_av5282 AV5282 Support
*
* @ingroup bsp_m68k
*
* @brief AV5282 support.
*/

7
c/src/lib/libbsp/m68k/av5282/start/start.S
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@@ -5,8 +5,10 @@
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*
* COPYRIGHT (c) 1989-1998.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -14,6 +16,7 @@
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>
#include <rtems/asm.h>
#define SRAM_SIZE (64*1024)

76
c/src/lib/libbsp/m68k/av5282/startup/init5282.c
View File

@@ -7,12 +7,15 @@
* work has been done by the bootstrap dBUG code.
*/
#include <rtems.h>
#include <bsp.h>
#define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
#define MM_SDRAM_BASE (0x00000000)
#define m68k_set_cacr(_cacr) \
__asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
#define m68k_set_acr0(_acr0) \
__asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
#define m68k_set_acr1(_acr1) \
__asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
#define MM_SDRAM_BASE (0x00000000)
/*
* External methods used by this file
@@ -41,49 +44,44 @@ void Init5282 (void)
MCF5282_CS0_CSMR = 0x007f0001;
MCF5282_CS0_CSCR =(((0xf)&0x0F)<<10)|(1<<8)|(0x80);
/*Setup the SDRAM */
for(x=0; x<20000; x++)
{
temp +=1;
}
MCF5282_SDRAMC_DCR = 0x00000239;
MCF5282_SDRAMC_DACR0 = 0x00001320;
MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
for(x=0; x<20000; x++)
{
temp +=1;
}
/* set ip ( bit 3 ) in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
/* init precharge */
*((short *)MM_SDRAM_BASE) = 0;
/* set RE in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00008000);
/* wait */
for(x=0; x<20000; x++)
{
temp +=1;
}
/* issue IMRS */
MCF5282_SDRAMC_DACR0 |= (0x00000040);
*((short *)MM_SDRAM_BASE) = 0x0000;
for(x=0; x<60000; x++)
{
temp +=1;
}
*((unsigned long*)MM_SDRAM_BASE)=0x12345678;
/*Setup the SDRAM */
for(x=0; x<20000; x++) {
temp +=1;
}
MCF5282_SDRAMC_DCR = 0x00000239;
MCF5282_SDRAMC_DACR0 = 0x00001320;
MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
for(x=0; x<20000; x++) {
temp +=1;
}
/* set ip ( bit 3 ) in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
/* init precharge */
*((short *)MM_SDRAM_BASE) = 0;
/* set RE in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00008000);
/* wait */
for(x=0; x<20000; x++) {
temp +=1;
}
/* issue IMRS */
MCF5282_SDRAMC_DACR0 |= (0x00000040);
*((short *)MM_SDRAM_BASE) = 0x0000;
for(x=0; x<60000; x++) {
temp +=1;
}
*((unsigned long*)MM_SDRAM_BASE)=0x12345678;
/* Copy the interrupt vector table to address 0x0 in SDRAM */
{
uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
uint32_t *intvec = (uint32_t *)0x0;
register int i;
for (i = 0; i < 256; i++)
{
for (i = 0; i < 256; i++) {
*(intvec++) = *(inttab++);
}
}
/*
/*
* Copy data, clear BSS and call boot_card()
*/
CopyDataClearBSSAndStart ();