or1k: Indent & comment fix in cache.c

* Fix indentation of variable declarations.

* Change commented-out asm -> __asm__ to meet c99 standard if
  uncommented.

c/src/lib/libcpu/or1k/shared/cache/cache.c

@@ -26,6 +26,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
   ISR_Level level;
 
   _ISR_Local_disable (level);
+
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
 
@@ -85,6 +86,7 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
@@ -95,6 +97,7 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
@@ -105,6 +108,7 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
@@ -115,6 +119,7 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
@@ -126,6 +131,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch
 (const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
@@ -137,6 +143,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate
 (const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
@@ -148,6 +155,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 (const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
@@ -160,11 +168,12 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_flush(d_addr);
 
-  //asm volatile("l.csync");
+  //__asm__ volatile("l.csync");
 
   _ISR_Local_enable(level);
 }
@@ -172,6 +181,7 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
 void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_data_block_invalidate(d_addr);
@@ -192,6 +202,7 @@ void _CPU_cache_unfreeze_data(void)
 void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
   ISR_Level level;
+
   _ISR_Local_disable (level);
 
   _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);