bsps: Rework cache manager implementation

The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file.  Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

* bsps/shared/cache

* bsps/@RTEMS_CPU@/shared/cache

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.

bsps/arm/shared/cache/cache-cp15.c

@@ -20,11 +20,8 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
-#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
-
 #include <libcpu/arm-cp15.h>
-#include "../include/arm-cache-l1.h"
+#include "cache-cp15.h"
 
 #define CPU_DATA_CACHE_ALIGNMENT 32
 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
@@ -184,4 +181,4 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_local_enable(level);
 }
 
-#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */
+#include "../../shared/cache/cacheimpl.h"

bsps/arm/shared/cache/cache-cp15.h

@@ -1,6 +1,4 @@
 /**
- * @file arm-cache-l1.h
- *
  * @ingroup arm_shared
  *
  * @brief Level 1 Cache definitions and functions.

bsps/arm/shared/cache/cache-l2c-310.c

@@ -1,6 +1,4 @@
 /**
- * @file cache_.h
- *
  * @ingroup L2C-310_cache
  *
  * @brief Cache definitions and functions.
@@ -53,9 +51,6 @@
  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
  */
 
-#ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H
-#define LIBBSP_ARM_SHARED_L2C_310_CACHE_H
-
 #include <assert.h>
 #include <bsp.h>
 #include <bsp/fatal.h>
@@ -63,11 +58,8 @@
 #include <rtems/rtems/intr.h>
 #include <bsp/arm-release-id.h>
 #include <bsp/arm-errata.h>
-#include "../include/arm-cache-l1.h"
 
-#ifdef __cplusplus
+#include "cache-cp15.h"
-extern "C" {
-#endif /* __cplusplus */
 
 /* These two defines also ensure that the rtems_cache_* functions have bodies */
 #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
@@ -1338,11 +1330,4 @@ _CPU_cache_get_instruction_cache_size( const uint32_t level )
   return size;
 }
 
-
+#include "../../shared/cache/cacheimpl.h"
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */

bsps/arm/shared/cache/cache-v7m.c

@@ -12,9 +12,6 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#ifndef LIBBSP_ARM_ARMV7M_CACHE__H
-#define LIBBSP_ARM_ARMV7M_CACHE__H
-
 #include <rtems.h>
 #include <chip.h>
 
@@ -141,4 +138,4 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-#endif /* LIBBSP_ARM_ARMV7M_CACHE__H */
+#include "../../shared/cache/cacheimpl.h"

bsps/bfin/shared/cache/cache.c

@@ -12,8 +12,16 @@
 #include <rtems.h>
 #include <bsp.h>
 #include <libcpu/memoryRegs.h>
-#include "cache_.h"
 
+#define CPU_DATA_CACHE_ALIGNMENT          32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT   32
+
+#ifdef BSP_DATA_CACHE_CONFIG
+#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
+#else
+/* use 16K of each SRAM bank */
+#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
+#endif
 
 /* There are many syncs in the following code because they should be
    harmless except for wasting time, and this is easier than figuring out
@@ -21,7 +29,7 @@
    buffers and queued reads.  Many of them are likely unnecessary. */
 
 
-void _CPU_cache_flush_1_data_line(const void *d_addr) {
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr));
 }
@@ -32,26 +40,26 @@ void _CPU_cache_flush_1_data_line(const void *d_addr) {
    okay since with a pure invalidate method the caller would have no
    way to insure the dirty line hadn't been written out anyway prior
    to the invalidate. */
-void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr));
 }
 
-void _CPU_cache_freeze_data(void) {
+static void _CPU_cache_freeze_data(void) {
 }
 
-void _CPU_cache_unfreeze_data(void) {
+static void _CPU_cache_unfreeze_data(void) {
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
+static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
 
   __asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr));
 }
 
-void _CPU_cache_freeze_instruction(void) {
+static void _CPU_cache_freeze_instruction(void) {
 }
 
-void _CPU_cache_unfreeze_instruction(void) {
+static void _CPU_cache_unfreeze_instruction(void) {
 }
 
 /* incredibly inefficient...  It would be better to make use of the
@@ -59,7 +67,7 @@ void _CPU_cache_unfreeze_instruction(void) {
    cache line and flush just those.  However the documentation I've
    seen on those is a bit sketchy, and I sure wouldn't want to get it
    wrong. */
-void _CPU_cache_flush_entire_data(void) {
+static void _CPU_cache_flush_entire_data(void) {
   uint32_t i;
 
   i = 0;
@@ -71,7 +79,7 @@ void _CPU_cache_flush_entire_data(void) {
   __asm__ __volatile__ ("ssync");
 }
 
-void _CPU_cache_invalidate_entire_data(void) {
+static void _CPU_cache_invalidate_entire_data(void) {
   uint32_t dmemControl;
 
   __asm__ __volatile__ ("ssync");
@@ -83,21 +91,21 @@ void _CPU_cache_invalidate_entire_data(void) {
 
 /* this does not actually enable data cache unless CPLBs are also enabled.
    LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */
-void _CPU_cache_enable_data(void) {
+static void _CPU_cache_enable_data(void) {
 
   __asm__ __volatile__ ("ssync");
   *(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG;
   __asm__ __volatile__ ("ssync");
 }
 
-void _CPU_cache_disable_data(void) {
+static void _CPU_cache_disable_data(void) {
 
   __asm__ __volatile__ ("ssync");
   *(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK;
   __asm__ __volatile__ ("ssync");
 }
 
-void _CPU_cache_invalidate_entire_instruction(void) {
+static void _CPU_cache_invalidate_entire_instruction(void) {
   uint32_t imemControl;
 
   __asm__ __volatile__ ("ssync");
@@ -109,17 +117,18 @@ void _CPU_cache_invalidate_entire_instruction(void) {
 
 /* this only actually enables the instruction cache if the CPLBs are also
    enabled. */
-void _CPU_cache_enable_instruction(void) {
+static void _CPU_cache_enable_instruction(void) {
 
   __asm__ __volatile__ ("ssync");
   *(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC;
   __asm__ __volatile__ ("ssync");
 }
 
-void _CPU_cache_disable_instruction(void) {
+static void _CPU_cache_disable_instruction(void) {
 
   __asm__ __volatile__ ("ssync");
   *(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC;
   __asm__ __volatile__ ("ssync");
 }
 
+#include "../../../shared/cache/cacheimpl.h"

bsps/i386/shared/cache/cache.c

@@ -3,10 +3,13 @@
  */
 
 #include <rtems.h>
-#include "cache_.h"
 #include <rtems/score/cpu.h>
 #include <libcpu/page.h>
 
+#define I386_CACHE_ALIGNMENT 16
+#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
+#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
+
 void _CPU_disable_cache(void)
 {
   unsigned int regCr0;
@@ -44,45 +47,47 @@ void _CPU_enable_cache(void)
  */
 
 #if defined(I386_CACHE_ALIGNMENT)
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {}
-void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
+static void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {}
-void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
 
-void _CPU_cache_flush_entire_data(void)
+static void _CPU_cache_flush_entire_data(void)
 {
   __asm__ volatile ("wbinvd");
 }
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   __asm__ volatile ("invd");
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
         _CPU_enable_cache();
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
         _CPU_disable_cache();
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   __asm__ volatile ("invd");
 }
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   _CPU_enable_cache();
 }
 
-void _CPU_cache_disable_instruction( void )
+static void _CPU_cache_disable_instruction( void )
 {
   _CPU_disable_cache();
 }
 #endif
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/genmcf548x/start/cache.c

@@ -12,10 +12,6 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-
-#ifndef LIBBSP_M68K_GENMCF548X_CACHE_H
-#define LIBBSP_M68K_GENMCF548X_CACHE_H
-
 #include <bsp.h>
 
 #define CPU_DATA_CACHE_ALIGNMENT 16
@@ -114,4 +110,4 @@ static inline void _CPU_cache_flush_entire_data( void)
   }
 }
 
-#endif /* LIBBSP_M68K_GENMCF548X_CACHE_H */
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache-mcf5223x.c

@@ -0,0 +1,38 @@
+/*
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <mcf5223x/mcf5223x.h>
+#include "cache.h"
+
+/*
+ * Cannot be frozen
+ */
+static void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
+
+/*
+ * Write-through data cache -- flushes are unnecessary
+ */
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_entire_data(void) {}
+
+static void _CPU_cache_enable_instruction(void) {}
+static void _CPU_cache_disable_instruction(void) {}
+static void _CPU_cache_invalidate_entire_instruction(void) {}
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr) {}
+
+static void _CPU_cache_enable_data(void) {}
+static void _CPU_cache_disable_data(void) {}
+static void _CPU_cache_invalidate_entire_data(void) {}
+static void _CPU_cache_invalidate_1_data_line(const void *addr) {}
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache-mcf5225x.c

@@ -0,0 +1,34 @@
+/**
+ *  @file
+ *
+ *  Cache Management Support Routines for the MCF5225x
+ */
+
+#include <rtems.h>
+#include "cache.h"
+
+/*
+ * Cannot be frozen
+ */
+static void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
+
+/*
+ * Write-through data cache -- flushes are unnecessary
+ */
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_entire_data(void) {}
+
+static void _CPU_cache_enable_instruction(void) {}
+static void _CPU_cache_disable_instruction(void) {}
+static void _CPU_cache_invalidate_entire_instruction(void) {}
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr) {}
+
+static void _CPU_cache_enable_data(void) {}
+static void _CPU_cache_disable_data(void) {}
+static void _CPU_cache_invalidate_entire_data(void) {}
+static void _CPU_cache_invalidate_1_data_line(const void *addr) {}
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache-mcf5235.c

@@ -9,7 +9,7 @@
 
 #include <rtems.h>
 #include <mcf5235/mcf5235.h>
-#include "cache_.h"
+#include "cache.h"
 
 /*
  *  Default value for the cacr is set by the BSP
@@ -19,18 +19,18 @@ extern uint32_t cacr_mode;
 /*
  * Cannot be frozen
  */
-void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
 
 /*
  * Write-through data cache -- flushes are unnecessary
  */
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_flush_entire_data(void) {}
+static void _CPU_cache_flush_entire_data(void) {}
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
     rtems_interrupt_level level;
 
@@ -40,7 +40,7 @@ void _CPU_cache_enable_instruction(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
     rtems_interrupt_level level;
 
@@ -50,12 +50,12 @@ void _CPU_cache_disable_instruction(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
 {
     /*
      * Top half of cache is I-space
@@ -64,7 +64,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
     rtems_interrupt_level level;
 
@@ -74,7 +74,7 @@ void _CPU_cache_enable_data(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
     rtems_interrupt_level level;
 
@@ -84,12 +84,12 @@ void _CPU_cache_disable_data(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *addr)
+static void _CPU_cache_invalidate_1_data_line(const void *addr)
 {
     /*
      * Bottom half of cache is D-space
@@ -97,3 +97,5 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
     addr = (void *)((int)addr & ~0x400);
     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache-mcf5282.c

@@ -6,7 +6,7 @@
 
 #include <rtems.h>
 #include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
-#include "cache_.h"
+#include "cache.h"
 
 /*
  * CPU-space access
@@ -40,18 +40,18 @@ void mcf5xxx_initialize_cacr(uint32_t cacr)
 /*
  * Cannot be frozen
  */
-void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
 
 /*
  * Write-through data cache -- flushes are unnecessary
  */
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_flush_entire_data(void) {}
+static void _CPU_cache_flush_entire_data(void) {}
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -62,7 +62,7 @@ void _CPU_cache_enable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -72,13 +72,13 @@ void _CPU_cache_disable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
   NOP;
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
 {
   /*
    * Top half of cache is I-space
@@ -87,7 +87,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
   rtems_interrupt_level level;
 
@@ -97,7 +97,7 @@ void _CPU_cache_enable_data(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
   rtems_interrupt_level level;
 
@@ -107,12 +107,12 @@ void _CPU_cache_disable_data(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *addr)
+static void _CPU_cache_invalidate_1_data_line(const void *addr)
 {
   /*
    * Bottom half of cache is D-space
@@ -120,3 +120,5 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
   addr = (void *)((int)addr & ~0x400);
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache-mcf532x.c

@@ -6,7 +6,7 @@
 
 #include <rtems.h>
 #include <mcf532x/mcf532x.h>
-#include "cache_.h"
+#include "cache.h"
 
 #define m68k_set_cacr(_cacr) \
   __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
@@ -23,23 +23,23 @@ static uint32_t cacr_mode = MCF_CACR_ESB |
 /*
  * Cannot be frozen
  */
-void _CPU_cache_freeze_data(void)
+static void _CPU_cache_freeze_data(void)
 {
 }
 
-void _CPU_cache_unfreeze_data(void)
+static void _CPU_cache_unfreeze_data(void)
 {
 }
 
-void _CPU_cache_freeze_instruction(void)
+static void _CPU_cache_freeze_instruction(void)
 {
 }
 
-void _CPU_cache_unfreeze_instruction(void)
+static void _CPU_cache_unfreeze_instruction(void)
 {
 }
 
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+static void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
   register unsigned long adr = (((unsigned long) d_addr >> 4) & 0xff) << 4;
 
@@ -52,7 +52,7 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
 }
 
-void _CPU_cache_flush_entire_data(void)
+static void _CPU_cache_flush_entire_data(void)
 {
   register unsigned long set, adr;
 
@@ -68,7 +68,7 @@ void _CPU_cache_flush_entire_data(void)
   }
 }
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -81,7 +81,7 @@ void _CPU_cache_enable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -94,12 +94,12 @@ void _CPU_cache_disable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   m68k_set_cacr(cacr_mode | MCF_CACR_CINVA);
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
 {
   register unsigned long adr = (((unsigned long) addr >> 4) & 0xff) << 4;
 
@@ -112,7 +112,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (adr));
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
   /*
    * The 532x has a unified data and instruction cache, so we call through
@@ -121,7 +121,7 @@ void _CPU_cache_enable_data(void)
   _CPU_cache_enable_instruction();
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
   /*
    * The 532x has a unified data and instruction cache, so we call through
@@ -130,12 +130,14 @@ void _CPU_cache_disable_data(void)
   _CPU_cache_disable_instruction();
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   _CPU_cache_invalidate_entire_instruction();
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *addr)
+static void _CPU_cache_invalidate_1_data_line(const void *addr)
 {
   _CPU_cache_invalidate_1_instruction_line(addr);
 }
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache.c

@@ -0,0 +1,3 @@
+#include <rtems.h>
+#include "cache.h"
+#include "../../../shared/cache/cacheimpl.h"

bsps/m68k/shared/cache/cache.h

@@ -1,9 +1,35 @@
 /*
- *  Cache Management Support Routines for the MC68040
+ *  M68K Cache Manager Support
  */
 
-#include <rtems.h>
+#if (defined(__mc68020__) && !defined(__mcpu32__))
-#include "cache_.h"
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+#elif defined(__mc68030__)
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# define M68K_DATA_CACHE_ALIGNMENT 16
+#elif ( defined(__mc68040__) || defined (__mc68060__) )
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# define M68K_DATA_CACHE_ALIGNMENT 16
+#elif ( defined(__mcf5200__) )
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# if ( defined(__mcf528x__) )
+#  define M68K_DATA_CACHE_ALIGNMENT 16
+# endif
+#elif ( defined(__mcf5300__) )
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# define M68K_DATA_CACHE_ALIGNMENT 16
+#elif defined(__mcfv4e__)
+# define M68K_INSTRUCTION_CACHE_ALIGNMENT 16
+# define M68K_DATA_CACHE_ALIGNMENT 16
+#endif
+
+#if defined(M68K_DATA_CACHE_ALIGNMENT)
+#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
+#endif
+
+#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT)
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT
+#endif
 
 /*
  *  Since the cacr is common to all mc680x0, provide macros
@@ -187,4 +213,3 @@ void _CPU_cache_disable_instruction ( void )
 	_CPU_CACR_AND( 0xFFFF7FFF );
 }
 #endif
-/* end of file */

bsps/or1k/headers.am

@@ -2,5 +2,4 @@
 
 include_bspdir = $(includedir)/bsp
 include_bsp_HEADERS =
-include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/cache_.h
 include_bsp_HEADERS += ../../../../../bsps/or1k/include/bsp/linker-symbols.h

bsps/or1k/include/bsp/cache_.h

@@ -1,43 +0,0 @@
-/*
- * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_OR1K_SHARED_CACHE_H
-#define LIBBSP_OR1K_SHARED_CACHE_H
-
-#include <assert.h>
-#include <bsp.h>
-#include <rtems/rtems/intr.h>
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/* These two defines also ensure that the rtems_cache_* functions have bodies */
-#define CPU_DATA_CACHE_ALIGNMENT        32
-#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
-
-#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
-
-static inline size_t
-_CPU_cache_get_data_cache_size( const uint32_t level )
-{
-  return (level == 0 || level == 1)? 8192 : 0;
-}
-
-static inline size_t
-_CPU_cache_get_instruction_cache_size( const uint32_t level )
-{
-  return (level == 0 || level == 1)? 8192 : 0;
-}
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_OR1K_SHARED_CACHE_H */

bsps/or1k/shared/cache/cache.c

@@ -18,7 +18,24 @@
 #include <rtems/score/interr.h>
 #include <rtems/score/or1k-utility.h>
 #include <rtems/score/percpu.h>
-#include "cache_.h"
+
+#define CPU_DATA_CACHE_ALIGNMENT        32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1
+#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
+
+static inline size_t
+_CPU_cache_get_data_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
+
+static inline size_t
+_CPU_cache_get_instruction_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
 
 static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 {
@@ -79,7 +96,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 
 /* Implement RTEMS cache manager functions */
 
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+static void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -92,7 +109,7 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -103,17 +120,17 @@ void _CPU_cache_invalidate_1_data_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_freeze_data(void)
+static void _CPU_cache_freeze_data(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_unfreeze_data(void)
+static void _CPU_cache_unfreeze_data(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -124,17 +141,17 @@ void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_freeze_instruction(void)
+static void _CPU_cache_freeze_instruction(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_unfreeze_instruction(void)
+static void _CPU_cache_unfreeze_instruction(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_flush_entire_data(void)
+static void _CPU_cache_flush_entire_data(void)
 {
   size_t addr;
   ISR_Level level;
@@ -153,7 +170,7 @@ void _CPU_cache_flush_entire_data(void)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   size_t addr;
   ISR_Level level;
@@ -172,7 +189,7 @@ void _CPU_cache_invalidate_entire_data(void)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   size_t addr;
   ISR_Level level;
@@ -205,7 +222,7 @@ void _CPU_cache_invalidate_entire_instruction(void)
  * cache line operation.
  */
 
-void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
+static void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -242,7 +259,7 @@ void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
+static void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -279,7 +296,7 @@ void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
+static void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -316,7 +333,7 @@ void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -329,7 +346,7 @@ void _CPU_cache_enable_data(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -342,7 +359,7 @@ void _CPU_cache_disable_data(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -355,7 +372,7 @@ void _CPU_cache_enable_instruction(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -367,3 +384,5 @@ void _CPU_cache_disable_instruction(void)
 
   _ISR_Local_enable(level);
 }
+
+#include "../../../shared/cache/cacheimpl.h"

bsps/powerpc/shared/cache/cache.c

@@ -12,9 +12,6 @@
  * Surrey Satellite Technology Limited (SSTL), 2001
  */
 
-#ifndef LIBCPU_POWERPC_CACHE_H
-#define LIBCPU_POWERPC_CACHE_H
-
 #include <rtems.h>
 #include <rtems/powerpc/powerpc.h>
 #include <rtems/powerpc/registers.h>
@@ -319,4 +316,4 @@ static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
   __asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory");
 }
 
-#endif /* LIBCPU_POWERPC_CACHE_H */
+#include "../../../bsps/shared/cache/cacheimpl.h"

bsps/shared/cache/cacheimpl.h

@@ -40,7 +40,6 @@
  */
 
 #include <rtems.h>
-#include "cache_.h"
 
 #if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES
 #error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"

bsps/shared/cache/nocache.c

@@ -0,0 +1 @@
+#include "cacheimpl.h"

bsps/sparc/leon2/start/cache.c

@@ -2,9 +2,6 @@
  *  SPARC Cache Manager Support
  */
 
-#ifndef __SPARC_CACHE_h
-#define __SPARC_CACHE_h
-
 /*
  * CACHE MANAGER: The following functions are CPU-specific.
  * They provide the basic implementation for the rtems_* cache
@@ -14,8 +11,7 @@
  * FIXME: Some functions simply have not been implemented.
  */
 
-/* This define is set in a Makefile */
+#include <stddef.h>
-#if defined(HAS_INSTRUCTION_CACHE)
 
 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 0
 
@@ -52,7 +48,4 @@ static inline void _CPU_cache_disable_instruction (   void )
 {
 }
 
-#endif /* defined(HAS_INSTRUCTION_CACHE) */
+#include "../../../shared/cache/cacheimpl.h"
-
-#endif
-/* end of include file */

bsps/sparc/leon3/start/cache.c

@@ -12,16 +12,9 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#ifndef LEON3_CACHE_H
-#define LEON3_CACHE_H
-
 #include <amba.h>
 #include <leon.h>
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
@@ -195,8 +188,4 @@ static inline void _CPU_cache_disable_instruction(void)
   /* TODO */
 }
 
-#ifdef __cplusplus
+#include "../../../shared/cache/cacheimpl.h"
-}
-#endif /* __cplusplus */
-
-#endif /* LEON3_CACHE_H */

c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am

@@ -52,7 +52,6 @@ noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
 libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # for the Altera hwlib
 libbsp_a_CPPFLAGS += -I${srcdir}/hwlib/include
@@ -133,10 +132,7 @@ libbsp_a_SOURCES += ../../shared/tod.c
 libbsp_a_SOURCES += rtc/rtc.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
 
 ###############################################################################
 #                  Special Rules                                              #

c/src/lib/libbsp/arm/atsam/Makefile.am

@@ -136,9 +136,7 @@ libbsp_a_SOURCES += clock/systick-freq.c
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-v7m.c
-libbsp_a_SOURCES += ../shared/armv7m/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv7m/include
 
 # Network
 if HAS_NETWORKING

c/src/lib/libbsp/arm/beagle/Makefile.am

@@ -36,7 +36,6 @@ dist_project_lib_DATA += startup/linkcmds.beagle
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
 libbsp_a_LIBADD =
 
 # Shared
@@ -97,10 +96,7 @@ libbsp_a_SOURCES += clock.c
 libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 ###############################################################################
 #                  Special Rules                                              #

c/src/lib/libbsp/arm/csb336/Makefile.am

@@ -6,8 +6,6 @@ include $(top_srcdir)/../../bsp.am
 
 dist_project_lib_DATA = startup/bsp_specs
 
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-
 DISTCLEANFILES = include/bspopts.h
 noinst_PROGRAMS =
 
@@ -45,10 +43,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/lan91c11x.c

c/src/lib/libbsp/arm/csb337/Makefile.am

@@ -9,8 +9,6 @@ dist_project_lib_DATA = startup/bsp_specs
 if ENABLE_LCD
 endif
 
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-
 if ENABLE_UMON
 endif
 
@@ -76,10 +74,7 @@ libbsp_a_SOURCES += ../../shared/umon/umoncons.c
 endif
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c

c/src/lib/libbsp/arm/edb7312/Makefile.am

@@ -50,9 +50,7 @@ libbsp_a_SOURCES += irq/irq.c
 libbsp_a_SOURCES += irq/bsp_irq_asm.S
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c

c/src/lib/libbsp/arm/gdbarmsim/Makefile.am

@@ -50,9 +50,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-server.c
 libbsp_a_SOURCES += ../../shared/src/irq-shell.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 #libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
 #    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock.rel \

c/src/lib/libbsp/arm/gumstix/Makefile.am

@@ -46,9 +46,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-shell.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 if ON_SKYEYE
 libbsp_a_SOURCES += fb/fb.c

c/src/lib/libbsp/arm/imx/Makefile.am

@@ -29,8 +29,6 @@ dist_project_lib_DATA += startup/linkcmds.imx7
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -76,10 +74,7 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
 libbsp_a_SOURCES += ../shared/arm-generic-timer-clock-config.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 # I2C
 libbsp_a_SOURCES += i2c/imx-i2c.c

c/src/lib/libbsp/arm/lm3s69xx/Makefile.am

@@ -31,8 +31,6 @@ dist_project_lib_DATA += startup/linkcmds.lm3s6965_qemu
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -81,9 +79,7 @@ libbsp_a_SOURCES += ../shared/armv7m/clock/armv7m-clock-config.c
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
 # SSI
 libbsp_a_SOURCES += ssi/ssi.c

c/src/lib/libbsp/arm/lpc176x/Makefile.am

@@ -40,8 +40,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc1768_mbed_ahb_ram_eth
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -114,9 +112,7 @@ libbsp_a_SOURCES += misc/restart.c
 libbsp_a_SOURCES += watchdog/watchdog.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/lpc24xx/Makefile.am

@@ -49,8 +49,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc40xx_ea_rom_int
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c \
@@ -121,9 +119,7 @@ libbsp_a_SOURCES += ../shared/arm-pl111-fb.c
 libbsp_a_SOURCES += startup/fb-config.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/lpc32xx/Makefile.am

@@ -40,8 +40,6 @@ dist_project_lib_DATA += startup/linkcmds.lpc32xx_mzx
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -103,11 +101,7 @@ libbsp_a_SOURCES += misc/idle-thread.c
 # I2C
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
-
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/raspberrypi/Makefile.am

@@ -114,10 +114,7 @@ libbsp_a_SOURCES += i2c/i2c.c
 libbsp_a_SOURCES += spi/spi.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../shared/armv467ar-basic-cache
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

@@ -37,8 +37,6 @@ dist_project_lib_DATA += startup/linkcmds.realview_pbx_a9_qemu_smp
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -85,10 +83,7 @@ libbsp_a_SOURCES += ../../shared/clockdrv_shell.h
 libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c

c/src/lib/libbsp/arm/rtl22xx/Makefile.am

@@ -49,9 +49,7 @@ libbsp_a_SOURCES += irq/irq.c
 libbsp_a_SOURCES += console/uart.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c

c/src/lib/libbsp/arm/smdk2410/Makefile.am

@@ -6,8 +6,6 @@ include $(top_srcdir)/../../bsp.am
 
 dist_project_lib_DATA = startup/bsp_specs
 
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-
 DISTCLEANFILES = include/bspopts.h
 
 EXTRA_DIST += start/start.S
@@ -58,10 +56,7 @@ libbsp_a_SOURCES += smc/smc.c
 libbsp_a_SOURCES += smc/smc.h
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache
 
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel
 

c/src/lib/libbsp/arm/stm32f4/Makefile.am

@@ -30,8 +30,6 @@ dist_project_lib_DATA += startup/linkcmds.stm32f4
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -85,9 +83,7 @@ libbsp_a_SOURCES += ../shared/armv7m/clock/armv7m-clock-config.c
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/cache/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
 ###############################################################################
 #                  Special Rules                                              #

c/src/lib/libbsp/arm/tms570/Makefile.am

@@ -39,8 +39,6 @@ dist_project_lib_DATA += startup/linkcmds.tms570ls3137_hdk_with_loader
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -96,9 +94,7 @@ libbsp_a_SOURCES += misc/cpucounterread.c
 # Watchdog
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../../libcpu/arm/shared/include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
 
 if TMS570_USE_HWINIT_STARTUP
 libbsp_a_SOURCES += hwinit/tms570_sys_core.S

c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am

@@ -35,8 +35,6 @@ project_lib_DATA += linkcmds
 noinst_LIBRARIES = libbsp.a
 
 libbsp_a_SOURCES =
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS)
-libbsp_a_LIBADD =
 
 # Shared
 libbsp_a_SOURCES += ../../shared/bootcard.c
@@ -84,10 +82,7 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
 libbsp_a_SOURCES += i2c/cadence-i2c.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-l2c-310.c
-libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
-libbsp_a_SOURCES += ../shared/arm-l2c-310/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/arm-l2c-310
 
 # Start hooks
 libbsp_a_SOURCES += startup/bspstarthooks.c startup/bspstartmmu.c

c/src/lib/libbsp/bfin/TLL6527M/Makefile.am

@@ -29,10 +29,10 @@ libbsp_a_SOURCES = \
 libbsp_a_SOURCES += ../../shared/bspreset.c
 
 libbsp_a_SOURCES += console/console.c
+libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/mmu.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/interrupt.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

c/src/lib/libbsp/bfin/bf537Stamp/Makefile.am

@@ -30,6 +30,7 @@ libbsp_a_SOURCES += \
 libbsp_a_SOURCES += ../../shared/bspreset.c
 
 libbsp_a_SOURCES += console/console.c
+libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/networkconfig.c
@@ -37,7 +38,6 @@ endif
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/mmu.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/interrupt.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

c/src/lib/libbsp/bfin/eZKit533/Makefile.am

@@ -30,10 +30,10 @@ libbsp_a_SOURCES += \
 libbsp_a_SOURCES += ../../shared/bspreset.c
 
 libbsp_a_SOURCES += console/console-io.c
+libbsp_a_SOURCES += ../../../../../../bsps/bfin/shared/cache/cache.c
 
 libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/mmu.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/interrupt.rel
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/cache.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/uart.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/clock.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rtc.rel

c/src/lib/libbsp/epiphany/epiphany_sim/Makefile.am

@@ -62,9 +62,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 # debugio
 libbsp_a_SOURCES += console/console-io.c

c/src/lib/libbsp/i386/pc386/Makefile.am

@@ -170,8 +170,9 @@ libbsp_a_SOURCES += ne2000/ne2000.c
 libbsp_a_SOURCES += wd8003/wd8003.c
 endif
 
-libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/i386/shared/cache/cache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/page.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/page.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/score.rel
 
 if HAS_SMP

c/src/lib/libbsp/lm32/lm32_evr/Makefile.am

@@ -41,9 +41,7 @@ libbsp_a_SOURCES += ../../lm32/shared/console/uart.c
 libbsp_a_SOURCES += ../../lm32/shared/timer/timer.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += ../../lm32/shared/tsmac/tsmac.c

c/src/lib/libbsp/lm32/milkymist/Makefile.am

@@ -88,9 +88,7 @@ libbsp_a_SOURCES += ../../lm32/shared/milkymist_video/video.c
 libbsp_a_SOURCES += ../../lm32/shared/milkymist_versions/versions.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += ../../lm32/shared/milkymist_networking/network.c

c/src/lib/libbsp/m32c/m32cbsp/Makefile.am

@@ -34,9 +34,7 @@ libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
     $(timer_SOURCES)
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/m32c/m32cbsp/headers.am

c/src/lib/libbsp/m68k/av5282/Makefile.am

@@ -40,9 +40,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5282.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
-    ../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/csb360/Makefile.am

@@ -34,9 +34,7 @@ libbsp_a_SOURCES += ../../shared/bspreset.c
 libbsp_a_SOURCES += console/console-io.c ../../shared/console-polled.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \

c/src/lib/libbsp/m68k/gen68340/Makefile.am

@@ -37,8 +37,9 @@ libbsp_a_SOURCES += console/console.c console/m340uart.c \
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/gen68360/Makefile.am

@@ -42,8 +42,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 if HAS_FPSP
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel

c/src/lib/libbsp/m68k/genmcf548x/Makefile.am

@@ -49,9 +49,7 @@ libbsp_a_SOURCES += irq/irq.c
 libbsp_a_SOURCES += irq/intc-icr-init-values.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/genmcf548x/start/cache.c
-libbsp_a_SOURCES += ../include/cache_.h
-libbsp_a_CPPFLAGS += -I$(srcdir)/include
 
 if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c

c/src/lib/libbsp/m68k/mcf5206elite/Makefile.am

@@ -44,9 +44,7 @@ libbsp_a_SOURCES += tod/ds1307.c tod/todcfg.c ../../shared/tod.c
 libbsp_a_SOURCES += nvram/nvram.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \

c/src/lib/libbsp/m68k/mcf52235/Makefile.am

@@ -38,9 +38,9 @@ libbsp_a_SOURCES += console/debugio.c
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5223x.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
-    ../../../libcpu/@RTEMS_CPU@/mcf5223x/cachepd.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/mcf5225x/Makefile.am

@@ -33,9 +33,9 @@ libbsp_a_SOURCES += console/console.c
 libbsp_a_SOURCES += console/debugio.c
 libbsp_a_SOURCES += timer/timer.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5225x.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
-    ../../../libcpu/@RTEMS_CPU@/mcf5225x/cachepd.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/mcf5235/Makefile.am

@@ -42,9 +42,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5235.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
-    ../../../libcpu/@RTEMS_CPU@/mcf5235/cachepd.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/mcf5329/Makefile.am

@@ -41,10 +41,10 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf532x.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
+    ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
-    ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
-    ../../../libcpu/@RTEMS_CPU@/mcf532x/cachepd.rel
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/m68k/mcf5329/headers.am

c/src/lib/libbsp/m68k/mrm332/Makefile.am

@@ -38,8 +38,9 @@ libbsp_a_SOURCES += spurious/spinit.c
 # timer
 libbsp_a_SOURCES += timer/timer.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/m68k/mvme147/Makefile.am

@@ -37,8 +37,9 @@ libbsp_a_SOURCES += console/console.c ../../shared/dummy_printk_support.c
 # timer
 libbsp_a_SOURCES += timer/timer.c timer/timerisr.S
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 EXTRA_DIST += times

c/src/lib/libbsp/m68k/mvme147s/Makefile.am

@@ -45,8 +45,9 @@ libbsp_a_SOURCES += shmsupp/addrconv.c shmsupp/getcfg.c shmsupp/lock.c \
     shmsupp/mpisr.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 EXTRA_DIST += times

c/src/lib/libbsp/m68k/mvme162/Makefile.am

@@ -44,8 +44,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += ../mvme167/network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 if HAS_FPSP
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel

c/src/lib/libbsp/m68k/mvme167/Makefile.am

@@ -41,8 +41,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/misc.rel \
     ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/fpsp.rel
 

c/src/lib/libbsp/m68k/uC5282/Makefile.am

@@ -39,9 +39,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
-libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
+libbsp_a_SOURCES += ../../../../../../bsps/m68k/shared/cache/cache-mcf5282.c
-    ../../../libcpu/@RTEMS_CPU@/mcf5282/cachepd.rel \
+
-    ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/misc.rel
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/m68k/uC5282/headers.am

c/src/lib/libbsp/mips/csb350/Makefile.am

@@ -53,8 +53,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c
 endif
 
-libbsp_a_LIBADD  = ../../../libcpu/mips/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/mips/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/mips/shared/interrupts.rel
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/mips/csb350/headers.am

c/src/lib/libbsp/mips/hurricane/Makefile.am

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
 libbsp_a_SOURCES += irq/vectorisrs.c
 libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
-libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/rm52xx/timer.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/jmr3904/Makefile.am

@@ -47,8 +47,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
 libbsp_a_SOURCES += irq/vectorisrs.c
 libbsp_a_SOURCES += ../shared/irq/interruptmask.c
 
-libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/mips/jmr3904/headers.am

c/src/lib/libbsp/mips/malta/Makefile.am

@@ -54,8 +54,9 @@ libbsp_a_SOURCES += ../../shared/console_control.c
 # timer
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
-libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 
 # pci
 libbsp_a_SOURCES += pci/pci.c

c/src/lib/libbsp/mips/rbtx4925/Makefile.am

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
 libbsp_a_SOURCES += irq/vectorisrs.c
 libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
 
-libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/mips/rbtx4938/Makefile.am

@@ -55,8 +55,9 @@ libbsp_a_SOURCES += ../shared/irq/irq.c
 libbsp_a_SOURCES += irq/vectorisrs.c
 libbsp_a_SOURCES += ../shared/irq/interruptmask_TX49.c
 
-libbsp_a_LIBADD  = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
+
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/interrupts.rel
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/tx49/timer.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/moxie/moxiesim/Makefile.am

@@ -40,9 +40,7 @@ libbsp_a_SOURCES += ../../shared/console-polled.c console/console-io.c \
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 EXTRA_DIST += times
 

c/src/lib/libbsp/nios2/nios2_iss/Makefile.am

@@ -44,7 +44,7 @@ libbsp_a_SOURCES += console/console.c ../../shared/console-polled.c
 libbsp_a_SOURCES += timer/timer.c
 
 # Cache
-libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/nios2/nios2_iss/headers.am

c/src/lib/libbsp/or1k/generic_or1k/Makefile.am

@@ -74,7 +74,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
+libbsp_a_SOURCES += ../../../../../../bsps/or1k/shared/cache/cache.c
 
 ###############################################################################
 #                  Special Rules                                              #

c/src/lib/libbsp/powerpc/beatnik/Makefile.am

@@ -163,8 +163,9 @@ endif
 # tod
 libbsp_a_SOURCES += ../../shared/tod.c tod/todcfg.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

c/src/lib/libbsp/powerpc/gen5200/Makefile.am

@@ -110,8 +110,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network_5200/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD =  ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-	../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
 	../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

c/src/lib/libbsp/powerpc/gen83xx/Makefile.am

@@ -73,13 +73,9 @@ libbsp_a_SOURCES += i2c/i2c_init.c
 # bsp_spi
 libbsp_a_SOURCES += spi/spi_init.c
 
-if HAS_NETWORKING
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
-libbsp_a_SOURCES += network/network.c
-libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
-endif
 
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-	../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
 	../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel   \
@@ -88,6 +84,11 @@ libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
 	../../../libcpu/@RTEMS_CPU@/mpc83xx/spi.rel \
 	../../../libcpu/@RTEMS_CPU@/mpc83xx/gtm.rel
 
+if HAS_NETWORKING
+libbsp_a_SOURCES += network/network.c
+libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel
+endif
+
 EXTRA_DIST += README.mpc8349eamds
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/powerpc/haleakala/Makefile.am

@@ -42,10 +42,11 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/network.c 
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
     ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel

c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am

@@ -114,9 +114,10 @@ libbsp_a_SOURCES += ../../i386/pc386/ne2000/ne2000.c
 endif
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
     polledIO.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \

c/src/lib/libbsp/powerpc/mpc55xxevb/Makefile.am

@@ -106,8 +106,9 @@ endif
 
 # BSP library
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/misc.rel \
     ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel \

c/src/lib/libbsp/powerpc/mpc8260ads/Makefile.am

@@ -54,8 +54,9 @@ libbsp_a_SOURCES += network/if_hdlcsubr.c
 libbsp_a_SOURCES += network/network.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc8260/console-generic.rel \

c/src/lib/libbsp/powerpc/mvme3100/Makefile.am

@@ -105,8 +105,9 @@ network_rel_CPPFLAGS = $(AM_CPPFLAGS)
 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/e500/clock.rel \
     ../../../libcpu/@RTEMS_CPU@/e500/timer.rel \

c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

@@ -83,10 +83,11 @@ project_lib_DATA += mvme5500start.$(OBJEXT)
 project_lib_DATA += linkcmds
 dist_project_lib_DATA += ../shared/startup/linkcmds.share
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

c/src/lib/libbsp/powerpc/psim/Makefile.am

@@ -60,8 +60,9 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += network/if_sim.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \

c/src/lib/libbsp/powerpc/qemuppc/Makefile.am

@@ -51,8 +51,9 @@ noinst_LIBRARIES = libbsp.a
 libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \
     $(irq_SOURCES)
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \

c/src/lib/libbsp/powerpc/qoriq/Makefile.am

@@ -96,8 +96,9 @@ libbsp_a_SOURCES += shmsupp/lock.S \
 	shmsupp/intercom.c \
 	shmsupp/intercom-mpci.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-	../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
 	../../../libcpu/@RTEMS_CPU@/e500/mmu.rel

c/src/lib/libbsp/powerpc/ss555/Makefile.am

@@ -35,9 +35,10 @@ libbsp_a_SOURCES += ../../shared/bspreset.c
 # tm27supp
 libbsp_a_SOURCES += startup/tm27supp.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc5xx/clock.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc5xx/console-generic.rel \

c/src/lib/libbsp/powerpc/t32mppc/Makefile.am

@@ -64,8 +64,9 @@ libbsp_a_SOURCES += irq/irq.c
 libbsp_a_SOURCES += ../../shared/console-termios.c
 libbsp_a_SOURCES += console/console.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-	../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel
 

c/src/lib/libbsp/powerpc/tqm8xx/Makefile.am

@@ -62,9 +62,10 @@ libbsp_a_SOURCES += network/network_fec.c
 libbsp_a_SOURCES += network/network_scc.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     ../../../libcpu/@RTEMS_CPU@/mpc8xx/console-generic.rel \

c/src/lib/libbsp/powerpc/virtex/Makefile.am

@@ -66,10 +66,11 @@ endif
 libbsp_a_SOURCES += timer/timer-config.c
 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD += \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
     ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
-    ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel
 
 include $(top_srcdir)/../../../../automake/local.am

c/src/lib/libbsp/powerpc/virtex4/Makefile.am

@@ -45,9 +45,10 @@ libbsp_a_SOURCES += irq/irq_init.c
 # mmu
 libbsp_a_SOURCES += mmu/mmu.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
                   ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
-                  ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
                   ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
                   ../../../libcpu/@RTEMS_CPU@/ppc403/clock.rel \
                   ../../../libcpu/@RTEMS_CPU@/ppc403/timer.rel

c/src/lib/libbsp/powerpc/virtex5/Makefile.am

@@ -47,9 +47,10 @@ libbsp_a_SOURCES += irq/irq_init.c
 # mmu
 libbsp_a_SOURCES += mmu/mmu.c
 
+libbsp_a_SOURCES += ../../../../../../bsps/powerpc/shared/cache/cache.c
+
 libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
                   ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
-                  ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \
                   ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \
                   ../../../libcpu/@RTEMS_CPU@/e500/clock.rel \
                   ../../../libcpu/@RTEMS_CPU@/e500/timer.rel

c/src/lib/libbsp/riscv/riscv_generic/Makefile.am

@@ -63,9 +63,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
 libbsp_a_SOURCES += irq/irq.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 # debugio
 libbsp_a_SOURCES += console/console-io.c

c/src/lib/libbsp/sh/gensh1/Makefile.am

@@ -47,9 +47,7 @@ libbsp_a_SOURCES += console/sci.c
 libbsp_a_SOURCES += ../../shared/dummy_printk_support.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 EXTRA_DIST += times
 

c/src/lib/libbsp/sh/gensh2/Makefile.am

@@ -51,9 +51,7 @@ libbsp_a_SOURCES += console/sci_termios.c
 libbsp_a_SOURCES += ../../shared/dummy_printk_support.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/sh/gensh2/headers.am

c/src/lib/libbsp/sh/gensh4/Makefile.am

@@ -38,9 +38,7 @@ libbsp_a_SOURCES += console/sh4uart.c
 libbsp_a_SOURCES += hw_init/hw_init.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 EXTRA_DIST += times
 

c/src/lib/libbsp/sh/shsim/Makefile.am

@@ -47,9 +47,7 @@ libbsp_a_SOURCES += console/console-debugio.c
 libbsp_a_SOURCES += ../../shared/timerstub.c
 
 # Cache
-libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
-libbsp_a_SOURCES += ../../shared/include/cache_.h
-libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/../../shared/include
 
 include $(top_srcdir)/../../../../automake/local.am
 include $(srcdir)/../../../../../../bsps/sh/shsim/headers.am

c/src/lib/libbsp/shared/include/cache_.h

@@ -1 +0,0 @@
-/* Empty */

c/src/lib/libbsp/sparc/erc32/Makefile.am

@@ -76,9 +76,10 @@ if HAS_NETWORKING
 libbsp_a_SOURCES += erc32sonic/erc32sonic.c
 endif
 
+libbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
+
 libbsp_a_LIBADD  = \
     ../../../libcpu/@RTEMS_CPU@/access.rel \
-    ../../../libcpu/@RTEMS_CPU@/cache.rel \
     ../../../libcpu/@RTEMS_CPU@/reg_win.rel \
     ../../../libcpu/@RTEMS_CPU@/syscall.rel