forked from Imagelibrary/rtems
4cf93658ef
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* Copyright (c) 2007-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp.h>
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#define CPU_DATA_CACHE_ALIGNMENT 16
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 16
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/*
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* There is no complete cache lock (only 2 ways of 4 can be locked)
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*/
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static inline void _CPU_cache_freeze_data(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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bsp_cacr_set_flags( MCF548X_CACR_IDCM);
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
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}
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static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_enable_data(void)
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{
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bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
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}
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static inline void _CPU_cache_disable_data(void)
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{
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bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
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}
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static inline void _CPU_cache_invalidate_1_data_line( const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_flush_1_data_line( const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_flush_entire_data( void)
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{
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uint32_t line = 0;
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for (line = 0; line < 512; ++line) {
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_CPU_cache_flush_1_data_line( (const void *) (line * 16));
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}
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}
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#include "../../../shared/cache/cacheimpl.h"
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