forked from Imagelibrary/rtems
sparc: Improve _CPU_Context_validate()
Write the pattern only once to the entry register window and the floating point registers. Update #2270.
This commit is contained in:
Alexander Krutwig
committed by
Sebastian Huber
Sebastian Huber
parent
5611839a7e
commit
4a5a45045a
@@ -19,8 +19,10 @@
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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#define FRAME_OFFSET_BUFFER (CPU_MINIMUM_STACK_FRAME_SIZE)
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#define FRAME_OFFSET_L0 (FRAME_OFFSET_BUFFER + 0x04)
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#define FRAME_OFFSET_BUFFER_0 (CPU_MINIMUM_STACK_FRAME_SIZE)
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#define FRAME_OFFSET_BUFFER_1 (FRAME_OFFSET_BUFFER_0 + 0x04)
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#define FRAME_OFFSET_BUFFER_2 (FRAME_OFFSET_BUFFER_1 + 0x04)
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#define FRAME_OFFSET_L0 (FRAME_OFFSET_BUFFER_2 + 0x04)
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#define FRAME_OFFSET_L1 (FRAME_OFFSET_L0 + 0x04)
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#define FRAME_OFFSET_L2 (FRAME_OFFSET_L1 + 0x04)
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#define FRAME_OFFSET_L3 (FRAME_OFFSET_L2 + 0x04)
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@@ -36,8 +38,7 @@
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#define FRAME_OFFSET_I5 (FRAME_OFFSET_I4 + 0x04)
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#define FRAME_OFFSET_I6 (FRAME_OFFSET_I5 + 0x04)
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#define FRAME_OFFSET_I7 (FRAME_OFFSET_I6 + 0x04)
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#define FRAME_OFFSET_SP (FRAME_OFFSET_I7 + 0x04)
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#define FRAME_END (FRAME_OFFSET_SP + 0x04)
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#define FRAME_END (FRAME_OFFSET_I7 + 0x04)
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#define FRAME_SIZE \
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((FRAME_END + CPU_STACK_ALIGNMENT - 1) & ~(CPU_STACK_ALIGNMENT - 1))
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@@ -50,27 +51,13 @@
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.macro check_float_register reg
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sub %g1, 1, %g1
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st \reg, [%sp + FRAME_OFFSET_BUFFER]
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ld [%sp + FRAME_OFFSET_BUFFER], %o1
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st \reg, [%sp + FRAME_OFFSET_BUFFER_0]
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ld [%sp + FRAME_OFFSET_BUFFER_0], %o1
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cmp %g1, %o1
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bne restore_registers
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nop
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.endm
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.macro check_fsr_register reg
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st \reg, [%sp + FRAME_OFFSET_BUFFER]
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ld [%sp + FRAME_OFFSET_BUFFER], %o1
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sub %g1, 1, %g1
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clr %g3
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sethi %hi(0xCF800000), %g3
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or %g3, %lo(0x0FFF), %g3
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and %g1, %g3, %g3
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and %o1, %g3, %o1
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cmp %o1, %g3
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bne restore_registers
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nop
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.endm
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.macro write_register reg
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add %g1, 1, %g1
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mov %g1, \reg
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@@ -78,26 +65,8 @@
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.macro write_float_register reg
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add %g1, 1, %g1
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st %g1, [%sp + FRAME_OFFSET_BUFFER]
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ld [%sp + FRAME_OFFSET_BUFFER], \reg
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.endm
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.macro write_fsr_register reg
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st \reg, [%sp + FRAME_OFFSET_BUFFER]
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ld [%sp + FRAME_OFFSET_BUFFER], %o1
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add %g1, 1, %g1
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clr %g3
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/*
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* FSR is masked with undefined, reserved or system-specific values
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* (e.g. FPU architecture version, FP queue).
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*/
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sethi %hi(0xCF800000), %g3
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or %g3, %lo(0x0FFF), %g3
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and %g1, %g3, %g3
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or %o1, %g3, %g3
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st %g3, [%sp + FRAME_OFFSET_BUFFER]
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ld [%sp + FRAME_OFFSET_BUFFER], \reg
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st %g1, [%sp + FRAME_OFFSET_BUFFER_0]
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ld [%sp + FRAME_OFFSET_BUFFER_0], \reg
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.endm
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.align 4
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@@ -136,7 +105,6 @@ SYM(_CPU_Context_validate):
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st %i5, [%sp + FRAME_OFFSET_I5]
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st %i6, [%sp + FRAME_OFFSET_I6]
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st %i7, [%sp + FRAME_OFFSET_I7]
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st %sp, [%sp + FRAME_OFFSET_SP]
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cmp %g4, 0
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bne write_locals_and_outputs
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@@ -146,8 +114,10 @@ SYM(_CPU_Context_validate):
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new_check_cycle:
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clr %g4
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sub %g1, 1, %g1
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add %g4, 1, %g4
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ld [%sp + FRAME_OFFSET_BUFFER_1], %g1
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b switch_to_next_window
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nop
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/* Write pattern values into registers */
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check_for_fp:
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@@ -155,7 +125,20 @@ check_for_fp:
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be write_y
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nop
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write_fsr_register %fsr
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/*
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* Write pattern to FSR. FSR is masked with undefined, reserved or
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* system-specific values (e.g. FPU architecture version, FP queue).
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*/
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st %fsr, [%sp + FRAME_OFFSET_BUFFER_0]
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ld [%sp + FRAME_OFFSET_BUFFER_0], %o1
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add %g1, 1, %g1
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sethi %hi(0xCF800000), %g3
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or %g3, %lo(0x0FFF), %g3
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and %g1, %g3, %g3
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or %o1, %g3, %g3
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st %g3, [%sp + FRAME_OFFSET_BUFFER_0]
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ld [%sp + FRAME_OFFSET_BUFFER_0], %fsr
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write_float_register %f0
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write_float_register %f1
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write_float_register %f2
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@@ -224,6 +207,12 @@ write_locals_and_outputs:
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/* Don't write register $o7 => return address */
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add %g4, 1, %g4
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cmp %g4, 1
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bne no_store
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nop
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st %g1, [%sp + FRAME_OFFSET_BUFFER_1]
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no_store:
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cmp %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS
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bne switch_to_next_window
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nop
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@@ -284,12 +273,15 @@ dont_check_i0:
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/* Check Y register */
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y_checking:
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st %o1, [%sp + FRAME_OFFSET_BUFFER_2]
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mov %y, %o1
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check_register %o1
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ld [%sp + FRAME_OFFSET_BUFFER_2], %o1
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cmp %g2, 0
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be new_check_cycle
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nop
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st %o1, [%sp + FRAME_OFFSET_BUFFER_2]
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/* Check floating point registers */
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check_float_register %f31
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check_float_register %f30
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@@ -323,9 +315,20 @@ y_checking:
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check_float_register %f2
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check_float_register %f1
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check_float_register %f0
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check_fsr_register %fsr
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be new_check_cycle
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st %fsr, [%sp + FRAME_OFFSET_BUFFER_0]
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ld [%sp + FRAME_OFFSET_BUFFER_0], %o1
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sub %g1, 1, %g1
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clr %g3
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sethi %hi(0xCF800000), %g3
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or %g3, %lo(0x0FFF), %g3
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and %g1, %g3, %g3
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and %o1, %g3, %o1
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cmp %o1, %g3
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bne restore_registers
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ld [%sp + FRAME_OFFSET_BUFFER_2], %o1
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b new_check_cycle
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nop
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/****** RESTORE STARTS HERE *******/
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