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bsps/imxrt: Add imxrt1166_cm7_saltshaker BSP

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The BSP is for a custom i.MXRT1166 based board. At the moment, only the
cortex M7 is supported.
This commit is contained in:
Christian Mauderer
2023-04-12 17:34:31 +02:00
parent 780149bc38
commit 4a3ace7c7a
23 changed files with 6907 additions and 4 deletions
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823
bsps/arm/imxrt/boards/saltshaker/clock_config.c Normal file
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/*
* Copyright 2017-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
*
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v11.0
processor: MIMXRT1166xxxxx
package_id: MIMXRT1166DVM6A
mcu_data: ksdk2_0
processor_version: 13.0.2
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
#include "fsl_dcdc.h"
#include "fsl_pmu.h"
#include "fsl_clock.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ARM_PLL_CLK.outFreq, value: 600 MHz, locked: true, accuracy: '0.001'}
- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: AXI_CLK_ROOT.outFreq, value: 600 MHz}
- {id: BUS_CLK_ROOT.outFreq, value: 198 MHz}
- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 120 MHz}
- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET1_CLK_ROOT.outFreq, value: 50 MHz, locked: true, accuracy: '0.001'}
- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
- {id: ENET_25M_CLK_ROOT.outFreq, value: 25 MHz, locked: true, accuracy: '0.001'}
- {id: ENET_REF_CLK.outFreq, value: 50 MHz, locked: true, accuracy: '0.001'}
- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: ENET_TX_CLK.outFreq, value: 25 MHz, locked: true, accuracy: '0.001'}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPSPI1_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPSPI2_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPSPI3_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPSPI4_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPSPI5_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPSPI6_CLK_ROOT.outFreq, value: 50 MHz}
- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M4_CLK_ROOT.outFreq, value: 240 MHz}
- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
- {id: M7_CLK_ROOT.outFreq, value: 600 MHz}
- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
- {id: MQS_MCLK.outFreq, value: 24 MHz}
- {id: OSC_24M.outFreq, value: 24 MHz}
- {id: OSC_32K.outFreq, value: 32.768 kHz}
- {id: OSC_RC_16M.outFreq, value: 16 MHz}
- {id: OSC_RC_400M.outFreq, value: 400 MHz}
- {id: OSC_RC_48M.outFreq, value: 48 MHz}
- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz, locked: true, accuracy: '0.001'}
- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 2160/13 MHz}
- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
- {id: SYS_PLL1_CLK.outFreq, value: 1 GHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL1_DIV2_CLK.outFreq, value: 500 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL1_DIV5_CLK.outFreq, value: 200 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 396 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz, locked: true, accuracy: '0.001'}
- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz, locked: true, accuracy: '0.001'}
- {id: USDHC1_CLK_ROOT.outFreq, value: 200 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
settings:
- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
- {id: SemcConfigurationPatchConfig, value: disabled}
- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
- {id: ANADIG_PLL.ARM_PLL_POST_DIV.scale, value: '4'}
- {id: ANADIG_PLL.ARM_PLL_VDIV.scale, value: '100'}
- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
- {id: ANADIG_PLL.SYS_PLL2_PFD3_DIV.scale, value: '24'}
- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
- {id: CCM.CLOCK_ROOT1.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD3_CLK}
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD0_CLK}
- {id: CCM.CLOCK_ROOT43.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT43.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT44.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT44.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT45.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT45.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT46.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT46.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT47.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT47.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT48.DIV.scale, value: '4', locked: true}
- {id: CCM.CLOCK_ROOT48.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT51.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT51.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT54.DIV.scale, value: '8'}
- {id: CCM.CLOCK_ROOT54.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT55.MUX.sel, value: ANADIG_OSC.OSC_24M}
- {id: CCM.CLOCK_ROOT58.MUX.sel, value: ANADIG_PLL.SYS_PLL1_DIV5_CLK}
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
- {id: IOMUXC_GPR.ENET_REF_CLK_SEL.sel, value: CCM.ENET1_CLK_ROOT}
sources:
- {id: IOMUXC_GPR.ENET_REF_CLK_EXT.outFreq, value: 50 MHz, enabled: true}
- {id: IOMUXC_GPR.ENET_TX_CLK_EXT.outFreq, value: 25 MHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
#if __CORTEX_M == 7
#define BYPASS_LDO_LPSR 1
#endif
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
{
.postDivider = kCLOCK_PllPostDiv4, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
.loopDivider = 200, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
};
const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN =
{
.pllDiv2En = 1, /* Enable Sys Pll1 divide-by-2 clock or not */
.pllDiv5En = 1, /* Enable Sys Pll1 divide-by-5 clock or not */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
{
.mfd = 268435455, /* Denominator of spread spectrum */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
{
.loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
.postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
.numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
.ss = NULL, /* Spread spectrum parameter */
.ssEnable = false, /* Enable spread spectrum or not */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
clock_root_config_t rootCfg = {0};
/* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
DCDC_BootIntoDCM(DCDC);
#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
#endif
/* Config CLK_1M */
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
/* Init OSC RC 16M */
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
/* Init OSC RC 400M */
CLOCK_OSC_EnableOscRc400M();
CLOCK_OSC_GateOscRc400M(true);
/* Init OSC RC 48M */
CLOCK_OSC_EnableOsc48M(true);
CLOCK_OSC_EnableOsc48MDiv2(true);
/* Config OSC 24M */
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
/* Wait for 24M OSC to be stable. */
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
{
}
/* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
#endif
/* Init Arm Pll. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* Init Sys Pll1. */
CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN);
/* Init Sys Pll2. */
CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
/* Init System Pll2 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
/* Init System Pll2 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
/* Init System Pll2 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
/* Init System Pll2 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24);
/* Init Sys Pll3. */
CLOCK_InitSysPll3();
/* Init System Pll3 pfd0. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
/* Init System Pll3 pfd1. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
/* Init System Pll3 pfd2. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
/* Init System Pll3 pfd3. */
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
/* Bypass Audio Pll. */
CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
/* DeInit Audio Pll. */
CLOCK_DeinitAudioPll();
/* Init Video Pll. */
CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
/* Module clock root configurations. */
/* Configure M7 using ARM_PLL_CLK */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
#endif
/* Configure M4 using SYS_PLL3_CLK */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
#endif
/* Configure BUS using SYS_PLL2_PFD3_CLK */
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
/* Configure BUS_LPSR using SYS_PLL3_CLK */
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
/* Configure SEMC using SYS_PLL3_PFD0_CLK */
#ifndef SKIP_SEMC_INIT
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
#endif
/* Configure CSSYS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
/* Configure CSTRACE using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 4
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
#endif
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
#if __CORTEX_M == 7
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
#endif
/* Configure ADC1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
/* Configure ADC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
/* Configure ACMP using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
/* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
/* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
/* Configure GPT1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
/* Configure GPT2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
/* Configure GPT3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
/* Configure GPT4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
/* Configure GPT5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
/* Configure GPT6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
#endif
/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
/* Configure CAN1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
/* Configure CAN2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
/* Configure CAN3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
/* Configure LPUART1 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
/* Configure LPUART2 using SYS_PLL2_CLK */
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
rootCfg.div = 22;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
/* Configure LPUART3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
/* Configure LPUART4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
/* Configure LPUART5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
/* Configure LPUART6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
/* Configure LPUART7 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
/* Configure LPUART8 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
/* Configure LPUART9 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
/* Configure LPUART10 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
/* Configure LPUART11 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
/* Configure LPUART12 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
/* Configure LPI2C1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
/* Configure LPI2C2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
/* Configure LPI2C3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
/* Configure LPI2C4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
/* Configure LPI2C5 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
/* Configure LPI2C6 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
/* Configure LPSPI1 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
/* Configure LPSPI2 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
/* Configure LPSPI3 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
/* Configure LPSPI4 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
/* Configure LPSPI5 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
/* Configure LPSPI6 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
/* Configure EMV1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
/* Configure EMV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
/* Configure ENET1 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 4;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
/* Configure ENET2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
/* Configure ENET_25M using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 8;
CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
/* Configure ENET_TIMER1 using OSC_24M */
rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
/* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
/* Configure USDHC1 using SYS_PLL1_DIV5_CLK */
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
/* Configure USDHC2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
/* Configure ASRC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
/* Configure MQS using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
/* Configure MIC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
/* Configure SPDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
/* Configure SAI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
/* Configure SAI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
/* Configure SAI3 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
/* Configure SAI4 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
/* Configure GC355 using PLL_VIDEO_CLK */
rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
rootCfg.div = 2;
CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
/* Configure LCDIF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
/* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
/* Configure MIPI_REF using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
/* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
/* Configure CSI2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
/* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
/* Configure CSI2_UI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
/* Configure CSI using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
/* Configure CKO1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
/* Configure CKO2 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET Tx clock source. */
IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK;
/* Set ENET Ref clock source. */
IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
/* Set ENET_1G Tx clock source. */
IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
/* Set ENET_1G Ref clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
/* Set GPT3 High frequency reference clock source. */
IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
/* Set GPT4 High frequency reference clock source. */
IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
/* Set GPT5 High frequency reference clock source. */
IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
/* Set GPT6 High frequency reference clock source. */
IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
#if __CORTEX_M == 7
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
#else
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
#endif
}

35
bsps/arm/imxrt/boards/saltshaker/clock_config.h Normal file
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef BOARD_CLOCK_CONFIG_H
#define BOARD_CLOCK_CONFIG_H
#include <bspopts.h>
#include <fsl_clock_config.h>
#define FLEXSPI_IN_USE
#endif /* BOARD_CLOCK_CONFIG_H */

310
bsps/arm/imxrt/boards/saltshaker/dcd.c Normal file
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/*
* Copyright 2017-2023 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/***********************************************************************************************************************
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
**********************************************************************************************************************/
#include "dcd.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
#endif
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
__attribute__((section(".boot_hdr.dcd_data"), used))
#elif defined(__ICCARM__)
#pragma location = ".boot_hdr.dcd_data"
#endif
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: DCDx v3.0
processor: MIMXRT1166xxxxx
package_id: MIMXRT1166DVM6A
mcu_data: ksdk2_0
processor_version: 13.0.2
output_format: c_array
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
const uint8_t dcd_data[] = {
/* HEADER */
/* Tag */
0xD2,
/* Image Length */
0x03, 0x98,
/* Version */
0x41,
/* COMMANDS */
/* group: 'SDRAM Initialization' */
/* #1.1-93, command header bytes for merged 'Write - value' command */
0xCC, 0x02, 0xEC, 0x04,
/* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4, comment: 'SEMC_CLKROOT = SYS_PLL2_PFD1 / 2' */
0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03,
/* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, size: 4, comment: 'SEMC_ADDR00' */
0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
/* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, size: 4, comment: 'SEMC_ADDR01' */
0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
/* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, size: 4, comment: 'SEMC_ADDR02' */
0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
/* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, size: 4, comment: 'SEMC_ADDR03' */
0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
/* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, size: 4, comment: 'SEMC_ADDR04' */
0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
/* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, size: 4, comment: 'SEMC_ADDR05' */
0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
/* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, size: 4, comment: 'SEMC_ADDR06' */
0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
/* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, size: 4, comment: 'SEMC_ADDR07' */
0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
/* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, size: 4, comment: 'SEMC_ADDR08' */
0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
/* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, size: 4, comment: 'SEMC_ADDR09' */
0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
/* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, size: 4, comment: 'SEMC_ADDR10' */
0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
/* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, size: 4, comment: 'SEMC_ADDR11' */
0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
/* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, size: 4, comment: 'SEMC_ADDR12' */
0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
/* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, size: 4, comment: 'SEMC_BA0' */
0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
/* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, size: 4, comment: 'SEMC_BA1' */
0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
/* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, size: 4, comment: 'SEMC_CKE' */
0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
/* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, size: 4, comment: 'SEMC_CLK' */
0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
/* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, size: 4, comment: 'SEMC_CS0' */
0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00,
/* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, size: 4, comment: 'SEMC_WE' */
0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
/* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, size: 4, comment: 'SEMC_CAS' */
0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
/* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, size: 4, comment: 'SEMC_RAS' */
0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
/* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, size: 4, comment: 'SEMC_DM00' */
0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
/* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, size: 4, comment: 'SEMC_DM01' */
0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
/* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, size: 4, comment: 'SEMC_DATA00' */
0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00,
/* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, size: 4, comment: 'SEMC_DATA01' */
0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
/* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, size: 4, comment: 'SEMC_DATA02' */
0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
/* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, size: 4, comment: 'SEMC_DATA03' */
0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
/* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, size: 4, comment: 'SEMC_DATA04' */
0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
/* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, size: 4, comment: 'SEMC_DATA05' */
0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
/* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, size: 4, comment: 'SEMC_DATA06' */
0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
/* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, size: 4, comment: 'SEMC_DATA07' */
0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
/* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, size: 4, comment: 'SEMC_DATA08' */
0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
/* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, size: 4, comment: 'SEMC_DATA09' */
0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
/* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, size: 4, comment: 'SEMC_DATA10' */
0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
/* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, size: 4, comment: 'SEMC_DATA11' */
0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
/* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, size: 4, comment: 'SEMC_DATA12' */
0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, size: 4, comment: 'SEMC_DATA13' */
0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
/* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, size: 4, comment: 'SEMC_DATA14' */
0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
/* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, size: 4, comment: 'SEMC_DATA15' */
0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
/* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, size: 4, comment: 'SEMC_DQS' */
0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10,
/* #1.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, size: 4, comment: 'SEMC_ADDR00' */
0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08,
/* #1.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, size: 4, comment: 'SEMC_ADDR01' */
0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08,
/* #1.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, size: 4, comment: 'SEMC_ADDR02' */
0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08,
/* #1.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, size: 4, comment: 'SEMC_ADDR03' */
0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08,
/* #1.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, size: 4, comment: 'SEMC_ADDR04' */
0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08,
/* #1.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, size: 4, comment: 'SEMC_ADDR05' */
0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08,
/* #1.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, size: 4, comment: 'SEMC_ADDR06' */
0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08,
/* #1.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, size: 4, comment: 'SEMC_ADDR07' */
0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08,
/* #1.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, size: 4, comment: 'SEMC_ADDR08' */
0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08,
/* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, size: 4, comment: 'SEMC_ADDR09' */
0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08,
/* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, size: 4, comment: 'SEMC_ADDR10' */
0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08,
/* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, size: 4, comment: 'SEMC_ADDR11' */
0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08,
/* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, size: 4, comment: 'SEMC_ADDR12' */
0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08,
/* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, size: 4, comment: 'SEMC_BA0' */
0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08,
/* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, size: 4, comment: 'SEMC_BA1' */
0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08,
/* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, size: 4, comment: 'SEMC_CKE' */
0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08,
/* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, size: 4, comment: 'SEMC_CLK' */
0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08,
/* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x04, size: 4, comment: 'SEMC_CS0' */
0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x04,
/* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, size: 4, comment: 'SEMC_WE' */
0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08,
/* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, size: 4, comment: 'SEMC_CAS' */
0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08,
/* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, size: 4, comment: 'SEMC_RAS' */
0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08,
/* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, size: 4, comment: 'SEMC_DM00' */
0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08,
/* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, size: 4, comment: 'SEMC_DM01' */
0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08,
/* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, size: 4, comment: 'SEMC_DATA00' */
0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08,
/* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, size: 4, comment: 'SEMC_DATA01' */
0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08,
/* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, size: 4, comment: 'SEMC_DATA02' */
0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08,
/* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, size: 4, comment: 'SEMC_DATA03' */
0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08,
/* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, size: 4, comment: 'SEMC_DATA04' */
0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08,
/* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, size: 4, comment: 'SEMC_DATA05' */
0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08,
/* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, size: 4, comment: 'SEMC_DATA06' */
0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08,
/* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, size: 4, comment: 'SEMC_DATA07' */
0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08,
/* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, size: 4, comment: 'SEMC_DATA08' */
0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08,
/* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, size: 4, comment: 'SEMC_DATA09' */
0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08,
/* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, size: 4, comment: 'SEMC_DATA10' */
0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08,
/* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, size: 4, comment: 'SEMC_DATA11' */
0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08,
/* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, size: 4, comment: 'SEMC_DATA12' */
0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08,
/* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, size: 4, comment: 'SEMC_DATA13' */
0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08,
/* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, size: 4, comment: 'SEMC_DATA14' */
0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08,
/* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, size: 4, comment: 'SEMC_DATA15' */
0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08,
/* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, size: 4, comment: 'SEMC_DQS' */
0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08,
/* #1.82, command: write_value, address: SEMC_MCR, value: 0x1FFF0004, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x00, 0x1F, 0xFF, 0x00, 0x04,
/* #1.83, command: write_value, address: SEMC_BMCR0, value: 0x104085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x08, 0x00, 0x10, 0x40, 0x85,
/* #1.84, command: write_value, address: SEMC_BMCR1, value: 0x40246085, size: 4, comment: 'Default values from SEMC_GetDefaultConfig' */
0x40, 0x0D, 0x40, 0x0C, 0x40, 0x24, 0x60, 0x85,
/* #1.85, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4, comment: 'CS0: Start add Address 0x80000000; Memsize 64MByte' */
0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D,
/* #1.86, command: write_value, address: SEMC_SDRAMCR0, value: 0xF35, size: 4, comment: 'PortSize 16; Burst Len 8; 9 Bit Column Addresses; CAS Latency 3' */
0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x35,
/* #1.87, command: write_value, address: SEMC_SDRAMCR1, value: 0x00664B22, size: 4, comment: 'PRE2ACT: tRP = 18ns; ACT2RW: tRCD = 18ns; RFRC: tRFC=72ns; WRC: tWR=15ns; CKEOFF: tRAS_min = 42ns; ACT2PRE: tRAS_min = 42ns' */
0x40, 0x0D, 0x40, 0x44, 0x00, 0x66, 0x4B, 0x22,
/* #1.88, command: write_value, address: SEMC_SDRAMCR2, value: 0x00090B13, size: 4, comment: 'SRCC: tXSR=120ns; REF2REF: tRFC=72ns; ACT2ACT: tRC=60ns' */
0x40, 0x0D, 0x40, 0x48, 0x00, 0x09, 0x0B, 0x13,
/* #1.89, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A00, size: 4, comment: 'Default values from NXP examples for SEMC' */
0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x00,
/* #1.90, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00,
/* #1.91, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02,
/* #1.92, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00,
/* #1.93, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4, comment: 'IP Command: Precharge All' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
/* #2, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #3, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #4, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #5, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #6, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #7.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Auto Refresh' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #8, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #9, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #10, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #11, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #12, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #13.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4, comment: 'IP Command: Precharge All' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
/* #14, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #15, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #16, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #17, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #18, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #19.1-3, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x1C, 0x04,
/* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4, comment: 'Mode: BurstLen8; CAS Latency 3' */
0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33,
/* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4, comment: 'IP Command: Mode Set' */
0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
/* #20, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #21, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #22, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #23, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #24, command: nop */
0xC0, 0x00, 0x04, 0x00,
/* #25.1-2, command header bytes for merged 'Write - value' command */
0xCC, 0x00, 0x14, 0x04,
/* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */
0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03,
/* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x8070A01, size: 4, comment: 'Enable autorefresh. Otherwise same as above.' */
0x40, 0x0D, 0x40, 0x4C, 0x08, 0x07, 0x0A, 0x01
};
/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
#else
const uint8_t dcd_data[] = {0x00};
#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
#endif /* XIP_BOOT_HEADER_ENABLE */

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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef BOARD_DCD_H
#define BOARD_DCD_H
#include <bsp/flash-headers.h>
#include <stdint.h>
#define XIP_BOOT_HEADER_ENABLE 1
#define XIP_BOOT_HEADER_DCD_ENABLE 1
#define dcd_data imxrt_dcd_data
#endif /* BOARD_DCD_H */

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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/flash-headers.h>
#include <bspopts.h>
const flexspi_nor_config_t imxrt_flexspi_config = {
.memConfig = {
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackInternally,
.csHoldTime = 1u, /* In serial Clk cycles. tSLCH = 3ns for the W25Q64JV. */
.csSetupTime = 1u, /* In serial Clk cycles. tCHSH = 3ns for the W25Q64JV. */
.columnAddressWidth = 0u, /* W25Q64JV needs one linear address. */
.controllerMiscOption = 0u,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz, /* FIXME: 133MHz should be possible */
.sflashA1Size = IMXRT_MEMORY_FLASH_SIZE,
.dataValidTime = {0u, 0u}, /* Only relevant for Clock < 100MHz */
.busyOffset = 0,
.busyBitPolarity = 0,
.lookupTable = {
/* Read LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_READ + 0] = FLEXSPI_LUT_SEQ(
CMD_SDR, FLEXSPI_1PAD, 0xEB,
RADDR_SDR, FLEXSPI_4PAD, 24),
[4 * NOR_CMD_LUT_SEQ_IDX_READ + 1] = FLEXSPI_LUT_SEQ(
DUMMY_SDR, FLEXSPI_4PAD, 6,
READ_SDR, FLEXSPI_4PAD, 4),
/* Read Status LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS + 0] = FLEXSPI_LUT_SEQ(
CMD_SDR, FLEXSPI_1PAD, 0x5,
READ_SDR, FLEXSPI_1PAD, 4),
/* Write Enable LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE + 0] = 0,
/* Erase Sector LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR + 0] = 0,
/* Page Program LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 0] = 0,
/* Erase Chip LUTs */
[4 * NOR_CMD_LUT_SEQ_IDX_CHIPERASE + 0] = 0,
},
},
.pageSize = 256,
.sectorSize = 4096,
.blockSize = 32 * 1024,
.isUniformBlockSize = 1,
};

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/*
* Copyright 2018 NXP.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_iomuxc.h"
#include <bsp.h>
#include <bsp/start.h>
BSP_START_TEXT_SECTION
void BOARD_InitDEBUG_UARTPins(void) {
CLOCK_EnableClock(kCLOCK_Iomuxc);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_LPUART8_TXD, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_03_LPUART8_RXD, 0U);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_02_LPUART8_TXD, 0x10B0u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_03_LPUART8_RXD, 0x10B0u);
}

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bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c Normal file
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bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts Normal file
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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2020-2023 embedded brains GmbH & Co. KG
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* FIXME: Compilation should be automated.
*
* Compile this file with the following commands:
* export BSP_DIR="${RTEMS_SRC_DIR}/bsps/arm/imxrt/"
* arm-rtems6-cpp -P -x assembler-with-cpp -I "${BSP_DIR}/include/" -include "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dts" /dev/null | \
* dtc -O dtb -o "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dtb" -b 0 -p 64
* rtems-bin2c -A 8 -C -N imxrt_dtb "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.dtb" "${BSP_DIR}/dts/imxrt1166-cm7-saltshaker.c"
*/
/dts-v1/;
#include <imxrt/imxrt1166-pinfunc.h>
#include <imxrt/imxrt1166.dtsi>
/ {
led-controller {
compatible = "gpio-leds";
pinctrl-0 = <&pinctrl_led>;
status = "okay";
led-0 {
gpios = <&gpio9 15 0>;
};
led-1 {
gpios = <&gpio9 16 0>;
};
led-2 {
gpios = <&gpio9 18 0>;
};
};
usdhc1_vcard: usdhc1_vcard {
compatible = "regulator-fixed";
regulator-name = "usdhc1-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio10 2 0>;
regulator-boot-on;
};
};
&lpuart8 {
pinctrl-0 = <&pinctrl_lpuart8>;
status = "okay";
};
&chosen {
stdout-path = &lpuart8;
};
&fec2 {
pinctrl-0 = <&pinctrl_fec2>;
phy-reset-gpios = <&gpio9 14 1>;
phy-mode = "rmii";
status = "okay";
};
&lpi2c1 {
pinctrl-0 = <&pinctrl_lpi2c1>;
};
&lpi2c5 {
pinctrl-0 = <&pinctrl_lpi2c5>;
};
&lpi2c6 {
pinctrl-0 = <&pinctrl_lpi2c6>;
};
&lpspi1 {
pinctrl-0 = <&pinctrl_lpspi1>;
};
&lpspi3 {
pinctrl-0 = <&pinctrl_lpspi3>;
};
&lpspi4 {
pinctrl-0 = <&pinctrl_lpspi4>;
};
&lpuart7 {
pinctrl-0 = <&pinctrl_lpuart7>;
};
&lpuart12 {
pinctrl-0 = <&pinctrl_lpuart12>;
};
&usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1>;
status = "okay";
bus-width = <4>;
cd-gpios = <&gpio9 31 1>;
cd-inverted;
vmmc-supply = <&usdhc1_vcard>;
};
&video_mux {
pinctrl-0 = <&pinctrl_video_mux>;
};
&iomuxc {
pinctrl_lpuart8: lpuart8grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_02_LPUART8_TXD 0x8
IMXRT_PAD_GPIO_AD_03_LPUART8_RXD 0x13000
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_33_ENET_MDIO 0x1c
IMXRT_PAD_GPIO_EMC_B2_19_ENET_MDC 0x00
IMXRT_PAD_GPIO_AD_26_ENET_RX_DATA00 0x02
IMXRT_PAD_GPIO_AD_27_ENET_RX_DATA01 0x02
IMXRT_PAD_GPIO_AD_24_ENET_RX_EN 0x02
IMXRT_PAD_GPIO_AD_30_ENET_TX_DATA00 0x02
IMXRT_PAD_GPIO_AD_31_ENET_TX_DATA01 0x02
IMXRT_PAD_GPIO_AD_28_ENET_TX_EN 0x02
IMXRT_PAD_GPIO_AD_29_ENET_REF_CLK 0x40000002
IMXRT_PAD_GPIO_AD_25_ENET_RX_ER 0x02
/* ENET_RST */
IMXRT_PAD_GPIO_AD_15_GPIO9_IO14 0x1c
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_08_LPI2C1_SCL 0x40000011
IMXRT_PAD_GPIO_AD_09_LPI2C1_SDA 0x40000011
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
IMXRT_PAD_GPIO_EMC_B2_04_LPSPI3_SCK 0x04
IMXRT_PAD_GPIO_EMC_B2_06_LPSPI3_SOUT 0x04
IMXRT_PAD_GPIO_EMC_B2_07_LPSPI3_SIN 0x04
IMXRT_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 0x04
IMXRT_PAD_GPIO_EMC_B2_08_LPSPI3_PCS1 0x04
IMXRT_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 0x04
IMXRT_PAD_GPIO_EMC_B2_10_LPSPI3_PCS3 0x04
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
IMXRT_PAD_GPIO_EMC_B2_04_LPSPI3_SCK 0x06
IMXRT_PAD_GPIO_EMC_B2_06_LPSPI3_SOUT 0x06
IMXRT_PAD_GPIO_EMC_B2_07_LPSPI3_SIN 0x06
IMXRT_PAD_GPIO_EMC_B2_05_LPSPI3_PCS0 0x06
IMXRT_PAD_GPIO_EMC_B2_08_LPSPI3_PCS1 0x06
IMXRT_PAD_GPIO_EMC_B2_09_LPSPI3_PCS2 0x06
IMXRT_PAD_GPIO_EMC_B2_10_LPSPI3_PCS3 0x06
>;
};
pinctrl_lpspi1: lpspi1grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_20_LPSPI1_PCS3 0x06
IMXRT_PAD_GPIO_EMC_B2_00_LPSPI1_SCK 0x06
IMXRT_PAD_GPIO_EMC_B2_01_LPSPI1_PCS0 0x06
IMXRT_PAD_GPIO_EMC_B2_02_LPSPI1_SOUT 0x06
IMXRT_PAD_GPIO_EMC_B2_03_LPSPI1_SIN 0x06
>;
};
pinctrl_lpspi4: lpspi4grp {
fsl,pins = <
IMXRT_PAD_GPIO_SD_B2_00_LPSPI4_SCK 0x06
IMXRT_PAD_GPIO_SD_B2_01_LPSPI4_PCS0 0x06
IMXRT_PAD_GPIO_SD_B2_02_LPSPI4_SOUT 0x06
IMXRT_PAD_GPIO_SD_B2_03_LPSPI4_SIN 0x06
IMXRT_PAD_GPIO_SD_B2_04_LPSPI4_PCS1 0x06
IMXRT_PAD_GPIO_SD_B2_05_LPSPI4_PCS2 0x06
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_00_LPUART7_TXD 0x0c
IMXRT_PAD_GPIO_AD_01_LPUART7_RXD 0x0c
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMXRT_PAD_GPIO_SD_B1_00_USDHC1_CMD 0x04
IMXRT_PAD_GPIO_SD_B1_01_USDHC1_CLK 0x08
IMXRT_PAD_GPIO_SD_B1_02_USDHC1_DATA0 0x04
IMXRT_PAD_GPIO_SD_B1_03_USDHC1_DATA1 0x04
IMXRT_PAD_GPIO_SD_B1_04_USDHC1_DATA2 0x04
IMXRT_PAD_GPIO_SD_B1_05_USDHC1_DATA3 0x04
IMXRT_PAD_GPIO_AD_32_GPIO9_IO31 0x10 /* CD */
IMXRT_PAD_GPIO_AD_34_GPIO10_IO01 0x00 /* VSEL */
IMXRT_PAD_GPIO_AD_35_GPIO10_IO02 0x00 /* PWR_B */
>;
};
pinctrl_video_mux: videomuxgrp {
fsl,pins = <
IMXRT_PAD_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x0a
IMXRT_PAD_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x0a
IMXRT_PAD_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x0a
IMXRT_PAD_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x0a
IMXRT_PAD_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x0a
IMXRT_PAD_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x0a
IMXRT_PAD_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x0a
IMXRT_PAD_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x0a
IMXRT_PAD_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x0a
IMXRT_PAD_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x0a
IMXRT_PAD_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x0a
IMXRT_PAD_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x0a
IMXRT_PAD_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x0a
IMXRT_PAD_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x0a
IMXRT_PAD_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x0a
IMXRT_PAD_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x0a
IMXRT_PAD_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x0a
IMXRT_PAD_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x0a
IMXRT_PAD_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x0a
IMXRT_PAD_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x0a
IMXRT_PAD_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x0a
IMXRT_PAD_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x0a
IMXRT_PAD_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x0a
IMXRT_PAD_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x0a
IMXRT_PAD_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x0a
IMXRT_PAD_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x0a
IMXRT_PAD_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x0a
IMXRT_PAD_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x0a
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
IMXRT_PAD_GPIO_AD_16_GPIO9_IO15 0x00
IMXRT_PAD_GPIO_AD_17_GPIO9_IO16 0x00
IMXRT_PAD_GPIO_AD_19_GPIO9_IO18 0x00
>;
};
};
&iomuxc_lpsr {
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
IMXRT_PAD_GPIO_LPSR_09_LPI2C5_SCL 0x40000011
IMXRT_PAD_GPIO_LPSR_08_LPI2C5_SDA 0x40000011
>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins = <
IMXRT_PAD_GPIO_LPSR_07_LPI2C6_SCL 0x40000011
IMXRT_PAD_GPIO_LPSR_06_LPI2C6_SDA 0x40000011
>;
};
pinctrl_lpuart12: lpuart12grp {
fsl,pins = <
IMXRT_PAD_GPIO_LPSR_00_LPUART12_TXD 0x0d
IMXRT_PAD_GPIO_LPSR_01_LPUART12_RXD 0x0d
IMXRT_PAD_GPIO_LPSR_04_LPUART12_RTS_B 0x0d
IMXRT_PAD_GPIO_LPSR_05_LPUART12_CTS_B 0x0d
>;
};
};
&iomuxc_snvs {
};

5
bsps/arm/imxrt/include/bsp/irq.h
View File

@@ -34,6 +34,7 @@
#ifndef LIBBSP_ARM_IMXRT_IRQ_H
#define LIBBSP_ARM_IMXRT_IRQ_H
#include <bspopts.h>
#ifndef ASM
#include <rtems/irq.h>
#include <rtems/irq-extension.h>
@@ -43,7 +44,11 @@
extern "C" {
#endif /* __cplusplus */
#if IMXRT_IS_MIMXRT10xx
#define BSP_INTERRUPT_VECTOR_COUNT 160
#elif IMXRT_IS_MIMXRT11xx
#define BSP_INTERRUPT_VECTOR_COUNT 217
#endif
#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
#ifdef __cplusplus

1607
bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h Normal file
View File

File diff suppressed because it is too large Load Diff

1224
bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

23
bsps/arm/imxrt/start/bspstart.c
View File

@@ -59,6 +59,13 @@ static void imxrt_disable_wait_mode(void)
* every WFI.
*/
CLOCK_SetMode(kCLOCK_ModeRun);
#elif IMXRT_IS_MIMXRT11xx
/*
* i.MX RT11xx doesn't support disabling power saving for WFI. On the other
* hand it doesn't have a separate interrupt controller like the i.MX RT1050.
* So a power save during WFI is only annoying during debugging but doesn't
* hurt otherwise.
*/
#else
#error Disabling wait mode not implemented for this chip.
#endif
@@ -129,6 +136,22 @@ uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
return intr[0];
}
/*
* Clock frequencies for peripherals like SD card. These are used by libbsd
* drivers.
*/
#if IMXRT_IS_MIMXRT11xx
uint32_t
imx_ccm_sdhci_hz(void)
{
/*
* We don't know which SDHCI is used. So just return the clock frequency
* of the first SDHCI and hope the best.
*/
return CLOCK_GetRootClockFreq(kCLOCK_Root_Usdhc1);
}
#endif
/* Make sure to pull in the flash headers */
__attribute__((used)) static const void *hdr_dcd = &imxrt_dcd_data;
__attribute__((used)) static const void *hdr_ivt = &imxrt_image_vector_table;

4
bsps/arm/imxrt/start/bspstarthooks.c
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
* Copyright (c) 2013-2023 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -35,8 +35,6 @@
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
/* FIXME: Initializing SDRAM is currently done by DCD. It would be more user
* friendly if that would be done here with a readable structure. */
if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
SCB_EnableICache();
}

4
bsps/arm/imxrt/start/imxrt-ffec-init.c
View File

@@ -41,6 +41,7 @@ void imxrt_ffec_init(void)
fdt = bsp_fdt_get();
#if IMXRT_IS_MIMXRT10xx
const clock_enet_pll_config_t config = {
.enableClkOutput = true,
.enableClkOutput25M = false,
@@ -50,6 +51,9 @@ void imxrt_ffec_init(void)
CLOCK_InitEnetPll(&config);
iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
#else
iomuxc_gpr->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
#endif
node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
if (node >= 0) {

32
spec/build/bsps/arm/imxrt/bspimxrt1166-cm7-saltshaker.yml Normal file
View File

@@ -0,0 +1,32 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: arm
bsp: imxrt1166-cm7-saltshaker
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2023 embedded brains GmbH (http://www.embedded-brains.de)
cppflags: []
enabled-by: true
family: imxrt
includes:
- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166
- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers
- bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/xip
- bsps/arm/imxrt/mcux-sdk/drivers/common
- bsps/arm/imxrt/mcux-sdk/drivers/semc
install:
- destination: ${BSP_INCLUDEDIR}/imxrt
source:
- bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.dts
- bsps/arm/imxrt/include/imxrt/imxrt1166.dtsi
- bsps/arm/imxrt/include/imxrt/imxrt1166-pinfunc.h
links:
- role: build-dependency
uid: obj-mimxrt1166-cm7
source:
- bsps/arm/imxrt/boards/saltshaker/clock_config.c
- bsps/arm/imxrt/boards/saltshaker/dcd.c
- bsps/arm/imxrt/boards/saltshaker/flash-flexspi-config.c
- bsps/arm/imxrt/boards/saltshaker/pin_mux.c
- bsps/arm/imxrt/dts/imxrt1166-cm7-saltshaker.c
type: build

2
spec/build/bsps/arm/imxrt/optmemdtcmsz.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x00040000
- enabled-by: true
value: 0x00020000
description: |

2
spec/build/bsps/arm/imxrt/optmemextramsz.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x04000000
- enabled-by: true
value: 0x02000000
description: |

4
spec/build/bsps/arm/imxrt/optmemflashorigin.yml
View File

@@ -7,12 +7,14 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x30000000
- enabled-by: true
value: 0x60000000
description: |
Origin of the external flash memory. That can be for example a flash
connected to FlexSPI or to SEMC. The default value is for a HyperFlash
connected to FlexSPI.
connected to FlexSPI or a board specific variant for special BSPs.
enabled-by: true
format: '{:#010x}'
links: []

2
spec/build/bsps/arm/imxrt/optmemflashsz.yml
View File

@@ -7,6 +7,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x00800000
- enabled-by: true
value: 0x04000000
description: |

2
spec/build/bsps/arm/imxrt/optmemitcmsz.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x0003ff00
- enabled-by: true
value: 0x0001ff00
description: |

2
spec/build/bsps/arm/imxrt/optmemocramorigin.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2023 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x20340000
- enabled-by: true
value: 0x20200000
description: |

2
spec/build/bsps/arm/imxrt/optmemocramsz.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2021 embedded brains GmbH & Co. KG
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: 0x00040000
- enabled-by: true
value: 0x00040000
description: |

2
spec/build/bsps/arm/imxrt/optvariant.yml
View File

@@ -90,6 +90,8 @@ actions:
conf.define("IMXRT_IS_{}xx".format(value[:8]), True)
build-type: option
default:
- enabled-by: arm/imxrt1166-cm7-saltshaker
value: MIMXRT1166DVM6A_cm7
- enabled-by: true
value: MIMXRT1052DVL6B
enabled-by: true