forked from Imagelibrary/rtems
4a3ace7c7a
The BSP is for a custom i.MXRT1166 based board. At the moment, only the cortex M7 is supported.
91 lines
3.0 KiB
C
91 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2020 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/fdt.h>
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#include <bsp/imx-gpio.h>
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#include <chip.h>
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#include <fsl_clock.h>
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#include <libfdt.h>
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#include <rtems/counter.h>
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void imxrt_ffec_init(void)
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{
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volatile IOMUXC_GPR_Type *iomuxc_gpr = IOMUXC_GPR;
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const void *fdt;
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int node;
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fdt = bsp_fdt_get();
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#if IMXRT_IS_MIMXRT10xx
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const clock_enet_pll_config_t config = {
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.enableClkOutput = true,
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.enableClkOutput25M = false,
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.loopDivider = 1
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};
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CLOCK_InitEnetPll(&config);
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iomuxc_gpr->GPR1 |= IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
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#else
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iomuxc_gpr->GPR4 |= IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
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#endif
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node = fdt_node_offset_by_compatible(fdt, -1, "fsl,imxrt-fec");
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if (node >= 0) {
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struct imx_gpio_pin reset;
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struct imx_gpio_pin interrupt;
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rtems_status_code sc;
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sc = imx_gpio_init_from_fdt_property(
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&reset, node, "phy-reset-gpios",
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IMX_GPIO_MODE_OUTPUT, 0);
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if (sc == RTEMS_SUCCESSFUL) {
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sc = imx_gpio_init_from_fdt_property(
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&interrupt, node, "rtems,phy-interrupt-gpios",
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IMX_GPIO_MODE_INPUT, 0);
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imx_gpio_set_output(&reset, 0);
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if (sc == RTEMS_SUCCESSFUL) {
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/* Force interrupt GPIO to high. Otherwise we
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* get NAND_TREE mode of the PHY. */
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interrupt.mode = IMX_GPIO_MODE_OUTPUT;
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imx_gpio_init(&interrupt);
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imx_gpio_set_output(&interrupt, 1);
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}
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rtems_counter_delay_nanoseconds(100000);
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imx_gpio_set_output(&reset, 1);
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rtems_counter_delay_nanoseconds(5);
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if (sc == RTEMS_SUCCESSFUL) {
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interrupt.mode = IMX_GPIO_MODE_INPUT;
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imx_gpio_init(&interrupt);
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}
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}
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}
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}
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