forked from Imagelibrary/rtems
2005-03-11 Philippe Simons <loki_666@fastmail.fm>
* Makefile.am, configure.ac: Added gp32 BSP. * s3c2400/.cvsignore, s3c2400/Makefile.am, s3c2400/clock/clockdrv.c, s3c2400/include/s3c2400.h, s3c2400/irq/bsp_irq_asm.S, s3c2400/irq/bsp_irq_init.c, s3c2400/irq/irq.c, s3c2400/irq/irq.h, s3c2400/timer/timer.c: New files.
This commit is contained in:
Jay Monkman
@@ -1,3 +1,11 @@
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2005-03-11 Philippe Simons <loki_666@fastmail.fm>
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* Makefile.am, configure.ac: Added gp32 BSP.
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* s3c2400/.cvsignore, s3c2400/Makefile.am, s3c2400/clock/clockdrv.c,
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s3c2400/include/s3c2400.h, s3c2400/irq/bsp_irq_asm.S,
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s3c2400/irq/bsp_irq_init.c, s3c2400/irq/irq.c, s3c2400/irq/irq.h,
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s3c2400/timer/timer.c: New files.
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2005-03-08 Jay Monkman <jtm@lopingdog.com>
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* mc9328mxl/irq/irq.h: Fixed error in declaration of bsp_vector_table.
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@@ -4,7 +4,7 @@
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ACLOCAL_AMFLAGS = -I ../../../aclocal
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SUBDIRS = shared at91rm9200 mc9328mxl
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SUBDIRS = shared at91rm9200 mc9328mxl s3c2400
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all-local: $(TMPINSTALL_FILES)
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@@ -24,14 +24,17 @@ RTEMS_PROG_CCAS
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RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
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AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "at91rm9200" || \
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test "$RTEMS_CPU_MODEL" = "mc9328mxl")
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test "$RTEMS_CPU_MODEL" = "mc9328mxl" || \
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test "$RTEMS_CPU_MODEL" = "s3c2400")
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AM_CONDITIONAL(at91rm9200, test "$RTEMS_CPU_MODEL" = "at91rm9200")
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AM_CONDITIONAL(mc9328mxl, test "$RTEMS_CPU_MODEL" = "mc9328mxl")
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AM_CONDITIONAL(s3c2400, test "$RTEMS_CPU_MODEL" = "s3c2400")
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# Explicitly list all Makefiles here
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AC_CONFIG_FILES([Makefile
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shared/Makefile
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at91rm9200/Makefile
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mc9328mxl/Makefile
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s3c2400/Makefile
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])
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AC_OUTPUT
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2
c/src/lib/libcpu/arm/s3c2400/.cvsignore
Normal file
2
c/src/lib/libcpu/arm/s3c2400/.cvsignore
Normal file
@@ -0,0 +1,2 @@
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Makefile.in
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Makefile
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71
c/src/lib/libcpu/arm/s3c2400/Makefile.am
Normal file
71
c/src/lib/libcpu/arm/s3c2400/Makefile.am
Normal file
@@ -0,0 +1,71 @@
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##
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## $Id$
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##
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noinst_PROGRAMS =
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include $(top_srcdir)/../../../automake/compile.am
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if s3c2400
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include_s3c2400dir = $(includedir)/s3c2400
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include_libcpudir = $(includedir)/libcpu
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include_HEADERS = include/s3c2400.h
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## clock
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noinst_PROGRAMS += clock.rel
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clock_rel_SOURCES = clock/clockdrv.c
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clock_rel_CPPFLAGS = $(AM_CPPFLAGS)
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clock_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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## timer
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noinst_PROGRAMS += timer.rel
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timer_rel_SOURCES = timer/timer.c
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timer_rel_CPPFLAGS = $(AM_CPPFLAGS)
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timer_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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## interrupt
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include_HEADERS += irq/irq.h
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noinst_PROGRAMS += irq.rel
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irq_rel_SOURCES = irq/irq.c irq/bsp_irq_init.c \
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../../../libbsp/arm/shared/irq/irq_init.c irq/bsp_irq_asm.S \
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../../../libbsp/arm/shared/irq/irq_asm.S irq/irq.h
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irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
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irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
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endif
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## --
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all-local: $(PREINSTALL_FILES)
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PREINSTALL_DIRS =
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PREINSTALL_FILES =
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$(PROJECT_INCLUDE)/$(dirstamp):
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@$(mkdir_p) $(PROJECT_INCLUDE)
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@: > $(PROJECT_INCLUDE)/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
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if s3c2400
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$(PROJECT_INCLUDE)/s3c2400/$(dirstamp):
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@$(mkdir_p) $(PROJECT_INCLUDE)/s3c2400
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@: > $(PROJECT_INCLUDE)/s3c2400/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/s3c2400/$(dirstamp)
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$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
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@$(mkdir_p) $(PROJECT_INCLUDE)/libcpu
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@: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
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$(PROJECT_INCLUDE)/s3c2400.h: include/s3c2400.h $(PROJECT_INCLUDE)/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/s3c2400.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/s3c2400.h
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$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
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endif
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CLEANFILES = $(PREINSTALL_FILES)
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DISTCLEANFILES = $(PREINSTALL_DIRS)
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include $(top_srcdir)/../../../automake/local.am
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142
c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c
Normal file
142
c/src/lib/libcpu/arm/s3c2400/clock/clockdrv.c
Normal file
@@ -0,0 +1,142 @@
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/*
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* S3C2400 clock specific using the System Timer
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*
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* This is hardware specific part of the clock driver. At the end of this
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* file, the generic part of the driver is #included.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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*
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* $Id$
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*/
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#include <rtems.h>
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#include <irq.h>
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#include <bsp.h>
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#include <s3c2400.h>
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/* this is defined in ../../../shared/clockdrv_shell.c */
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rtems_isr Clock_isr(rtems_vector_number vector);
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static void clock_isr_on(const rtems_irq_connect_data *unused);
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static void clock_isr_off(const rtems_irq_connect_data *unused);
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static int clock_isr_is_on(const rtems_irq_connect_data *irq);
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/* Replace the first value with the clock's interrupt name. */
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rtems_irq_connect_data clock_isr_data = {BSP_INT_TIMER4,
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(rtems_irq_hdl)Clock_isr,
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clock_isr_on,
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clock_isr_off,
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clock_isr_is_on,
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3, /* unused for ARM cpus */
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0 }; /* unused for ARM cpus */
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/* If you follow the code, this is never used, so any value
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* should work
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*/
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#define CLOCK_VECTOR 0
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/**
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* When we get the clock interrupt
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* - clear the interrupt bit?
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* - restart the timer?
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*/
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#define Clock_driver_support_at_tick() \
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do { \
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ClearPending(BIT_TIMER4); \
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} while(0)
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/**
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* Installs the clock ISR. You shouldn't need to change this.
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*/
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#define Clock_driver_support_install_isr( _new, _old ) \
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do { \
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BSP_install_rtems_irq_handler(&clock_isr_data); \
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} while(0)
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/**
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* Initialize the hardware for the clock
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* - Set the frequency
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* - enable it
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* - clear any pending interrupts
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*
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* Since you may want the clock always running, you can
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* enable interrupts here. If you do so, the clock_isr_on(),
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* clock_isr_off(), and clock_isr_is_on() functions can be
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* NOPs.
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*/
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#define Clock_driver_support_initialize_hardware() \
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do { \
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uint32_t cr; \
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uint32_t freq,m,p,s; \
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/* set MUX for Timer4 to 1/16 */ \
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cr=rTCFG1 & 0xFFF0FFFF; \
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rTCFG1=(cr | (3<<16)); \
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/* compute MPLL freq */ \
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m = M_MDIV + 8; \
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p = M_PDIV + 2; \
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s = M_SDIV; \
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freq =(BSP_OSC_FREQ * m) / (p << s); \
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/* PCLK = MPLL/4 */ \
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freq = freq / 4; \
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/* set TIMER4 counter, input freq=PLCK/16/16Mhz*/ \
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freq = (freq /16)/16; \
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rTCNTB4 = ((freq / 1000) * BSP_Configuration.microseconds_per_tick) / 1000; \
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/*unmask TIMER4 irq*/ \
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rINTMSK&=~BIT_TIMER4; \
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/* start TIMER4 with autoreload */ \
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cr=rTCON & 0xFF8FFFFF; \
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rTCON=(cr|(0x6<<20)); \
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rTCON=(cr|(0x5<<20)); \
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} while (0)
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/**
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* Do whatever you need to shut the clock down and remove the
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* interrupt handler. Since this normally only gets called on
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* RTEMS shutdown, you may not need to do anything other than
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* remove the ISR.
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*/
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#define Clock_driver_support_shutdown_hardware() \
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do { \
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/* Disable timer */ \
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BSP_remove_rtems_irq_handler(&clock_isr_data); \
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} while (0)
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/**
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* Enables clock interrupt.
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*
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* If the interrupt is always on, this can be a NOP.
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*/
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static void clock_isr_on(const rtems_irq_connect_data *unused)
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{
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return;
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}
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/**
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* Disables clock interrupts
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*
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* If the interrupt is always on, this can be a NOP.
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*/
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static void clock_isr_off(const rtems_irq_connect_data *unused)
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{
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return;
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}
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/**
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* Tests to see if clock interrupt is enabled, and returns 1 if so.
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* If interrupt is not enabled, returns 0.
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*
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* If the interrupt is always on, this always returns 1.
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*/
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static int clock_isr_is_on(const rtems_irq_connect_data *irq)
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{
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return 1;
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}
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/* Make sure to include this, and only at the end of the file */
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#include "../../../../libbsp/shared/clockdrv_shell.c"
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444
c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
Normal file
444
c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h
Normal file
@@ -0,0 +1,444 @@
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/************************************************
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* NAME : s3c2400.h
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* Version : 3.7.2002
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*
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* Based on 24x.h for the Samsung Development Board
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************************************************/
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#ifndef __S3C2400_H__
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#define __S3C2400_H__
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/* Memory control */
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#define rBWSCON (*(volatile unsigned *)0x14000000)
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#define rBANKCON0 (*(volatile unsigned *)0x14000004)
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#define rBANKCON1 (*(volatile unsigned *)0x14000008)
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#define rBANKCON2 (*(volatile unsigned *)0x1400000C)
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#define rBANKCON3 (*(volatile unsigned *)0x14000010)
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#define rBANKCON4 (*(volatile unsigned *)0x14000014)
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#define rBANKCON5 (*(volatile unsigned *)0x14000018)
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||||
#define rBANKCON6 (*(volatile unsigned *)0x1400001C)
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||||
#define rBANKCON7 (*(volatile unsigned *)0x14000020)
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||||
#define rREFRESH (*(volatile unsigned *)0x14000024)
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||||
#define rBANKSIZE (*(volatile unsigned *)0x14000028)
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||||
#define rMRSRB6 (*(volatile unsigned *)0x1400002C)
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||||
#define rMRSRB7 (*(volatile unsigned *)0x14000030)
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||||
|
||||
|
||||
/* INTERRUPT */
|
||||
#define rSRCPND (*(volatile unsigned *)0x14400000)
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||||
#define rINTMOD (*(volatile unsigned *)0x14400004)
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||||
#define rINTMSK (*(volatile unsigned *)0x14400008)
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||||
#define rPRIORITY (*(volatile unsigned *)0x1440000C)
|
||||
#define rINTPND (*(volatile unsigned *)0x14400010)
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||||
#define rINTOFFSET (*(volatile unsigned *)0x14400014)
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||||
|
||||
|
||||
/* DMA */
|
||||
#define rDISRC0 (*(volatile unsigned *)0x14600000)
|
||||
#define rDIDST0 (*(volatile unsigned *)0x14600004)
|
||||
#define rDCON0 (*(volatile unsigned *)0x14600008)
|
||||
#define rDSTAT0 (*(volatile unsigned *)0x1460000C)
|
||||
#define rDCSRC0 (*(volatile unsigned *)0x14600010)
|
||||
#define rDCDST0 (*(volatile unsigned *)0x14600014)
|
||||
#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018)
|
||||
#define rDISRC1 (*(volatile unsigned *)0x14600020)
|
||||
#define rDIDST1 (*(volatile unsigned *)0x14600024)
|
||||
#define rDCON1 (*(volatile unsigned *)0x14600028)
|
||||
#define rDSTAT1 (*(volatile unsigned *)0x1460002C)
|
||||
#define rDCSRC1 (*(volatile unsigned *)0x14600030)
|
||||
#define rDCDST1 (*(volatile unsigned *)0x14600034)
|
||||
#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038)
|
||||
#define rDISRC2 (*(volatile unsigned *)0x14600040)
|
||||
#define rDIDST2 (*(volatile unsigned *)0x14600044)
|
||||
#define rDCON2 (*(volatile unsigned *)0x14600048)
|
||||
#define rDSTAT2 (*(volatile unsigned *)0x1460004C)
|
||||
#define rDCSRC2 (*(volatile unsigned *)0x14600050)
|
||||
#define rDCDST2 (*(volatile unsigned *)0x14600054)
|
||||
#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058)
|
||||
#define rDISRC3 (*(volatile unsigned *)0x14600060)
|
||||
#define rDIDST3 (*(volatile unsigned *)0x14600064)
|
||||
#define rDCON3 (*(volatile unsigned *)0x14600068)
|
||||
#define rDSTAT3 (*(volatile unsigned *)0x1460006C)
|
||||
#define rDCSRC3 (*(volatile unsigned *)0x14600070)
|
||||
#define rDCDST3 (*(volatile unsigned *)0x14600074)
|
||||
#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078)
|
||||
|
||||
|
||||
/* CLOCK & POWER MANAGEMENT */
|
||||
#define rLOCKTIME (*(volatile unsigned *)0x14800000)
|
||||
#define rMPLLCON (*(volatile unsigned *)0x14800004)
|
||||
#define rUPLLCON (*(volatile unsigned *)0x14800008)
|
||||
#define rCLKCON (*(volatile unsigned *)0x1480000C)
|
||||
#define rCLKSLOW (*(volatile unsigned *)0x14800010)
|
||||
#define rCLKDIVN (*(volatile unsigned *)0x14800014)
|
||||
|
||||
|
||||
/* LCD CONTROLLER */
|
||||
#define rLCDCON1 (*(volatile unsigned *)0x14A00000)
|
||||
#define rLCDCON2 (*(volatile unsigned *)0x14A00004)
|
||||
#define rLCDCON3 (*(volatile unsigned *)0x14A00008)
|
||||
#define rLCDCON4 (*(volatile unsigned *)0x14A0000C)
|
||||
#define rLCDCON5 (*(volatile unsigned *)0x14A00010)
|
||||
#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014)
|
||||
#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018)
|
||||
#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C)
|
||||
#define rREDLUT (*(volatile unsigned *)0x14A00020)
|
||||
#define rGREENLUT (*(volatile unsigned *)0x14A00024)
|
||||
#define rBLUELUT (*(volatile unsigned *)0x14A00028)
|
||||
#define rDP1_2 (*(volatile unsigned *)0x14A0002C)
|
||||
#define rDP4_7 (*(volatile unsigned *)0x14A00030)
|
||||
#define rDP3_5 (*(volatile unsigned *)0x14A00034)
|
||||
#define rDP2_3 (*(volatile unsigned *)0x14A00038)
|
||||
#define rDP5_7 (*(volatile unsigned *)0x14A0003c)
|
||||
#define rDP3_4 (*(volatile unsigned *)0x14A00040)
|
||||
#define rDP4_5 (*(volatile unsigned *)0x14A00044)
|
||||
#define rDP6_7 (*(volatile unsigned *)0x14A00048)
|
||||
#define rDITHMODE (*(volatile unsigned *)0x14A0004C)
|
||||
#define rTPAL (*(volatile unsigned *)0x14A00050)
|
||||
#define GP32_PALETTE (*(volatile unsigned *)0x14A00400) /* SJS */
|
||||
|
||||
|
||||
/* UART */
|
||||
#define rULCON0 (*(volatile unsigned char *)0x15000000)
|
||||
#define rUCON0 (*(volatile unsigned short *)0x15000004)
|
||||
#define rUFCON0 (*(volatile unsigned char *)0x15000008)
|
||||
#define rUMCON0 (*(volatile unsigned char *)0x1500000C)
|
||||
#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010)
|
||||
#define rUERSTAT0 (*(volatile unsigned char *)0x15000014)
|
||||
#define rUFSTAT0 (*(volatile unsigned short *)0x15000018)
|
||||
#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C)
|
||||
#define rUBRDIV0 (*(volatile unsigned short *)0x15000028)
|
||||
|
||||
#define rULCON1 (*(volatile unsigned char *)0x15004000)
|
||||
#define rUCON1 (*(volatile unsigned short *)0x15004004)
|
||||
#define rUFCON1 (*(volatile unsigned char *)0x15004008)
|
||||
#define rUMCON1 (*(volatile unsigned char *)0x1500400C)
|
||||
#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010)
|
||||
#define rUERSTAT1 (*(volatile unsigned char *)0x15004014)
|
||||
#define rUFSTAT1 (*(volatile unsigned short *)0x15004018)
|
||||
#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C)
|
||||
#define rUBRDIV1 (*(volatile unsigned short *)0x15004028)
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
#define rUTXH0 (*(volatile unsigned char *)0x15000023)
|
||||
#define rURXH0 (*(volatile unsigned char *)0x15000027)
|
||||
#define rUTXH1 (*(volatile unsigned char *)0x15004023)
|
||||
#define rURXH1 (*(volatile unsigned char *)0x15004027)
|
||||
|
||||
#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
|
||||
#define RdURXH0() (*(volatile unsigned char *)0x15000027)
|
||||
#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
|
||||
#define RdURXH1() (*(volatile unsigned char *)0x15004027)
|
||||
|
||||
#define UTXH0 (0x15000020+3) /* byte_access address by DMA */
|
||||
#define URXH0 (0x15000024+3)
|
||||
#define UTXH1 (0x15004020+3)
|
||||
#define URXH1 (0x15004024+3)
|
||||
|
||||
#else /* Little Endian */
|
||||
#define rUTXH0 (*(volatile unsigned char *)0x15000020)
|
||||
#define rURXH0 (*(volatile unsigned char *)0x15000024)
|
||||
#define rUTXH1 (*(volatile unsigned char *)0x15004020)
|
||||
#define rURXH1 (*(volatile unsigned char *)0x15004024)
|
||||
|
||||
#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
|
||||
#define RdURXH0() (*(volatile unsigned char *)0x15000024)
|
||||
#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
|
||||
#define RdURXH1() (*(volatile unsigned char *)0x15004024)
|
||||
|
||||
#define UTXH0 (0x15000020) /* byte_access address by DMA */
|
||||
#define URXH0 (0x15000024)
|
||||
#define UTXH1 (0x15004020)
|
||||
#define URXH1 (0x15004024)
|
||||
#endif
|
||||
|
||||
|
||||
/* PWM TIMER */
|
||||
#define rTCFG0 (*(volatile unsigned *)0x15100000)
|
||||
#define rTCFG1 (*(volatile unsigned *)0x15100004)
|
||||
#define rTCON (*(volatile unsigned *)0x15100008)
|
||||
#define rTCNTB0 (*(volatile unsigned *)0x1510000C)
|
||||
#define rTCMPB0 (*(volatile unsigned *)0x15100010)
|
||||
#define rTCNTO0 (*(volatile unsigned *)0x15100014)
|
||||
#define rTCNTB1 (*(volatile unsigned *)0x15100018)
|
||||
#define rTCMPB1 (*(volatile unsigned *)0x1510001C)
|
||||
#define rTCNTO1 (*(volatile unsigned *)0x15100020)
|
||||
#define rTCNTB2 (*(volatile unsigned *)0x15100024)
|
||||
#define rTCMPB2 (*(volatile unsigned *)0x15100028)
|
||||
#define rTCNTO2 (*(volatile unsigned *)0x1510002C)
|
||||
#define rTCNTB3 (*(volatile unsigned *)0x15100030)
|
||||
#define rTCMPB3 (*(volatile unsigned *)0x15100034)
|
||||
#define rTCNTO3 (*(volatile unsigned *)0x15100038)
|
||||
#define rTCNTB4 (*(volatile unsigned *)0x1510003C)
|
||||
#define rTCNTO4 (*(volatile unsigned *)0x15100040)
|
||||
|
||||
|
||||
/* USB DEVICE */
|
||||
#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140)
|
||||
#define rPWR_REG (*(volatile unsigned *)0x15200144)
|
||||
#define rINT_REG (*(volatile unsigned *)0x15200148)
|
||||
#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C)
|
||||
#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150)
|
||||
#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
|
||||
#define rEP0_CSR (*(volatile unsigned *)0x15200160)
|
||||
#define rEP0_MAXP (*(volatile unsigned *)0x15200164)
|
||||
#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168)
|
||||
#define rEP0_FIFO (*(volatile unsigned *)0x1520016C)
|
||||
#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180)
|
||||
#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184)
|
||||
#define rEP1_FIFO (*(volatile unsigned *)0x15200188)
|
||||
#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190)
|
||||
#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194)
|
||||
#define rEP2_FIFO (*(volatile unsigned *)0x15200198)
|
||||
#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0)
|
||||
#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4)
|
||||
#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8)
|
||||
#define rEP3_FIFO (*(volatile unsigned *)0x152001AC)
|
||||
#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0)
|
||||
#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4)
|
||||
#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8)
|
||||
#define rEP4_FIFO (*(volatile unsigned *)0x152001BC)
|
||||
#define rDMA_CON (*(volatile unsigned *)0x152001C0)
|
||||
#define rDMA_UNIT (*(volatile unsigned *)0x152001C4)
|
||||
#define rDMA_FIFO (*(volatile unsigned *)0x152001C8)
|
||||
#define rDMA_TX (*(volatile unsigned *)0x152001CC)
|
||||
#define rTEST_MODE (*(volatile unsigned *)0x152001F4)
|
||||
#define rIN_CON_REG (*(volatile unsigned *)0x152001F8)
|
||||
|
||||
|
||||
/* WATCH DOG TIMER */
|
||||
#define rWTCON (*(volatile unsigned *)0x15300000)
|
||||
#define rWTDAT (*(volatile unsigned *)0x15300004)
|
||||
#define rWTCNT (*(volatile unsigned *)0x15300008)
|
||||
|
||||
|
||||
/* IIC */
|
||||
#define rIICCON (*(volatile unsigned *)0x15400000)
|
||||
#define rIICSTAT (*(volatile unsigned *)0x15400004)
|
||||
#define rIICADD (*(volatile unsigned *)0x15400008)
|
||||
#define rIICDS (*(volatile unsigned *)0x1540000C)
|
||||
|
||||
|
||||
/* IIS */
|
||||
#define rIISCON (*(volatile unsigned *)0x15508000)
|
||||
#define rIISMOD (*(volatile unsigned *)0x15508004)
|
||||
#define rIISPSR (*(volatile unsigned *)0x15508008)
|
||||
#define rIISFIFCON (*(volatile unsigned *)0x1550800C)
|
||||
|
||||
#ifdef __BIG_ENDIAN
|
||||
#define IISFIF ((volatile unsigned short *)0x15508012)
|
||||
|
||||
#else /* Little Endian */
|
||||
#define IISFIF ((volatile unsigned short *)0x15508010)
|
||||
#endif
|
||||
|
||||
|
||||
/* I/O PORT */
|
||||
#define rPACON (*(volatile unsigned *)0x15600000)
|
||||
#define rPADAT (*(volatile unsigned *)0x15600004)
|
||||
|
||||
#define rPBCON (*(volatile unsigned *)0x15600008)
|
||||
#define rPBDAT (*(volatile unsigned *)0x1560000C)
|
||||
#define rPBUP (*(volatile unsigned *)0x15600010)
|
||||
|
||||
#define rPCCON (*(volatile unsigned *)0x15600014)
|
||||
#define rPCDAT (*(volatile unsigned *)0x15600018)
|
||||
#define rPCUP (*(volatile unsigned *)0x1560001C)
|
||||
|
||||
#define rPDCON (*(volatile unsigned *)0x15600020)
|
||||
#define rPDDAT (*(volatile unsigned *)0x15600024)
|
||||
#define rPDUP (*(volatile unsigned *)0x15600028)
|
||||
|
||||
#define rPECON (*(volatile unsigned *)0x1560002C)
|
||||
#define rPEDAT (*(volatile unsigned *)0x15600030)
|
||||
#define rPEUP (*(volatile unsigned *)0x15600034)
|
||||
|
||||
#define rPFCON (*(volatile unsigned *)0x15600038)
|
||||
#define rPFDAT (*(volatile unsigned *)0x1560003C)
|
||||
#define rPFUP (*(volatile unsigned *)0x15600040)
|
||||
|
||||
#define rPGCON (*(volatile unsigned *)0x15600044)
|
||||
#define rPGDAT (*(volatile unsigned *)0x15600048)
|
||||
#define rPGUP (*(volatile unsigned *)0x1560004C)
|
||||
|
||||
#define rOPENCR (*(volatile unsigned *)0x15600050)
|
||||
#define rMISCCR (*(volatile unsigned *)0x15600054)
|
||||
#define rEXTINT (*(volatile unsigned *)0x15600058)
|
||||
|
||||
|
||||
/* RTC */
|
||||
#ifdef __BIG_ENDIAN
|
||||
#define rRTCCON (*(volatile unsigned char *)0x15700043)
|
||||
#define rRTCALM (*(volatile unsigned char *)0x15700053)
|
||||
#define rALMSEC (*(volatile unsigned char *)0x15700057)
|
||||
#define rALMMIN (*(volatile unsigned char *)0x1570005B)
|
||||
#define rALMHOUR (*(volatile unsigned char *)0x1570005F)
|
||||
#define rALMDAY (*(volatile unsigned char *)0x15700063)
|
||||
#define rALMMON (*(volatile unsigned char *)0x15700067)
|
||||
#define rALMYEAR (*(volatile unsigned char *)0x1570006B)
|
||||
#define rRTCRST (*(volatile unsigned char *)0x1570006F)
|
||||
#define rBCDSEC (*(volatile unsigned char *)0x15700073)
|
||||
#define rBCDMIN (*(volatile unsigned char *)0x15700077)
|
||||
#define rBCDHOUR (*(volatile unsigned char *)0x1570007B)
|
||||
#define rBCDDAY (*(volatile unsigned char *)0x1570007F)
|
||||
#define rBCDDATE (*(volatile unsigned char *)0x15700083)
|
||||
#define rBCDMON (*(volatile unsigned char *)0x15700087)
|
||||
#define rBCDYEAR (*(volatile unsigned char *)0x1570008B)
|
||||
#define rTICINT (*(volatile unsigned char *)0x15700047)
|
||||
|
||||
#else /* Little Endian */
|
||||
#define rRTCCON (*(volatile unsigned char *)0x15700040)
|
||||
#define rRTCALM (*(volatile unsigned char *)0x15700050)
|
||||
#define rALMSEC (*(volatile unsigned char *)0x15700054)
|
||||
#define rALMMIN (*(volatile unsigned char *)0x15700058)
|
||||
#define rALMHOUR (*(volatile unsigned char *)0x1570005C)
|
||||
#define rALMDAY (*(volatile unsigned char *)0x15700060)
|
||||
#define rALMMON (*(volatile unsigned char *)0x15700064)
|
||||
#define rALMYEAR (*(volatile unsigned char *)0x15700068)
|
||||
#define rRTCRST (*(volatile unsigned char *)0x1570006C)
|
||||
#define rBCDSEC (*(volatile unsigned char *)0x15700070)
|
||||
#define rBCDMIN (*(volatile unsigned char *)0x15700074)
|
||||
#define rBCDHOUR (*(volatile unsigned char *)0x15700078)
|
||||
#define rBCDDAY (*(volatile unsigned char *)0x1570007C)
|
||||
#define rBCDDATE (*(volatile unsigned char *)0x15700080)
|
||||
#define rBCDMON (*(volatile unsigned char *)0x15700084)
|
||||
#define rBCDYEAR (*(volatile unsigned char *)0x15700088)
|
||||
#define rTICINT (*(volatile unsigned char *)0x15700044)
|
||||
#endif
|
||||
|
||||
|
||||
/* ADC */
|
||||
#define rADCCON (*(volatile unsigned *)0x15800000)
|
||||
#define rADCDAT (*(volatile unsigned *)0x15800004)
|
||||
|
||||
|
||||
/* SPI */
|
||||
#define rSPCON (*(volatile unsigned *)0x15900000)
|
||||
#define rSPSTA (*(volatile unsigned *)0x15900004)
|
||||
#define rSPPIN (*(volatile unsigned *)0x15900008)
|
||||
#define rSPPRE (*(volatile unsigned *)0x1590000C)
|
||||
#define rSPTDAT (*(volatile unsigned *)0x15900010)
|
||||
#define rSPRDAT (*(volatile unsigned *)0x15900014)
|
||||
|
||||
|
||||
/* MMC INTERFACE */
|
||||
#define rMMCON (*(volatile unsigned *)0x15a00000)
|
||||
#define rMMCRR (*(volatile unsigned *)0x15a00004)
|
||||
#define rMMFCON (*(volatile unsigned *)0x15a00008)
|
||||
#define rMMSTA (*(volatile unsigned *)0x15a0000C)
|
||||
#define rMMFSTA (*(volatile unsigned *)0x15a00010)
|
||||
#define rMMPRE (*(volatile unsigned *)0x15a00014)
|
||||
#define rMMLEN (*(volatile unsigned *)0x15a00018)
|
||||
#define rMMCR7 (*(volatile unsigned *)0x15a0001C)
|
||||
#define rMMRSP0 (*(volatile unsigned *)0x15a00020)
|
||||
#define rMMRSP1 (*(volatile unsigned *)0x15a00024)
|
||||
#define rMMRSP2 (*(volatile unsigned *)0x15a00028)
|
||||
#define rMMRSP3 (*(volatile unsigned *)0x15a0002C)
|
||||
#define rMMCMD0 (*(volatile unsigned *)0x15a00030)
|
||||
#define rMMCMD1 (*(volatile unsigned *)0x15a00034)
|
||||
#define rMMCR16 (*(volatile unsigned *)0x15a00038)
|
||||
#define rMMDAT (*(volatile unsigned *)0x15a0003C)
|
||||
|
||||
|
||||
#define _ISR_STARTADDRESS rtems_vector_table
|
||||
/* ISR */
|
||||
#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
|
||||
#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
|
||||
#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
|
||||
#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
|
||||
#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
|
||||
#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
|
||||
#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
|
||||
#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
|
||||
|
||||
#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
|
||||
#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
|
||||
#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
|
||||
#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
|
||||
#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
|
||||
#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
|
||||
#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38))
|
||||
#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
|
||||
#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
|
||||
#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
|
||||
#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
|
||||
#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
|
||||
#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
|
||||
#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
|
||||
#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
|
||||
#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
|
||||
#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
|
||||
#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
|
||||
#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
|
||||
#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
|
||||
#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
|
||||
#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74))
|
||||
#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78))
|
||||
#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
|
||||
#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80))
|
||||
#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
|
||||
#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
|
||||
#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
|
||||
#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
|
||||
#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
|
||||
#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
|
||||
#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
|
||||
|
||||
|
||||
/* PENDING BIT */
|
||||
#define BIT_EINT0 (0x1)
|
||||
#define BIT_EINT1 (0x1<<1)
|
||||
#define BIT_EINT2 (0x1<<2)
|
||||
#define BIT_EINT3 (0x1<<3)
|
||||
#define BIT_EINT4 (0x1<<4)
|
||||
#define BIT_EINT5 (0x1<<5)
|
||||
#define BIT_EINT6 (0x1<<6)
|
||||
#define BIT_EINT7 (0x1<<7)
|
||||
#define BIT_TICK (0x1<<8)
|
||||
#define BIT_WDT (0x1<<9)
|
||||
#define BIT_TIMER0 (0x1<<10)
|
||||
#define BIT_TIMER1 (0x1<<11)
|
||||
#define BIT_TIMER2 (0x1<<12)
|
||||
#define BIT_TIMER3 (0x1<<13)
|
||||
#define BIT_TIMER4 (0x1<<14)
|
||||
#define BIT_UERR01 (0x1<<15)
|
||||
#define BIT_NOTUSED (0x1<<16)
|
||||
#define BIT_DMA0 (0x1<<17)
|
||||
#define BIT_DMA1 (0x1<<18)
|
||||
#define BIT_DMA2 (0x1<<19)
|
||||
#define BIT_DMA3 (0x1<<20)
|
||||
#define BIT_MMC (0x1<<21)
|
||||
#define BIT_SPI (0x1<<22)
|
||||
#define BIT_URXD0 (0x1<<23)
|
||||
#define BIT_URXD1 (0x1<<24)
|
||||
#define BIT_USBD (0x1<<25)
|
||||
#define BIT_USBH (0x1<<26)
|
||||
#define BIT_IIC (0x1<<27)
|
||||
#define BIT_UTXD0 (0x1<<28)
|
||||
#define BIT_UTXD1 (0x1<<29)
|
||||
#define BIT_RTC (0x1<<30)
|
||||
#define BIT_ADC (0x1<<31)
|
||||
#define BIT_ALLMSK (0xFFFFFFFF)
|
||||
|
||||
#define ClearPending(bit) {\
|
||||
rSRCPND = bit;\
|
||||
rINTPND = bit;\
|
||||
rINTPND;\
|
||||
}
|
||||
/* Wait until rINTPND is changed for the case that the ISR is very short. */
|
||||
#define LCD_WIDTH 240
|
||||
#define LCD_HEIGH 320
|
||||
#define LCD_ASPECT ((flaot)(LCD_WIDTH/LCD_HEIGHT))
|
||||
|
||||
#define GP32_KEY_SELECT 512
|
||||
#define GP32_KEY_START 256
|
||||
#define GP32_KEY_A 64
|
||||
#define GP32_KEY_B 32
|
||||
#define GP32_KEY_L 16
|
||||
#define GP32_KEY_R 128
|
||||
#define GP32_KEY_UP 8
|
||||
#define GP32_KEY_DOWN 2
|
||||
#define GP32_KEY_LEFT 1
|
||||
#define GP32_KEY_RIGHT 4
|
||||
|
||||
#endif /*__S3C2400_H__*/
|
||||
40
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S
Normal file
40
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S
Normal file
@@ -0,0 +1,40 @@
|
||||
/* bsp_irq_asm.S
|
||||
*
|
||||
* This file contains the implementation of the IRQ handler
|
||||
* for a specific BSP
|
||||
*
|
||||
* CopyRight (C) 2000 Canon Research France SA.
|
||||
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#define __asm__
|
||||
|
||||
/*
|
||||
* Function to obtain, execute an IT handler and acknowledge the IT
|
||||
*/
|
||||
|
||||
.globl ExecuteITHandler
|
||||
|
||||
ExecuteITHandler :
|
||||
|
||||
ldr r0, =0x14400014 /* Read rINTOFFSET */
|
||||
ldr r1, [r0]
|
||||
|
||||
ldr r0, =bsp_vector_table
|
||||
ldr r0, [r0, r1, LSL #2] /* Read the address */
|
||||
|
||||
stmdb sp!,{lr}
|
||||
ldr lr, =IRQ_return /* prepare the return from handler */
|
||||
|
||||
mov pc, r0
|
||||
|
||||
IRQ_return:
|
||||
ldmia sp!,{lr}
|
||||
|
||||
mov pc, lr
|
||||
27
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c
Normal file
27
c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c
Normal file
@@ -0,0 +1,27 @@
|
||||
/* irq_init.c
|
||||
*
|
||||
* This file contains the implementation of rtems initialization
|
||||
* related to interrupt handling.
|
||||
*
|
||||
* CopyRight (C) 2000 Canon Research Centre France SA.
|
||||
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
#include <irq.h>
|
||||
#include <bsp.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
extern void default_int_handler();
|
||||
|
||||
void BSP_rtems_irq_mngt_init()
|
||||
{
|
||||
/*
|
||||
* Here is the code to initialize the INT for
|
||||
* the specified BSP
|
||||
*/
|
||||
}
|
||||
110
c/src/lib/libcpu/arm/s3c2400/irq/irq.c
Normal file
110
c/src/lib/libcpu/arm/s3c2400/irq/irq.c
Normal file
@@ -0,0 +1,110 @@
|
||||
/* irq.c
|
||||
*
|
||||
* This file contains the implementation of the function described in irq.h
|
||||
*
|
||||
* CopyRight (C) 2000 Canon Research France SA.
|
||||
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
|
||||
#include <bsp.h>
|
||||
#include <irq.h>
|
||||
#include <rtems/score/thread.h>
|
||||
#include <rtems/score/apiext.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
/*
|
||||
* This function check that the value given for the irq line
|
||||
* is valid.
|
||||
*/
|
||||
|
||||
static int isValidInterrupt(int irq)
|
||||
{
|
||||
if ( (irq < 0) || (irq > BSP_MAX_INT)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* ------------------- RTEMS Single Irq Handler Mngt Routines ----------------
|
||||
*/
|
||||
|
||||
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
|
||||
{
|
||||
rtems_irq_hdl *HdlTable;
|
||||
rtems_interrupt_level level;
|
||||
|
||||
if (!isValidInterrupt(irq->name)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if default handler is actually connected. If not issue an error.
|
||||
*/
|
||||
HdlTable = VECTOR_TABLE;
|
||||
if (*(HdlTable + irq->name) != default_int_handler) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
_CPU_ISR_Disable(level);
|
||||
|
||||
/*
|
||||
* store the new handler
|
||||
*/
|
||||
*(HdlTable + irq->name) = irq->hdl;
|
||||
|
||||
/*
|
||||
* Enable interrupt on device
|
||||
*/
|
||||
if(irq->on)
|
||||
{
|
||||
irq->on(irq);
|
||||
}
|
||||
|
||||
_CPU_ISR_Enable(level);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
|
||||
{
|
||||
rtems_irq_hdl *HdlTable;
|
||||
rtems_interrupt_level level;
|
||||
|
||||
if (!isValidInterrupt(irq->name)) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the handler is actually connected. If not issue an error.
|
||||
*/
|
||||
HdlTable = VECTOR_TABLE;
|
||||
if (*(HdlTable + irq->name) != irq->hdl) {
|
||||
return 0;
|
||||
}
|
||||
_CPU_ISR_Disable(level);
|
||||
|
||||
/*
|
||||
* Disable interrupt on device
|
||||
*/
|
||||
if(irq->off) {
|
||||
irq->off(irq);
|
||||
}
|
||||
|
||||
/*
|
||||
* restore the default irq value
|
||||
*/
|
||||
*(HdlTable + irq->name) = default_int_handler;
|
||||
|
||||
_CPU_ISR_Enable(level);
|
||||
|
||||
return 1;
|
||||
}
|
||||
207
c/src/lib/libcpu/arm/s3c2400/irq/irq.h
Normal file
207
c/src/lib/libcpu/arm/s3c2400/irq/irq.h
Normal file
@@ -0,0 +1,207 @@
|
||||
/* irq.h
|
||||
*
|
||||
* This include file describe the data structure and the functions implemented
|
||||
* by rtems to write interrupt handlers.
|
||||
*
|
||||
* Copyright (c) 2000 Canon Research Centre France SA.
|
||||
* Emmanuel Raguet, mailto:raguet@crf.canon.fr
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in found in the file LICENSE in this distribution or at
|
||||
* http://www.rtems.com/license/LICENSE.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#ifndef _IRQ_H_
|
||||
#define _IRQ_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Include some preprocessor value also used by assember code
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
extern void default_int_handler();
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Constants
|
||||
+--------------------------------------------------------------------------*/
|
||||
|
||||
/* enum of the possible interrupt sources */
|
||||
typedef enum {
|
||||
BSP_EINT0 = 0,
|
||||
BSP_EINT1,
|
||||
BSP_EINT2,
|
||||
BSP_EINT3,
|
||||
BSP_EINT4,
|
||||
BSP_EINT5,
|
||||
BSP_EINT6,
|
||||
BSP_EINT7,
|
||||
BSP_INT_TICK,
|
||||
BSP_INT_WDT,
|
||||
BSP_INT_TIMER0,
|
||||
BSP_INT_TIMER1,
|
||||
BSP_INT_TIMER2,
|
||||
BSP_INT_TIMER3,
|
||||
BSP_INT_TIMER4,
|
||||
BSP_INT_UERR01,
|
||||
_res0,
|
||||
BSP_INT_DMA0,
|
||||
BSP_INT_DMA1,
|
||||
BSP_INT_DMA2,
|
||||
BSP_INT_DMA3,
|
||||
BSP_INT_MMC,
|
||||
BSP_INT_SPI,
|
||||
BSP_INT_URXD0,
|
||||
BSP_INT_URXD1,
|
||||
BSP_INT_USBD,
|
||||
BSP_INT_USBH,
|
||||
BSP_INT_IIC,
|
||||
BSP_INT_UTXD0,
|
||||
BSP_INT_UTXD1,
|
||||
BSP_INT_RTC,
|
||||
BSP_INT_ADC,
|
||||
|
||||
BSP_MAX_INT
|
||||
} rtems_irq_symbolic_name;
|
||||
|
||||
extern void *bsp_vector_table;
|
||||
#define VECTOR_TABLE &bsp_vector_table
|
||||
|
||||
/*
|
||||
* Type definition for RTEMS managed interrupts
|
||||
*/
|
||||
typedef unsigned char rtems_irq_level;
|
||||
typedef unsigned char rtems_irq_trigger;
|
||||
|
||||
struct __rtems_irq_connect_data__; /* forward declaratiuon */
|
||||
|
||||
typedef void (*rtems_irq_hdl) (void);
|
||||
typedef void (*rtems_irq_enable) (const struct __rtems_irq_connect_data__*);
|
||||
typedef void (*rtems_irq_disable) (const struct __rtems_irq_connect_data__*);
|
||||
typedef int (*rtems_irq_is_enabled) (const struct __rtems_irq_connect_data__*);
|
||||
|
||||
typedef struct __rtems_irq_connect_data__ {
|
||||
/*
|
||||
* IRQ line
|
||||
*/
|
||||
rtems_irq_symbolic_name name;
|
||||
|
||||
/*
|
||||
* handler. See comment on handler properties below in function prototype.
|
||||
*/
|
||||
rtems_irq_hdl hdl;
|
||||
|
||||
/*
|
||||
* function for enabling interrupts at device level (ONLY!).
|
||||
* The BSP code will automatically enable it at i8259s level.
|
||||
* RATIONALE : anyway such code has to exist in current driver code.
|
||||
* It is usually called immediately AFTER connecting the interrupt handler.
|
||||
* RTEMS may well need such a function when restoring normal interrupt
|
||||
* processing after a debug session.
|
||||
*
|
||||
*/
|
||||
rtems_irq_enable on;
|
||||
|
||||
/*
|
||||
* function for disabling interrupts at device level (ONLY!).
|
||||
* The code will disable it at i8259s level. RATIONALE : anyway
|
||||
* such code has to exist for clean shutdown. It is usually called
|
||||
* BEFORE disconnecting the interrupt. RTEMS may well need such
|
||||
* a function when disabling normal interrupt processing for
|
||||
* a debug session. May well be a NOP function.
|
||||
*/
|
||||
rtems_irq_disable off;
|
||||
|
||||
/*
|
||||
* function enabling to know what interrupt may currently occur
|
||||
* if someone manipulates the i8259s interrupt mask without care...
|
||||
*/
|
||||
rtems_irq_is_enabled isOn;
|
||||
|
||||
/*
|
||||
* priority level at the vplus level
|
||||
*/
|
||||
rtems_irq_level irqLevel;
|
||||
|
||||
/*
|
||||
* Trigger way : Rising or falling edge or High or low level
|
||||
*/
|
||||
rtems_irq_trigger irqTrigger;
|
||||
|
||||
} rtems_irq_connect_data;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Function Prototypes.
|
||||
+--------------------------------------------------------------------------*/
|
||||
/*
|
||||
* ------------------ RTEMS Single Irq Handler Mngt Routines ----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* function to initialize the interrupt for a specific BSP
|
||||
*/
|
||||
void BSP_rtems_irq_mngt_init();
|
||||
|
||||
|
||||
/*
|
||||
* function to connect a particular irq handler. This hanlder will NOT be called
|
||||
* directly as the result of the corresponding interrupt. Instead, a RTEMS
|
||||
* irq prologue will be called that will :
|
||||
*
|
||||
* 1) save the C scratch registers,
|
||||
* 2) switch to a interrupt stack if the interrupt is not nested,
|
||||
* 3) store the current i8259s' interrupt masks
|
||||
* 4) modify them to disable the current interrupt at 8259 level (and may
|
||||
* be others depending on software priorities)
|
||||
* 5) aknowledge the i8259s',
|
||||
* 6) demask the processor,
|
||||
* 7) call the application handler
|
||||
*
|
||||
* As a result the hdl function provided
|
||||
*
|
||||
* a) can perfectly be written is C,
|
||||
* b) may also well directly call the part of the RTEMS API that can be used
|
||||
* from interrupt level,
|
||||
* c) It only responsible for handling the jobs that need to be done at
|
||||
* the device level including (aknowledging/re-enabling the interrupt at device,
|
||||
* level, getting the data,...)
|
||||
*
|
||||
* When returning from the function, the following will be performed by
|
||||
* the RTEMS irq epilogue :
|
||||
*
|
||||
* 1) masks the interrupts again,
|
||||
* 2) restore the original i8259s' interrupt masks
|
||||
* 3) switch back on the orinal stack if needed,
|
||||
* 4) perform rescheduling when necessary,
|
||||
* 5) restore the C scratch registers...
|
||||
* 6) restore initial execution flow
|
||||
*
|
||||
*/
|
||||
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
|
||||
|
||||
/*
|
||||
* function to get the current RTEMS irq handler for ptr->name. It enables to
|
||||
* define hanlder chain...
|
||||
*/
|
||||
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);
|
||||
|
||||
/*
|
||||
* function to get disconnect the RTEMS irq handler for ptr->name.
|
||||
* This function checks that the value given is the current one for safety reason.
|
||||
* The user can use the previous function to get it.
|
||||
*/
|
||||
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data*);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _IRQ_H_ */
|
||||
/* end of include file */
|
||||
132
c/src/lib/libcpu/arm/s3c2400/timer/timer.c
Normal file
132
c/src/lib/libcpu/arm/s3c2400/timer/timer.c
Normal file
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* S3C2400 Timer driver
|
||||
*
|
||||
* This uses timer 1 for timing measurments.
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
*
|
||||
* http://www.OARcorp.com/rtems/license.html.
|
||||
*
|
||||
* Notes:
|
||||
* This file manages the benchmark timer used by the RTEMS Timing Test
|
||||
* Suite. Each measured time period is demarcated by calls to
|
||||
* Timer_initialize() and Read_timer(). Read_timer() usually returns
|
||||
* the number of microseconds since Timer_initialize() exitted.
|
||||
*
|
||||
* It is important that the timer start/stop overhead be determined
|
||||
* when porting or modifying this code.
|
||||
*
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
#include <s3c2400.h>
|
||||
|
||||
uint32_t g_start;
|
||||
uint32_t g_freq;
|
||||
|
||||
rtems_boolean Timer_driver_Find_average_overhead;
|
||||
|
||||
|
||||
/*
|
||||
* Set up Timer 1
|
||||
*/
|
||||
void Timer_initialize( void )
|
||||
{
|
||||
uint32_t cr;
|
||||
uint32_t m;
|
||||
uint32_t p;
|
||||
uint32_t s;
|
||||
|
||||
/* stop TIMER1*/
|
||||
cr=rTCON & 0xFFFFF0FF;
|
||||
rTCON=(cr | (0x0 << 8));
|
||||
|
||||
/* set MUX for Timer1 to 1/2 */
|
||||
cr=rTCFG1 & 0xFFFFFF0F;
|
||||
rTCFG1=(cr | (0<<4));
|
||||
|
||||
/* compute MPLL freq */
|
||||
m = M_MDIV + 8;
|
||||
p = M_PDIV + 2;
|
||||
s = M_SDIV;
|
||||
g_freq =(BSP_OSC_FREQ * m) / (p << s);
|
||||
|
||||
/* PCLK = MPLL/4 */
|
||||
g_freq = g_freq / 4;
|
||||
|
||||
/* input freq=PLCK/2 Mhz*/
|
||||
g_freq = g_freq / 2000;
|
||||
rTCNTB1 = 0xFFFF;
|
||||
|
||||
/* start TIMER1 with manual reload */
|
||||
cr=rTCON & 0xFFFFF0FF;
|
||||
rTCON=(cr | (0x1 << 9));
|
||||
rTCON=(cr | (0x1 << 8));
|
||||
|
||||
g_start = rTCNTO1;
|
||||
}
|
||||
|
||||
/*
|
||||
* The following controls the behavior of Read_timer().
|
||||
*
|
||||
* AVG_OVEREHAD is the overhead for starting and stopping the timer. It
|
||||
* is usually deducted from the number returned.
|
||||
*
|
||||
* LEAST_VALID is the lowest number this routine should trust. Numbers
|
||||
* below this are "noise" and zero is returned.
|
||||
*/
|
||||
|
||||
#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */
|
||||
/* (Y countdowns) to start/stop the timer. */
|
||||
/* This value is in microseconds. */
|
||||
#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */
|
||||
|
||||
int Read_timer( void )
|
||||
{
|
||||
uint32_t t;
|
||||
unsigned long long total;
|
||||
|
||||
t = rTCNTO1;
|
||||
/*
|
||||
* Total is calculated by taking into account the number of timer overflow
|
||||
* interrupts since the timer was initialized and clicks since the last
|
||||
* interrupts.
|
||||
*/
|
||||
|
||||
total = (g_start - t);
|
||||
|
||||
/* convert to microseconds */
|
||||
total = (total*1000) / g_freq;
|
||||
|
||||
if ( Timer_driver_Find_average_overhead == 1 ) {
|
||||
return (int) total;
|
||||
} else if ( total < LEAST_VALID ) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Somehow convert total into microseconds
|
||||
*/
|
||||
return (total - AVG_OVERHEAD);
|
||||
}
|
||||
|
||||
/*
|
||||
* Empty function call used in loops to measure basic cost of looping
|
||||
* in Timing Test Suite.
|
||||
*/
|
||||
|
||||
rtems_status_code Empty_function( void )
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void Set_find_average_overhead(
|
||||
rtems_boolean find_flag
|
||||
)
|
||||
{
|
||||
Timer_driver_Find_average_overhead = find_flag;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user