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2008-09-03 Joel Sherrill <joel.sherrill@OARcorp.com>

Browse Source 
* Makefile.am, README, configure.ac, console/85c30.c,
	console/console.c, console/consolebsp.h, include/bsp.h,
	include/gen2.h, irq/FPGA.c, irq/irq.c, irq/irq.h, irq/irq_init.c,
	start/start.S, startup/bspstart.c, startup/genpvec.c,
	startup/linkcmds, timer/timer.c, tod/tod.c: Initiate update and
	testing. Runs hello but does not run ticker yet.
This commit is contained in:
Joel Sherrill
2008-09-03 20:36:21 +00:00
parent e36390a662
commit 40e7ae2296
19 changed files with 389 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
c/src/lib/libbsp/powerpc/score603e/ChangeLog
View File

@@ -1,3 +1,12 @@
2008-09-03 Joel Sherrill <joel.sherrill@OARcorp.com>
* Makefile.am, README, configure.ac, console/85c30.c,
console/console.c, console/consolebsp.h, include/bsp.h,
include/gen2.h, irq/FPGA.c, irq/irq.c, irq/irq.h, irq/irq_init.c,
start/start.S, startup/bspstart.c, startup/genpvec.c,
startup/linkcmds, timer/timer.c, tod/tod.c: Initiate update and
testing. Runs hello but does not run ticker yet.
2008-08-31 Joel Sherrill <joel.sherrill@oarcorp.com>
* timer/timer.c: Eliminate empty function from every benchmark timer

20
c/src/lib/libbsp/powerpc/score603e/Makefile.am
View File

@@ -28,20 +28,26 @@ dist_project_lib_DATA += startup/linkcmds
startup_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \
startup/bspstart.c ../../shared/bootcard.c \
../../shared/sbrk.c startup/Hwr_init.c \
startup/genpvec.c ../../shared/gnatinstallhandler.c
startup/genpvec.c ../../shared/gnatinstallhandler.c \
../../powerpc/shared/showbats.c
pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
console_SOURCES = console/85c30.c console/85c30.h console/console.c \
console/tbl85c30.c console/consolebsp.h
include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
PCI_bus/PCI.h \
../../powerpc/shared/residual/residual.h \
../../powerpc/shared/residual/pnp.h \
../../powerpc/shared/openpic/openpic.h \
../../powerpc/shared/console/consoleIo.h
pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
../../powerpc/shared/pci/pcifinddevice.c
../../powerpc/shared/pci/pcifinddevice.c PCI_bus/PCI.c PCI_bus/universe.c
include_bsp_HEADERS += irq/irq.h
include_bsp_HEADERS += irq/irq.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
irq_SOURCES = irq/FPGA.c irq/irq.c ../../powerpc/shared/irq/irq_asm.S
include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
@@ -56,11 +62,10 @@ include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
../../shared/vmeUniverse/vmeUniverseDMA.h\
../../shared/vmeUniverse/bspVmeDmaList.h\
../../shared/vmeUniverse/VMEDMA.h
vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \
vme_SOURCES = \
../../shared/vmeUniverse/bspVmeDmaList.c \
../../shared/vmeUniverse/vme_am_defs.h \
../shared/vme/vmeconfig.c \
../shared/vme/vme_universe.c
../shared/vme/vmeconfig.c
EXTRA_DIST = start/start.S
start.$(OBJEXT): start/start.S
@@ -81,8 +86,9 @@ libbsp_a_LIBADD = \
../../../libcpu/@RTEMS_CPU@/shared/stack.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
include $(srcdir)/preinstall.am

10
c/src/lib/libbsp/powerpc/score603e/README
View File

@@ -42,13 +42,15 @@ STOP BITS: 1
Notes
=====
This BSP has been modified to use the latest exception model.
However, the modifications were never verified. This version
has been partially verified in that Hello.ralf will load and
run on the board.
This BSP has been tested using any Rom monitor. There have
This BSP has been tested using DINK Rom monitor. There have
been three rom chips loaded on the boards. One with the SDS
debug monitor, one with the firmworks monitor, and one with
the OAR Boot chip. The OAR Boot chip contains the basic
initialization from the SDS debugger and a jump to flash
location 0x04001200.
the DINK monitor.
The SCORE603e first generation board is no longer available,
does not appear to be in use by any RTEMS users, and thus

29
c/src/lib/libbsp/powerpc/score603e/configure.ac
View File

@@ -37,6 +37,35 @@ RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
[whether using console interrupts])
RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[1])
RTEMS_BSPOPTS_HELP([HAS_PMC_PSC8],
[whether has a PSC8 PMC board attached to PMC slot])
RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
[FIXME: Missing explanation])
RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
[If defined, then the PowerPC specific code in RTEMS will use some
of the special purpose registers to slightly optimize interrupt
response time. The use of these registers can conflict with
other tools like debuggers.])
RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
[If defined, then the PowerPC specific code in RTEMS will use
data cache instructions to optimize the context switch code.
This code can conflict with debuggers or emulators. It is known
to break the Corelis PowerPC emulator with at least some combinations
of PowerPC 603e revisions and emulator versions.
The BSP actually contains the call that enables this.])
RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
[This defines the base address of the exception table.
NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
RTEMS_CHECK_NETWORKING
AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")

27
c/src/lib/libbsp/powerpc/score603e/console/85c30.c
View File

@@ -4,7 +4,7 @@
*
* Currently only polled mode is supported.
*
* COPYRIGHT (c) 1989-1997.
* COPYRIGHT (c) 1989-2008.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
@@ -94,9 +94,7 @@ static void Write_85c30_register(
*csr = register_number;
rtems_bsp_delay_in_bus_cycles( 40 );
*csr = data;
rtems_bsp_delay_in_bus_cycles( 40 );
}
@@ -131,6 +129,8 @@ void initialize_85c30_port(
Console_Protocol *Setup;
uint16_t baud_constant;
printk("initialize_85c30_port start\n");
Setup = Port->Protocol;
ctrl = Port->ctrl;
@@ -155,17 +155,20 @@ void initialize_85c30_port(
/*
* Set Write Register 2 to contain the interrupt vector
*/
printk("initialize_85c30_port 2, %d\n", Port->Chip->vector );
Write_85c30_register( ctrl, 2, Port->Chip->vector );
#endif
/*
* Set Write Register 3 to disable the Receiver
*/
printk("initialize_85c30_port 0x03, 0x00\n");
Write_85c30_register( ctrl, 0x03, 0x00 );
/*
* Set Write Register 5 to disable the Transmitter
*/
printk("initialize_85c30_port 5, 0x00\n");
Write_85c30_register( ctrl, 5, 0x00 );
/* WR 6 -- unneeded in asynchronous mode */
@@ -175,11 +178,13 @@ void initialize_85c30_port(
/*
* Set Write Register 9 to disable all interrupt sources
*/
printk("initialize_85c30_port 9, 0x00\n");
Write_85c30_register( ctrl, 9, 0x00 );
/*
* Set Write Register 10 for simple Asynchronous operation
*/
printk("initialize_85c30_port 0x0a, 0x00\n");
Write_85c30_register( ctrl, 0x0a, 0x00 );
/*
@@ -187,6 +192,7 @@ void initialize_85c30_port(
* clock as BRG output and the transmit clock
* as the output source for TRxC pin via register 11
*/
printk("initialize_85c30_port 0x0b, 0x56\n");
Write_85c30_register( ctrl, 0x0b, 0x56 );
value = baud_constant;
@@ -196,12 +202,14 @@ void initialize_85c30_port(
* If the time constans = 1E, then the desire
* baud rate will be equilvalent to 9600, via register 12.
*/
printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff);
Write_85c30_register( ctrl, 0x0c, value & 0xff );
/*
* using register 13
* Setup the upper 8 bits time constants = 0
*/
printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8);
Write_85c30_register( ctrl, 0x0d, value>>8 );
/*
@@ -210,6 +218,7 @@ void initialize_85c30_port(
* rate generator enable with clock from the
* SCC's PCLK input via register 14.
*/
printk("initialize_85c30_port 0x0e, 0x07\n");
Write_85c30_register( ctrl, 0x0e, 0x07 );
/*
@@ -225,6 +234,7 @@ void initialize_85c30_port(
value = 0x01;
value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
printk("initialize_85c30_port 0x03, 0x%x\n", value);
Write_85c30_register( ctrl, 0x03, value );
/*
@@ -239,18 +249,21 @@ void initialize_85c30_port(
*/
value = 0x8a;
value = value | Char_size_85c30[ Setup->write_char_bits ].write_setup;
printk("initialize_85c30_port 0x05, 0x%x\n", value);
Write_85c30_register( ctrl, 0x05, value );
/*
* Reset Tx UNDERRUN/EOM LATCH and ERROR
* via register 0
*/
printk("initialize_85c30_port 0x00, 0xf0\n");
Write_85c30_register( ctrl, 0x00, 0xf0 );
#if CONSOLE_USE_INTERRUPTS
/*
* Set Write Register 1 to interrupt on Rx characters or special condition.
*/
printk("initialize_85c30_port 1, 0x10\n");
Write_85c30_register( ctrl, 1, 0x10 );
#endif
@@ -258,11 +271,13 @@ void initialize_85c30_port(
* Set Write Register 15 to disable extended functions.
*/
printk("initialize_85c30_port 15, 0x00\n");
Write_85c30_register( ctrl, 15, 0x00 );
/*
* Set the Command Register to Reset Ext/STATUS.
*/
printk("initialize_85c30_port 0x00, 0x10\n");
Write_85c30_register( ctrl, 0x00, 0x10 );
#if CONSOLE_USE_INTERRUPTS
@@ -273,12 +288,14 @@ void initialize_85c30_port(
* Enables parity as a special condition.
* Enables Tx interrupt.
*/
printk("initialize_85c30_port 1, 0x16\n");
Write_85c30_register( ctrl, 1, 0x16 );
/*
* Set Write Register 9 to enable all interrupt sources
* Changed from 0 to a
*/
printk("initialize_85c30_port 9, 0x0A\n");
Write_85c30_register( ctrl, 9, 0x0A );
/* XXX */
@@ -286,10 +303,12 @@ void initialize_85c30_port(
/*
* Issue reset highest Interrupt Under Service (IUS) command.
*/
printk("initialize_85c30_port STATUS_REGISTER, 0X38\n");
Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
#endif
printk("initialize_85c30_port end of method\n");
}
/* PAGE
@@ -377,7 +396,7 @@ rtems_isr ISR_85c30_Async(
uint16_t status;
volatile Console_Protocol *Protocol;
unsigned char data;
rtems_boolean did_something = FALSE;
bool did_something = FALSE;
Protocol = Port->Protocol;

16
c/src/lib/libbsp/powerpc/score603e/console/console.c
View File

@@ -210,6 +210,8 @@ rtems_device_driver console_initialize(
rtems_device_minor_number console;
int port, chip, p0,p1;
printk("console_initialize start\n");
/*
* initialize the termio interface.
*/
@@ -264,15 +266,18 @@ rtems_device_driver console_initialize(
* 2,3 are on the second ....
*/
for (port=0; port<NUM_Z85C30_PORTS; port++) {
chip = port >> 1;
for (port=1; port<NUM_Z85C30_PORTS; port++) {
chip = port >> 1;
printk("console_initialize initialize_85c30_port %d\n", port);
initialize_85c30_port( &Ports_85C30[port] );
}
#if CONSOLE_USE_INTERRUPTS
printk("console_initialize console_initialize_interrupts\n");
console_initialize_interrupts();
#endif
printk("console_initialize end\n");
return RTEMS_SUCCESSFUL;
}
@@ -441,6 +446,13 @@ debug_putc_onlcr(const char c)
console = USE_FOR_CONSOLE;
csr = Ports_85C30[ console ].ctrl;
if ('\n'==c){
rtems_interrupt_disable( isrlevel );
outbyte_polled_85c30( csr, '\r' );
rtems_interrupt_enable( isrlevel );
asm volatile("isync");
}
rtems_interrupt_disable( isrlevel );
outbyte_polled_85c30( csr, c );
rtems_interrupt_enable( isrlevel );

4
c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h
View File

@@ -17,6 +17,7 @@
#include <rtems.h>
#include <rtems/ringbuf.h>
#include <bsp.h>
#ifdef __cplusplus
extern "C" {
@@ -34,6 +35,7 @@ extern "C" {
*/
#if (HAS_PMC_PSC8)
#warning "HAS_PMC_PSC8 is Defined"
#define NUM_Z85C30_CHIPS_ON_MEZZANINE 4
#else
#define NUM_Z85C30_CHIPS_ON_MEZZANINE 0
@@ -77,7 +79,7 @@ typedef struct {
#if CONSOLE_USE_INTERRUPTS
volatile Ring_buffer_t TX_Buffer; /* Transmit Buffer */
volatile rtems_boolean Is_TX_active; /* Transmitting */
volatile bool Is_TX_active; /* Transmitting */
void *console_termios_data;
#endif

2
c/src/lib/libbsp/powerpc/score603e/include/bsp.h
View File

@@ -188,7 +188,7 @@ uint16_t read_and_clear_PMC_irq(
uint16_t irq
);
rtems_boolean Is_PMC_IRQ(
bool Is_PMC_IRQ(
uint32_t pmc_irq,
uint16_t status_word
);

34
c/src/lib/libbsp/powerpc/score603e/include/gen2.h
View File

@@ -60,27 +60,27 @@ extern "C" {
#define BSP_PMC_SERIAL_ADDRESS( _offset ) \
((volatile uint8_t *)(BSP_PCI_REGISTER_BASE + _offset))
((volatile uint8_t*)(BSP_PCI_REGISTER_BASE + _offset))
/*
* PMC serial channels - (4-7: 232 and 8-11: 422)
*/
#define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x200020)
#define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x200024)
#define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x200028)
#define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x20002c)
#define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x200030)
#define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x200034)
#define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x200038)
#define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x20003c)
#define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x200000)
#define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x200004)
#define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x200008)
#define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x20000c)
#define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x200010)
#define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x200014)
#define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x200018)
#define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x20001c)
#define SCORE603E_85C30_CTRL_4 BSP_PMC_SERIAL_ADDRESS(0x00200020)
#define SCORE603E_85C30_DATA_4 BSP_PMC_SERIAL_ADDRESS(0x00200024)
#define SCORE603E_85C30_CTRL_5 BSP_PMC_SERIAL_ADDRESS(0x00200028)
#define SCORE603E_85C30_DATA_5 BSP_PMC_SERIAL_ADDRESS(0x0020002c)
#define SCORE603E_85C30_CTRL_6 BSP_PMC_SERIAL_ADDRESS(0x00200030)
#define SCORE603E_85C30_DATA_6 BSP_PMC_SERIAL_ADDRESS(0x00200034)
#define SCORE603E_85C30_CTRL_7 BSP_PMC_SERIAL_ADDRESS(0x00200038)
#define SCORE603E_85C30_DATA_7 BSP_PMC_SERIAL_ADDRESS(0x0020003c)
#define SCORE603E_85C30_CTRL_8 BSP_PMC_SERIAL_ADDRESS(0x00200000)
#define SCORE603E_85C30_DATA_8 BSP_PMC_SERIAL_ADDRESS(0x00200004)
#define SCORE603E_85C30_CTRL_9 BSP_PMC_SERIAL_ADDRESS(0x00200008)
#define SCORE603E_85C30_DATA_9 BSP_PMC_SERIAL_ADDRESS(0x0020000c)
#define SCORE603E_85C30_CTRL_10 BSP_PMC_SERIAL_ADDRESS(0x00200010)
#define SCORE603E_85C30_DATA_10 BSP_PMC_SERIAL_ADDRESS(0x00200014)
#define SCORE603E_85C30_CTRL_11 BSP_PMC_SERIAL_ADDRESS(0x00200018)
#define SCORE603E_85C30_DATA_11 BSP_PMC_SERIAL_ADDRESS(0x0020001c)
#define _IO_BASE PREP_ISA_IO_BASE
#define SCORE603E_PCI_IO_CFG_ADDR 0x80000cf8

4
c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c
View File

@@ -120,12 +120,12 @@ uint16_t read_and_clear_PMC_irq(
return status_word;
}
rtems_boolean Is_PMC_IRQ(
bool Is_PMC_IRQ(
uint32_t pmc_irq,
uint16_t status_word
)
{
rtems_boolean result= FALSE;
bool result = FALSE;
switch(pmc_irq) {
case SCORE603E_85C30_4_IRQ:

12
c/src/lib/libbsp/powerpc/score603e/irq/irq.c
View File

@@ -89,6 +89,8 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data* irq)
rtems_interrupt_level level;
rtems_irq_connect_data* vchain;
printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
@@ -145,6 +147,8 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
printk("Invalid interrupt vector %d\n",irq->name);
return 0;
@@ -196,6 +200,7 @@ int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
{
rtems_interrupt_level level;
printk(" BSP_get_current_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -210,6 +215,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
rtems_interrupt_level level;
printk(" BSP_remove_rtems_irq_handler %d\n", irq->name );
if (!isValidInterrupt(irq->name)) {
return 0;
}
@@ -319,6 +325,8 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
default_rtems_entry = config->defaultEntry;
rtems_hdl_tbl = config->irqHdlTbl;
printk(" BSP_rtems_irq_mngt_set\n");
rtems_interrupt_disable(level);
/*
* set up internal tables used by rtems interrupt prologue
@@ -397,6 +405,7 @@ int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
}
unsigned BSP_spuriousIntr = 0;
/*
* High level IRQ handler called from shared_raw_irq_code_entry
*/
@@ -406,6 +415,7 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
register unsigned msr;
register unsigned new_msr;
printk(" C_dispatch_irq_handler %d\n", excNum);
if (excNum == ASM_DEC_VECTOR) {
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
@@ -417,6 +427,7 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
return 0;
}
irq = read_and_clear_irq();
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
@@ -440,6 +451,7 @@ int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
{
printk(" _ThreadProcessSignalsFromIrq \n");
/*
* Process pending signals that have not already been
* processed by _Thread_Displatch. This happens quite

141
c/src/lib/libbsp/powerpc/score603e/irq/irq.h
View File

@@ -18,8 +18,8 @@
* $Id$
*/
#ifndef LIBBSP_POWERPC_IRQ_H
#define LIBBSP_POWERPC_IRQ_H
#ifndef BSP_POWERPC_IRQ_H
#define BSP_POWERPC_IRQ_H
#define BSP_SHARED_HANDLER_SUPPORT 1
#include <rtems/irq.h>
@@ -65,54 +65,131 @@ extern "C" {
#endif
/*
* Symbolic IRQ names and related definitions
* rtems_irq_number Definitions
*/
/*
* ISA IRQ handler related definitions
*/
/*
* ISA IRQ handler related definitions
*/
#define BSP_ISA_IRQ_NUMBER (16)
#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET+BSP_ISA_IRQ_NUMBER-1)
/*
* PCI IRQ handlers related definitions
* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
*/
#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
/*
* PCI IRQ handlers related definitions
* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
*/
#define BSP_PCI_IRQ_NUMBER (16)
#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
/*
* PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
* handler might be connected
*/
#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
/*
* PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
* handler might be connected
*/
#define BSP_PROCESSOR_IRQ_NUMBER (1)
#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
/* Misc vectors for OPENPIC irqs (IPI, timers)
*/
#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
/* Misc vectors for OPENPIC irqs (IPI, timers)
*/
#define BSP_MISC_IRQ_NUMBER (8)
#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
/*
* Summary
*/
#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
/*
* Summary
*/
#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
/*
* Some PCI IRQ symbolic name definition
*/
#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
/*
* Some ISA IRQ symbolic name definition
*/
#define BSP_ISA_PERIODIC_TIMER (0)
#define BSP_ISA_KEYBOARD (1)
#define BSP_ISA_UART_COM2_IRQ (3)
#define BSP_ISA_UART_COM1_IRQ (4)
#define BSP_ISA_RT_TIMER1 (8)
#define BSP_ISA_RT_TIMER3 (10)
/*
* Some PCI IRQ symbolic name definition
*/
#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET)
#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
/*
* Some Processor execption handled as RTEMS IRQ symbolic name definition
*/
#if defined(mvme2100)
#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
#else
#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ
#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ
#endif
/*
* Some Processor execption handled as RTEMS IRQ symbolic name definition
*/
#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
/*
* Type definition for RTEMS managed interrupts
*/
typedef unsigned short rtems_i8259_masks;
extern volatile rtems_i8259_masks i8259s_cache;
/*-------------------------------------------------------------------------+
| Function Prototypes.
+--------------------------------------------------------------------------*/
/*
* ------------------------ Intel 8259 (or emulation) Mngt Routines -------
*/
void BSP_i8259s_init(void);
/*
* function to disable a particular irq at 8259 level. After calling
* this function, even if the device asserts the interrupt line it will
* not be propagated further to the processor
*
* RETURNS: 1/0 if the interrupt was enabled/disabled originally or
* a value < 0 on error.
*/
int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine);
/*
* function to enable a particular irq at 8259 level. After calling
* this function, if the device asserts the interrupt line it will
* be propagated further to the processor
*/
int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine);
/*
* function to acknowledge a particular irq at 8259 level. After calling
* this function, if a device asserts an enabled interrupt line it will
* be propagated further to the processor. Mainly usefull for people
* writing raw handlers as this is automagically done for RTEMS managed
* handlers.
*/
int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine);
/*
* function to check if a particular irq is enabled at 8259 level. After calling
*/
int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine);
extern void BSP_rtems_irq_mng_init(unsigned cpuId);
extern void BSP_i8259s_init(void);
/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
/* #include <bsp/irq_supp.h> */
#ifdef __cplusplus
}
};
#endif
#endif
#endif

4
c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c
View File

@@ -29,6 +29,10 @@
#include <bsp/motorola.h>
#include <rtems/bspIo.h>
#define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
#define SCAN_PCI_PRINT 1
#define TRACE_IRQ_INIT 1
typedef struct {
unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */
unsigned char device;

4
c/src/lib/libbsp/powerpc/score603e/start/start.S
View File

@@ -104,6 +104,10 @@ past_constants:
mr sp,r0 /* use user defined stack */
.Lnostack:
lis r13,_SDA_BASE_@ha
la r13,_SDA_BASE_@l(r13) /* Read-write small data */
/* set up initial stack frame */
addi sp,sp,-4 /* make sure we don't overwrite debug mem */
lis r0,0

140
c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
View File

@@ -21,6 +21,13 @@
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <rtems/bspIo.h>
#include <libcpu/cpuIdent.h>
#define DEBUG 1
/*
* Where the heap starts; is used by bsp_pretasking_hook;
*/
unsigned int BSP_heap_start;
/*
* PCI Bus Frequency
@@ -37,6 +44,14 @@ unsigned int BSP_processor_frequency; /* XXX - Set this based upon the Score boa
*/
unsigned int BSP_time_base_divisor = 1000; /* XXX - Just a guess */
/*
* system init stack
*/
#define INIT_STACK_SIZE 0x1000
extern unsigned long __rtems_end[];
/*
* Driver configuration parameters
*/
@@ -75,6 +90,9 @@ void bsp_pretasking_hook(void)
uint32_t heap_start;
uint32_t heap_size;
#if DEBUG
printk("bsp_pretasking_hook: Set Heap\n");
#endif
heap_start = (uint32_t) &end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
@@ -82,7 +100,13 @@ void bsp_pretasking_hook(void)
heap_size = Configuration.work_space_start - (void *)&end;
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
#if DEBUG
printk("bsp_pretasking_hook: bsp_libc_init\n");
#endif
bsp_libc_init((void *) heap_start, heap_size, 0);
#if DEBUG
printk("bsp_pretasking_hook: End of routine\n");
#endif
}
/*PAGE
@@ -97,31 +121,52 @@ void initialize_PMC();
void bsp_predriver_hook(void)
{
#if DEBUG
printk("bsp_predriver_hook: init_RTC\n");
#endif
init_RTC();
/* XXX - What Does this now ????
init_PCI();
initialize_universe();
*/
#if DEBUG
printk("bsp_predriver_hook: initialize_PCI_bridge\n");
#endif
initialize_PCI_bridge ();
#if (HAS_PMC_PSC8)
#if DEBUG
printk("bsp_predriver_hook: initialize_PMC\n");
#endif
initialize_PMC();
#endif
#if 0
/*
* Initialize Bsp General purpose vector table.
*/
#if DEBUG
printk("bsp_predriver_hook: initialize_external_exception_vector\n");
#endif
initialize_external_exception_vector();
#endif
#if (0)
/*
* XXX - Modify this to write a 48000000 (loop to self) command
* to each interrupt location. This is better for debug.
*/
#if DEBUG
printk("bsp_predriver_hook: bsp_spurious_initialize\n");
#endif
bsp_spurious_initialize();
#endif
ShowBATS();
#if DEBUG
printk("bsp_predriver_hook: End of routine\n");
#endif
}
/*PAGE
@@ -162,16 +207,27 @@ void initialize_PMC() {
/*
* Clear status, enable SERR and memory space only.
*/
#if DEBUG
printk("initialize_PMC: set Device Address 0x4 \n");
ShowBATS();
#endif
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x020080cc;
/*
* set PMC base address.
*/
#if DEBUG
printk("initialize_PMC: set Device Address 0x14 \n");
ShowBATS();
#endif
PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
PMC_addr = (volatile uint32_t*)
#if DEBUG
printk("initialize_PMC: set PMC Serial Address 0x100000\n");
#endif
PMC_addr = (volatile uint32_t*)
BSP_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
*PMC_addr = data & 0xfc;
@@ -191,9 +247,20 @@ void bsp_postdriver_hook(void)
extern void Init_EE_mask_init(void);
extern void open_dev_console(void);
#if DEBUG
printk("bsp_postdriver_hook: open_dev_console\n");
#endif
open_dev_console();
ShowBATS();
#if DEBUG
printk("bsp_postdriver_hook: Init_EE_mask_init\n");
#endif
Init_EE_mask_init();
ShowBATS();
#if DEBUG
printk("bsp_postdriver_hook: Finished procedure\n");
#endif
}
void bsp_set_trap_vectors( void );
@@ -209,13 +276,21 @@ void bsp_start( void )
{
unsigned char *work_space_start;
unsigned int msr_value = 0x0000;
uint32_t intrStackStart;
uint32_t intrStackSize;
volatile uint32_t *ptr;
ppc_cpu_id_t myCpu;
ppc_cpu_revision_t myCpuRevision;
rtems_bsp_delay( 1000 );
/*
* Zero out lots of memory
*/
#if DEBUG
printk("bsp_start: Zero out lots of memory\n");
ShowBATS();
#endif
memset(
&end,
@@ -226,10 +301,39 @@ void bsp_start( void )
BSP_processor_frequency = 266000000;
BSP_bus_frequency = 66000000;
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
* later...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
/*
* Initialize the interrupt related settings.
*/
intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
intrStackSize = rtems_configuration_get_interrupt_stack_size();
BSP_heap_start = intrStackStart + intrStackSize;
/*
* Initialize default raw exception handlers.
*/
printk("ppc_exc_initialize\n");
ppc_exc_initialize(
PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
intrStackStart,
intrStackSize
);
/*
* There are multiple ROM monitors available for this board.
*/
#if (SCORE603E_USE_SDS)
#if DEBUG
printk("bsp_start: USE SDS\n");
#endif
/*
* Write instruction for Unconditional Branch to ROM vector.
@@ -251,14 +355,23 @@ void bsp_start( void )
msr_value = 0x2030;
#elif (SCORE603E_USE_OPEN_FIRMWARE)
#if DEBUG
printk("bsp_start: USE OPEN FIRMWARE\n");
#endif
msr_value = 0x2030;
#elif (SCORE603E_USE_NONE)
#if DEBUG
printk("bsp_start: USE NONE\n");
#endif
msr_value = 0x2030;
_CPU_MSR_SET( msr_value );
bsp_set_trap_vectors();
#elif (SCORE603E_USE_DINK)
#if DEBUG
printk("bsp_start: USE DINK\n");
#endif
msr_value = 0x2030;
_CPU_MSR_SET( msr_value );
@@ -270,6 +383,9 @@ void bsp_start( void )
*ptr = 0x4c000064;
#else
#if DEBUG
printk("bsp_start: ERROR unknow ROM Monitor\n");
#endif
#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
#endif
@@ -281,6 +397,9 @@ void bsp_start( void )
* not malloc'ed. It is just "pulled from the air".
*/
#if DEBUG
printk("bsp_start: Calculate Wrokspace\n");
#endif
work_space_start =
(unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
@@ -294,10 +413,23 @@ void bsp_start( void )
/*
* initialize the device driver parameters
*/
#if DEBUG
printk("bsp_start: set clicks poer usec\n");
#endif
bsp_clicks_per_usec = 66 / 4; /* XXX get from linkcmds */
#if ( PPC_USE_DATA_CACHE )
#if DEBUG
printk("bsp_start: cache_enable\n");
#endif
instruction_cache_enable ();
data_cache_enable ();
#if DEBUG
printk("bsp_start: END PPC_USE_DATA_CACHE\n");
#endif
#endif
#if DEBUG
printk("bsp_start: end BSPSTART\n");
ShowBATS();
#endif
}

4
c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c
View File

@@ -52,6 +52,7 @@ typedef struct
/* XXX */
void init_irq_data_register(void);
#if 0
void initialize_external_exception_vector (void)
{
int i;
@@ -76,6 +77,7 @@ void initialize_external_exception_vector (void)
status = rtems_interrupt_catch( external_exception_ISR,
PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr );
}
#endif
void Init_EE_mask_init() {
;
@@ -164,7 +166,7 @@ rtems_isr external_exception_ISR (
node = (EE_ISR_Type *)(ISR_Array[ index ].first);
if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
printk"ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
printk ("ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
value = get_irq_mask();
printk(" Mask = %02x\n", value);
}

1
c/src/lib/libbsp/powerpc/score603e/startup/linkcmds
View File

@@ -193,6 +193,7 @@ SECTIONS
. = ALIGN(8) + 0x8000;
PROVIDE (__stack = .);
_end = . ;
__rtems_end = . ;
PROVIDE (end = .);
} >RAM

4
c/src/lib/libbsp/powerpc/score603e/timer/timer.c
View File

@@ -23,7 +23,7 @@
uint64_t Timer_driver_Start_time;
rtems_boolean benchmark_timer_find_average_overhead;
bool benchmark_timer_find_average_overhead;
/*
* benchmark_timer_initialize
@@ -71,7 +71,7 @@ int benchmark_timer_read()
}
void benchmark_timer_disable_subtracting_average_overhead(
rtems_boolean find_flag
bool find_flag
)
{
benchmark_timer_find_average_overhead = find_flag;

2
c/src/lib/libbsp/powerpc/score603e/tod/tod.c
View File

@@ -107,7 +107,7 @@ void ICM7170_GetTOD(
{
int year;
int usec;
static rtems_boolean init = TRUE;
static bool init = TRUE;
/* Initialize the clock at once prior to reading */
if (init ) {