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2007-09-12 Joel Sherrill <joel.sherrill@OARcorp.com>

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PR 1257/bsps
	* sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/score/cpu_asm.c,
	sh7045/timer/timer.c, sh7750/score/cpu_asm.c, sh7750/timer/timer.c:
	Code outside of cpukit should use the public API for
	rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the
	public API and directly accessing _CPU_ISR_Disable and
	_CPU_ISR_Enable, they were bypassing the compiler memory barrier
	directive which could lead to problems. This patch also changes the
	type of the variable passed into these routines and addresses minor
	style issues.
This commit is contained in:
Joel Sherrill
2007-09-12 15:23:49 +00:00
parent f93630db63
commit 3d7fa72bc2
7 changed files with 106 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
c/src/lib/libcpu/sh/ChangeLog
View File

@@ -1,3 +1,16 @@
2007-09-12 Joel Sherrill <joel.sherrill@OARcorp.com>
PR 1257/bsps
* sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/score/cpu_asm.c,
sh7045/timer/timer.c, sh7750/score/cpu_asm.c, sh7750/timer/timer.c:
Code outside of cpukit should use the public API for
rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the
public API and directly accessing _CPU_ISR_Disable and
_CPU_ISR_Enable, they were bypassing the compiler memory barrier
directive which could lead to problems. This patch also changes the
type of the variable passed into these routines and addresses minor
style issues.
2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org>
* sh7032/score/cpu_asm.c, sh7045/score/cpu_asm.c,

30
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
View File

@@ -68,10 +68,10 @@ unsigned int sh_set_irq_priority(
unsigned int irq,
unsigned int prio )
{
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
uint32_t level;
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
ISR_Level level;
/*
* first check for valid interrupt
@@ -112,14 +112,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
_CPU_ISR_Disable( level );
_ISR_Disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_CPU_ISR_Enable( level );
_ISR_Enable( level );
return 0;
}
@@ -257,9 +257,9 @@ asm volatile(
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
ISR_Level level;
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
@@ -275,13 +275,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level--;
@@ -294,7 +294,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
_ISR_Enable( level );
if ( _ISR_Nest_level )
return;

54
c/src/lib/libcpu/sh/sh7032/timer/timer.c
View File

@@ -72,10 +72,10 @@ static uint32_t Timer_HZ ;
void Timer_initialize( void )
{
uint8_t temp8;
uint16_t temp16;
uint32_t level;
rtems_isr *ignored;
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
Timer_HZ = rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE ;
@@ -85,51 +85,51 @@ void Timer_initialize( void )
*/
Timer_interrupts /* .i */ = 0;
_CPU_ISR_Disable( level);
rtems_interrupt_disable( level );
/*
* Somehow start the timer
*/
/* stop Timer 1 */
temp8 = read8( ITU_TSTR) & ITU1_STARTMASK;
write8( temp8, ITU_TSTR);
temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
write8( temp8, ITU_TSTR );
/* initialize counter 1 */
write16( 0, ITU_TCNT1);
write16( 0, ITU_TCNT1 );
/* Timer 1 is independent of other timers */
temp8 = read8( ITU_TSNC) & ITU1_SYNCMASK;
write8( temp8, ITU_TSNC);
temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
write8( temp8, ITU_TSNC );
/* Timer 1, normal mode */
temp8 = read8( ITU_TMDR) & ITU1_MODEMASK;
write8( temp8, ITU_TMDR);
temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
write8( temp8, ITU_TMDR );
/* Use a Phi/X counter */
write8( ITU1_TCRMASK, ITU_TCR1);
write8( ITU1_TCRMASK, ITU_TCR1 );
/* gra and grb are not used */
write8( ITU1_TIORMASK, ITU_TIOR1);
write8( ITU1_TIORMASK, ITU_TIOR1 );
/* reset all status flags */
temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1);
temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1 );
/* enable overflow interrupt */
write8( ITU1_TIERMASK, ITU_TIER1);
write8( ITU1_TIERMASK, ITU_TIER1 );
/* set interrupt priority */
temp16 = read16( INTC_IPRC) & IPRC_ITU1_MASK;
temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
temp16 |= ITU1_PRIO;
write16( temp16, INTC_IPRC);
write16( temp16, INTC_IPRC );
/* initialize ISR */
_CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
_CPU_ISR_Enable( level);
rtems_interrupt_enable( level );
/* start timer 1 */
temp8 = read8( ITU_TSTR) | ~ITU1_STARTMASK;
write8( temp8, ITU_TSTR);
temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
write8( temp8, ITU_TSTR );
}
/*
@@ -156,7 +156,7 @@ int Read_timer( void )
*/
cclicks = read16( ITU_TCNT1); /* XXX: read some HW here */
cclicks = read16( ITU_TCNT1 ); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
@@ -164,7 +164,7 @@ int Read_timer( void )
* interrupts.
*/
total = cclicks + Timer_interrupts * 65536 ;
total = cclicks + Timer_interrupts * 65536;
if ( Timer_driver_Find_average_overhead )
return total / CLOCK_SCALE; /* in XXX microsecond units */
@@ -175,7 +175,7 @@ int Read_timer( void )
/*
* Somehow convert total into microseconds
*/
return (total / CLOCK_SCALE - AVG_OVERHEAD) ;
return (total / CLOCK_SCALE - AVG_OVERHEAD);
}
}
@@ -204,8 +204,8 @@ void timerisr( void )
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1);
temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
write8( temp8, ITU_TSR1 );
Timer_interrupts += 1;
}

24
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
View File

@@ -70,7 +70,7 @@ unsigned int sh_set_irq_priority(
uint32_t shiftcount;
uint32_t prioreg;
uint16_t temp16;
uint32_t level;
ISR_Level level;
/*
* first check for valid interrupt
@@ -114,14 +114,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
_CPU_ISR_Disable( level );
_ISR_Disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
_CPU_ISR_Enable( level );
_ISR_Enable( level );
return 0;
}
@@ -259,9 +259,9 @@ __CPU_Context_restore:\n\
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
ISR_Level level;
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
@@ -277,13 +277,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level--;
@@ -296,7 +296,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
_ISR_Enable( level );
if ( _ISR_Nest_level )
return;

48
c/src/lib/libcpu/sh/sh7045/timer/timer.c
View File

@@ -63,10 +63,10 @@ static uint32_t Timer_MHZ ;
void Timer_initialize( void )
{
uint8_t temp8;
uint16_t temp16;
uint32_t level;
rtems_isr *ignored;
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
@@ -76,25 +76,25 @@ void Timer_initialize( void )
*/
Timer_interrupts /* .i */ = 0;
_CPU_ISR_Disable( level);
rtems_interrupt_disable( level );
/*
* Somehow start the timer
*/
/* stop Timer 1 */
temp8 = read8( MTU_TSTR) & MTU1_STARTMASK;
write8( temp8, MTU_TSTR);
temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
write8( temp8, MTU_TSTR );
/* initialize counter 1 */
write16( 0, MTU_TCNT1);
/* Timer 1 is independent of other timers */
temp8 = read8( MTU_TSYR) & MTU1_SYNCMASK;
write8( temp8, MTU_TSYR);
temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
write8( temp8, MTU_TSYR );
/* Timer 1, normal mode */
temp8 = read8( MTU_TMDR1) & MTU1_MODEMASK;
write8( temp8, MTU_TMDR1);
temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
write8( temp8, MTU_TMDR1 );
/* x0000000
* |||||+++--- Internal Clock
@@ -102,30 +102,30 @@ void Timer_initialize( void )
* |++-------- disable TCNT clear
* +---------- don`t care
*/
write8( MTU1_TCRMASK, MTU_TCR1);
write8( MTU1_TCRMASK, MTU_TCR1 );
/* gra and grb are not used */
write8( MTU1_TIORMASK, MTU_TIOR1);
write8( MTU1_TIORMASK, MTU_TIOR1 );
/* reset all status flags */
temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1);
temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1 );
/* enable overflow interrupt */
write8( MTU1_TIERMASK, MTU_TIER1);
write8( MTU1_TIERMASK, MTU_TIER1 );
/* set interrupt priority */
temp16 = read16( INTC_IPRC) & IPRC_MTU1_MASK;
temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
temp16 |= MTU1_PRIO;
write16( temp16, INTC_IPRC);
/* initialize ISR */
_CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
_CPU_ISR_Enable( level);
rtems_interrupt_enable( level );
/* start timer 1 */
temp8 = read8( MTU_TSTR) | ~MTU1_STARTMASK;
write8( temp8, MTU_TSTR);
temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
write8( temp8, MTU_TSTR );
}
/*
@@ -152,7 +152,7 @@ int Read_timer( void )
*/
clicks = read16( MTU_TCNT1); /* XXX: read some HW here */
clicks = read16( MTU_TCNT1 ); /* XXX: read some HW here */
/*
* Total is calculated by taking into account the number of timer overflow
@@ -160,7 +160,7 @@ int Read_timer( void )
* interrupts.
*/
total = clicks + Timer_interrupts * 65536 ;
total = clicks + Timer_interrupts * 65536;
if ( Timer_driver_Find_average_overhead )
return total / SCALE; /* in XXX microsecond units */
@@ -200,8 +200,8 @@ void timerisr( void )
uint8_t temp8;
/* reset the flags of the status register */
temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1);
temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
write8( temp8, MTU_TSR1 );
Timer_interrupts += 1;
}

10
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
View File

@@ -256,9 +256,9 @@ __CPU_Context_restore:\n\
void __ISR_Handler( uint32_t vector)
{
register uint32_t level;
ISR_Level level;
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level++;
@@ -274,13 +274,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
_CPU_ISR_Enable( level );
_ISR_Enable( level );
/* call isp */
if( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_CPU_ISR_Disable( level );
_ISR_Disable( level );
_Thread_Dispatch_disable_level--;
@@ -293,7 +293,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
_CPU_ISR_Enable( level );
_ISR_Enable( level );
if ( _ISR_Nest_level )
return;

20
c/src/lib/libcpu/sh/sh7750/timer/timer.c
View File

@@ -65,15 +65,15 @@ rtems_boolean Timer_driver_Find_average_overhead;
void
Timer_initialize(void)
{
uint8_t temp8;
uint16_t temp16;
uint8_t temp8;
uint16_t temp16;
rtems_interrupt_level level;
rtems_isr *ignored;
int cpudiv = 1;
int tidiv = 1;
Timer_interrupts = 0;
_CPU_ISR_Disable(level);
rtems_interrupt_disable(level);
/* Get CPU frequency divider from clock unit */
switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC)
@@ -167,7 +167,7 @@ Timer_initialize(void)
write16(temp16, SH7750_IPRA);
_CPU_ISR_Enable(level);
rtems_interrupt_enable(level);
/* Start the Timer 1 */
temp8 = read8(SH7750_TSTR);
@@ -203,20 +203,20 @@ Timer_initialize(void)
int
Read_timer(void)
{
uint32_t clicks;
uint32_t ints;
uint32_t total ;
uint32_t clicks;
uint32_t ints;
uint32_t total;
rtems_interrupt_level level;
uint32_t tcr;
uint32_t tcr;
_CPU_ISR_Disable(level);
rtems_interrupt_disable(level);
clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
tcr = read32(SH7750_TCR1);
ints = Timer_interrupts;
_CPU_ISR_Enable(level);
rtems_interrupt_enable(level);
/* Handle the case when timer overflowed but interrupt was not processed */
if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))